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mcf5307um/d rev. 2.0, 08/2000 mcf5307 coldfire integrated microprocessor users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
?motorola inc., 2000. all rights reserved. coldfire is a registered trademark and digitaldna is a trademark of motorola, inc. i 2 c is a registered trademark of philips semiconductors motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. ?ypical?parameters which may be provided in motorola data sheets and/or specifications c an and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customer? technical experts. motorola does not convey any license under its pate nt rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applic ation in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purch ase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its offi cers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motor ola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1?03?75?140 or 1?00?41?447 japan: motorola japan ltd.; sps, technical information center, 3?0?, minami?zabu. minato?u, tokyo 106?573 japan. 81??440?569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. 852?6668334 technical information center: 1?00?21?274 home page: http://www.motorola.com/semiconductors document comments : fax (512) 895-2638, attn: risc applications engineering world wide web addresses : http://www.motorola.com/powerpc http://www.motorola.com/netcomm http://www.motorola.com/coldfire f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 a part ii part iv part iii 6 glo ind part i overview coldfire core hardware multiply/accumulate (mac) unit local memory debug support sim overview phase-locked loop (pll) i 2 c module interrupt controller chip-select module synchronous/asynchronous dram controller module dma controller module timer module uart modules parallel port (general-purpose i/o) mechanical data signal descriptions bus operation ieee 1149.1 test access port (jtag) electrical specifications part i: mcf5307 processor core part ii: system integration module ( sim) part iv: hardware interface part iii: peripheral module glossary of terms and abbreviations index appendix: memory map b 20 glo ind ind f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview coldfire core hardware multiply/accumulate (mac) unit local memory debug support sim overview phase-locked loop (pll) i 2 c module interrupt controller chip-select module synchronous/asynchronous dram controller module dma controller module timer module uart modules parallel port (general-purpose i/o) mechanical data signal descriptions bus operation ieee 1149.1 test access port (jtag) electrical specifications part i: mcf5307 processor core part ii: system integration module ( sim) part iv: hardware interface part iii: peripheral module glossary of terms and abbreviations index appendix b: memory map 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 a part ii part iv part iii 6 part i 20 glo ind f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents v about this book chapter 1 overview 1.1 features ............................................................................................................... 1-1 1.2 mcf5307 features.............................................................................................. 1-4 1.2.1 process ............................................................................................................ 1-6 1.3 coldfire module description ............................................................................. 1-7 1.3.1 coldfire core ................................................................................................. 1-7 1.3.1.1 instruction fetch pipeline (ifp).................................................................. 1-7 1.3.1.2 operand execution pipeline (oep) ............................................................ 1-7 1.3.1.3 mac module.............................................................................................. 1-7 1.3.1.4 integer divide module................................................................................ 1-7 1.3.1.5 8-kbyte unified cache ............................................................................... 1-8 1.3.1.6 internal 4-kbyte sram ............................................................................. 1-8 1.3.2 dram controller ........................................................................................... 1-8 1.3.3 dma controller.............................................................................................. 1-8 1.3.4 uart modules............................................................................................... 1-8 1.3.5 timer module ................................................................................................. 1-9 1.3.6 i2c module ..................................................................................................... 1-9 1.3.7 system interface ........................................................................................... 1-10 1.3.7.1 external bus interface .............................................................................. 1-10 1.3.7.2 chip selects .............................................................................................. 1-10 1.3.7.3 16-bit parallel port interface .................................................................... 1-10 1.3.7.4 interrupt controller ................................................................................... 1-10 1.3.7.5 jtag......................................................................................................... 1-11 1.3.8 system debug interface................................................................................ 1-11 1.3.9 pll module.................................................................................................. 1-11 1.4 programming model, addressing modes, and instruction set......................... 1-12 1.4.1 programming model ..................................................................................... 1-13 1.4.2 user registers ............................................................................................... 1-14 1.4.3 supervisor registers ..................................................................................... 1-14 1.4.4 instruction set ............................................................................................... 1-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
vi mcf5307 users manual contents paragraph number title page number part i mcf5407 processor core chapter 2 coldfire core 2.1 features and enhancements.............................................................................. 2-21 2.1.1 clock-multiplied microprocessor core........................................................ 2-22 2.1.2 enhanced pipelines ....................................................................................... 2-22 2.1.2.1 instruction fetch pipeline (ifp)................................................................ 2-23 2.1.2.1.1 branch acceleration ............................................................................. 2-23 2.1.2.2 operand execution pipeline (oep) .......................................................... 2-24 2.1.2.2.1 illegal opcode handling....................................................................... 2-24 2.1.2.2.2 hardware multiply/accumulate (mac) unit ...................................... 2-24 2.1.2.2.3 hardware divide unit .......................................................................... 2-25 2.1.3 debug module enhancements ...................................................................... 2-25 2.2 programming model ......................................................................................... 2-26 2.2.1 user programming model ............................................................................ 2-27 2.2.1.1 data registers (d0?d7) ........................................................................... 2-27 2.2.1.2 address registers (a0?a6) ...................................................................... 2-27 2.2.1.3 stack pointer (a7, sp).............................................................................. 2-28 2.2.1.4 program counter (pc) .............................................................................. 2-28 2.2.1.5 condition code register (ccr)............................................................... 2-28 2.2.2 supervisor programming model................................................................... 2-29 2.2.2.1 status register (sr).................................................................................. 2-29 2.2.2.2 vector base register (vbr) .................................................................... 2-30 2.2.2.3 cache control register (cacr) .............................................................. 2-30 2.2.2.4 access control registers (acr0?acr1)................................................ 2-31 2.2.2.5 ram base address register (rambar) ............................................... 2-31 2.2.2.6 module base address register (mbar) ................................................. 2-31 2.3 integer data formats......................................................................................... 2-31 2.4 organization of data in registers..................................................................... 2-31 2.4.1 organization of integer data formats in registers ...................................... 2-31 2.4.2 organization of integer data formats in memory ....................................... 2-32 2.5 addressing mode summary ............................................................................. 2-33 2.6 instruction set summary................................................................................... 2-34 2.6.1 instruction set summary .............................................................................. 2-37 2.7 instruction timing ............................................................................................ 2-40 2.7.1 move instruction execution times ............................................................ 2-41 2.7.2 execution timings?one-operand instructions .......................................... 2-43 2.7.3 execution timings?two-operand instructions.......................................... 2-43 2.7.4 miscellaneous instruction execution times................................................. 2-45 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents vii 2.7.5 branch instruction execution times ............................................................ 2-46 2.8 exception processing overview ....................................................................... 2-47 2.8.1 exception stack frame definition................................................................ 2-49 2.8.2 processor exceptions .................................................................................... 2-50 chapter 3 hardware multiply/accumulate (mac) unit 3.1 overview............................................................................................................. 3-1 3.1.1 mac programming model............................................................................. 3-2 3.1.2 general operation........................................................................................... 3-3 3.1.3 mac instruction set summary ...................................................................... 3-4 3.1.4 data representation........................................................................................ 3-4 3.2 mac instruction execution timings.................................................................. 3-5 chapter 4 local memory 4.1 interactions between local memory modules ................................................... 4-1 4.2 sram overview ................................................................................................ 4-1 4.3 sram operation ................................................................................................ 4-2 4.4 sram programming model............................................................................... 4-3 4.4.1 sram base address register (rambar)................................................... 4-3 4.5 sram initialization............................................................................................ 4-4 4.5.1 sram initialization code .............................................................................. 4-5 4.6 power management ............................................................................................ 4-6 4.7 cache overview.................................................................................................. 4-6 4.8 cache organization............................................................................................. 4-7 4.8.1 cache line states: invalid, valid-unmodified, and valid-modified............. 4-8 4.8.2 the cache at start-up..................................................................................... 4-9 4.9 cache operation................................................................................................ 4-11 4.9.1 caching modes ............................................................................................. 4-13 4.9.1.1 cacheable accesses .................................................................................. 4-13 4.9.1.2 write-through mode ............................................................................... 4-14 4.9.1.3 copyback mode ....................................................................................... 4-14 4.9.2 cache-inhibited accesses ............................................................................. 4-14 4.9.3 cache protocol.............................................................................................. 4-15 4.9.3.1 read miss ................................................................................................. 4-15 4.9.3.2 write miss ............................................................................................... 4-16 4.9.3.3 read hit .................................................................................................... 4-16 4.9.3.4 write hit .................................................................................................. 4-16 4.9.4 cache coherency ......................................................................................... 4-17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
viii mcf5307 users manual contents paragraph number title page number 4.9.5 memory accesses for cache maintenance................................................... 4-17 4.9.5.1 cache filling............................................................................................. 4-17 4.9.5.2 cache pushes ............................................................................................ 4-18 4.9.5.2.1 push and store buffers ......................................................................... 4-18 4.9.5.2.2 push and store buffer bus operation................................................... 4-18 4.9.6 cache locking .............................................................................................. 4-19 4.10 cache registers................................................................................................. 4-21 4.10.1 cache control register (cacr) .................................................................. 4-21 4.10.2 access control registers (acr0?acr1).................................................... 4-22 4.11 cache management........................................................................................... 4-24 4.12 cache operation summary ............................................................................... 4-25 4.12.1 cache state transitions ................................................................................ 4-25 4.13 cache initialization code.................................................................................. 4-29 chapter 5 debug support 5.1 overview............................................................................................................. 5-1 5.2 signal description............................................................................................... 5-2 5.3 real-time trace support.................................................................................... 5-3 5.3.1 begin execution of taken branch (pst = 0x5) ............................................. 5-4 5.4 programming model ........................................................................................... 5-5 5.4.1 address attribute trigger register (aatr) .................................................. 5-7 5.4.2 address breakpoint registers (ablr, abhr) ............................................ 5-8 5.4.3 bdm address attribute register (baar)..................................................... 5-9 5.4.4 configuration/status register (csr)............................................................ 5-10 5.4.5 data breakpoint/mask registers (dbr, dbmr)......................................... 5-12 5.4.6 program counter breakpoint/mask registers (pbr, pbmr)...................... 5-13 5.4.7 trigger definition register (tdr) ............................................................... 5-14 5.5 background debug mode (bdm) .................................................................... 5-16 5.5.1 cpu halt....................................................................................................... 5-16 5.5.2 bdm serial interface.................................................................................... 5-17 5.5.2.1 receive packet format ............................................................................. 5-19 5.5.2.2 transmit packet format............................................................................ 5-19 5.5.3 bdm command set...................................................................................... 5-19 5.5.3.1 coldfire bdm command format............................................................ 5-20 5.5.3.1.1 extension words as required............................................................... 5-21 5.5.3.2 command sequence diagrams................................................................. 5-21 5.5.3.3 command set descriptions ...................................................................... 5-23 5.5.3.3.1 read a/d register ( rareg / rdreg ) ..................................................... 5-24 5.5.3.3.2 write a/d register ( wareg / wdreg )................................................... 5-25 5.5.3.3.3 read memory location ( read )............................................................ 5-26 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents ix 5.5.3.3.4 write memory location ( write ) ......................................................... 5-27 5.5.3.3.5 dump memory block ( dump ) .............................................................. 5-29 5.5.3.3.6 fill memory block ( fill ) ..................................................................... 5-31 5.5.3.3.7 resume execution ( go )........................................................................ 5-33 5.5.3.3.8 no operation ( nop ) .............................................................................. 5-34 5.5.3.3.9 synchronize pc to the pst/ddata lines ( sync _ pc ) ....................... 5-35 5.5.3.3.10 read control register ( rcreg ) ............................................................ 5-36 5.5.3.3.11 write control register ( wcreg ) .......................................................... 5-37 5.5.3.3.12 read debug module register ( rdmreg ) ............................................. 5-38 5.5.3.3.13 write debug module register ( wdmreg ) ........................................... 5-39 5.6 real-time debug support ................................................................................ 5-39 5.6.1 theory of operation...................................................................................... 5-40 5.6.1.1 emulator mode ......................................................................................... 5-41 5.6.2 concurrent bdm and processor operation .................................................. 5-41 5.7 motorola-recommended bdm pinout............................................................. 5-42 5.8 processor status, ddata definition............................................................... 5-42 5.8.1 user instruction set ...................................................................................... 5-43 5.8.2 supervisor instruction set............................................................................. 5-46 part ii system integration module (sim) chapter 6 sim overview 6.1 features ............................................................................................................... 6-1 6.2 programming model ........................................................................................... 6-3 6.2.1 sim register memory map............................................................................ 6-3 6.2.2 module base address register (mbar) ....................................................... 6-4 6.2.3 reset status register (rsr) ........................................................................... 6-5 6.2.4 software watchdog timer.............................................................................. 6-6 6.2.5 system protection control register (sypcr) ............................................... 6-8 6.2.6 software watchdog interrupt vector register (swivr)............................... 6-9 6.2.7 software watchdog service register (swsr)............................................... 6-9 6.2.8 pll clock control for cpu stop instruction ............................................ 6-10 6.2.9 pin assignment register (par) ................................................................... 6-10 6.2.10 bus arbitration control ................................................................................ 6-11 6.2.10.1 default bus master park register (mpark) .......................................... 6-11 6.2.10.1.1 arbitration for internally generated transfers (mpark[park])...... 6-12 6.2.10.1.2 arbitration between internal and external masters for accessing internal resources ......................................................... 6-14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
x mcf5307 users manual contents paragraph number title page number chapter 7 phase-locked loop (pll) 7.1 overview............................................................................................................. 7-1 7.1.1 pll:pclk ratios........................................................................................... 7-2 7.2 pll operation .................................................................................................... 7-2 7.2.1 reset/initialization .......................................................................................... 7-2 7.2.2 normal mode.................................................................................................. 7-2 7.2.3 reduced-power mode..................................................................................... 7-2 7.2.4 pll control register (pllcr)...................................................................... 7-3 7.3 pll port list ...................................................................................................... 7-3 7.4 timing relationships .......................................................................................... 7-4 7.4.1 pclk, pstclk, and bclko ....................................................................... 7-4 7.4.2 rsti timing ................................................................................................... 7-5 7.5 pll power supply filter circuit ........................................................................ 7-6 chapter 8 i 2 c module 8.1 overview............................................................................................................. 8-1 8.2 interface features................................................................................................ 8-1 8.3 i 2 c system configuration................................................................................... 8-3 8.4 i 2 c protocol ........................................................................................................ 8-3 8.4.1 arbitration procedure ..................................................................................... 8-4 8.4.2 clock synchronization.................................................................................... 8-5 8.4.3 handshaking ................................................................................................... 8-5 8.4.4 clock stretching ............................................................................................. 8-5 8.5 programming model ........................................................................................... 8-6 8.5.1 i 2 c address register (iadr) ......................................................................... 8-6 8.5.2 i 2 c frequency divider register (ifdr)......................................................... 8-7 8.5.3 i 2 c control register (i2cr) ........................................................................... 8-8 8.5.4 i 2 c status register (i2sr).............................................................................. 8-9 8.5.5 i 2 c data i/o register (i2dr) ....................................................................... 8-10 8.6 i 2 c programming examples ............................................................................. 8-10 8.6.1 initialization sequence.................................................................................. 8-10 8.6.2 generation of start................................................................................... 8-10 8.6.3 post-transfer software response................................................................. 8-11 8.6.4 generation of stop...................................................................................... 8-12 8.6.5 generation of repeated start................................................................... 8-12 8.6.6 slave mode ................................................................................................... 8-13 8.6.7 arbitration lost............................................................................................. 8-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents xi chapter 9 interrupt controller 9.1 overview............................................................................................................. 9-1 9.2 interrupt controller registers ............................................................................. 9-2 9.2.1 interrupt control registers (icr0?icr9) ...................................................... 9-3 9.2.2 autovector register (avr) ............................................................................ 9-5 9.2.3 interrupt pending and mask registers (ipr and imr)................................... 9-6 9.2.4 interrupt port assignment register (irqpar) .............................................. 9-7 chapter 10 chip-select module 10.1 overview........................................................................................................... 10-1 10.2 chip-select module signals ............................................................................. 10-1 10.3 chip-select operation....................................................................................... 10-2 10.3.1 general chip-select operation..................................................................... 10-3 10.3.1.1 8-, 16-, and 32-bit port sizing.................................................................. 10-4 10.3.1.2 global chip-select operation................................................................... 10-4 10.4 chip-select registers........................................................................................ 10-5 10.4.1 chip-select module registers ...................................................................... 10-6 10.4.1.1 chip-select address registers (csar0?csar7)................................... 10-6 10.4.1.2 chip-select mask registers (csmr0?csmr7)...................................... 10-6 10.4.1.3 chip-select control registers (cscr0?cscr7) .................................... 10-8 10.4.1.4 code example........................................................................................... 10-9 chapter 11 synchronous/asynchronous dram controller module 11.1 overview........................................................................................................... 11-1 11.1.1 definitions .................................................................................................... 11-2 11.1.2 block diagram and major components ....................................................... 11-2 11.2 dram controller operation ............................................................................ 11-3 11.2.1 dram controller registers ......................................................................... 11-3 11.3 asynchronous operation .................................................................................. 11-4 11.3.1 dram controller signals in asynchronous mode...................................... 11-4 11.3.2 asynchronous register set........................................................................... 11-4 11.3.2.1 dram control register (dcr) in asynchronous mode ........................ 11-4 11.3.2.2 dram address and control registers (dacr0/dacr1) ..................... 11-5 11.3.2.3 dram controller mask registers (dmr0/dmr1) ................................ 11-7 11.3.3 general asynchronous operation guidelines .............................................. 11-8 11.3.3.1 non-page-mode operation..................................................................... 11-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xii mcf5307 users manual contents paragraph number title page number 11.3.3.2 burst page-mode operation ................................................................... 11-12 11.3.3.3 continuous page mode........................................................................... 11-13 11.3.3.4 extended data out (edo) operation..................................................... 11-15 11.3.3.5 refresh operation ................................................................................... 11-16 11.4 synchronous operation................................................................................... 11-16 11.4.1 dram controller signals in synchronous mode...................................... 11-17 11.4.2 using edge select (edgesel) ................................................................. 11-18 11.4.3 synchronous register set ........................................................................... 11-19 11.4.3.1 dram control register (dcr) in synchronous mode.......................... 11-19 11.4.3.2 dram address and control registers (dacr0/dacr1) in synchronous mode ......................................................................... 11-20 11.4.3.3 dram controller mask registers (dmr0/dmr1) .............................. 11-22 11.4.4 general synchronous operation guidelines............................................... 11-23 11.4.4.1 address multiplexing ............................................................................. 11-23 11.4.4.2 interfacing example................................................................................ 11-27 11.4.4.3 burst page mode..................................................................................... 11-27 11.4.4.4 continuous page mode........................................................................... 11-29 11.4.4.5 auto-refresh operation.......................................................................... 11-31 11.4.4.6 self-refresh operation ........................................................................... 11-32 11.4.5 initialization sequence................................................................................ 11-33 11.4.5.1 mode register settings........................................................................... 11-33 11.5 sdram example ........................................................................................... 11-34 11.5.1 sdram interface configuration................................................................ 11-35 11.5.2 dcr initialization....................................................................................... 11-35 11.5.3 dacr initialization.................................................................................... 11-35 11.5.4 dmr initialization...................................................................................... 11-37 11.5.5 mode register initialization ....................................................................... 11-38 11.5.6 initialization code....................................................................................... 11-39 part iii peripheral module chapter 12 dma controller module 12.1 overview........................................................................................................... 12-1 12.1.1 dma module features ................................................................................. 12-2 12.2 dma signal description .................................................................................. 12-2 12.3 dma transfer overview.................................................................................. 12-3 12.4 dma controller module programming model................................................ 12-4 12.4.1 source address registers (sar0?sar3) .................................................... 12-6 12.4.2 destination address registers (dar0?dar3) ........................................... 12-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents xiii 12.4.3 byte count registers (bcr0?bcr3)........................................................... 12-7 12.4.4 dma control registers (dcr0?dcr3)...................................................... 12-8 12.4.5 dma status registers (dsr0?dsr3) ....................................................... 12-10 12.4.6 dma interrupt vector registers (divr0?divr3) ................................... 12-11 12.5 dma controller module functional description........................................... 12-11 12.5.1 transfer requests (cycle-steal and continuous modes) ........................... 12-12 12.5.2 data transfer modes .................................................................................. 12-12 12.5.2.1 dual-address transfers .......................................................................... 12-12 12.5.2.2 single-address transfers........................................................................ 12-13 12.5.3 channel initialization and startup .............................................................. 12-13 12.5.3.1 channel prioritization ............................................................................. 12-13 12.5.3.2 programming the dma controller module ........................................... 12-13 12.5.4 data transfer .............................................................................................. 12-14 12.5.4.1 external request and acknowledge operation ...................................... 12-14 12.5.4.2 auto-alignment...................................................................................... 12-17 12.5.4.3 bandwidth control.................................................................................. 12-18 12.5.5 termination................................................................................................. 12-18 chapter 13 timer module 13.1 overview........................................................................................................... 13-1 13.1.1 key features ................................................................................................. 13-2 13.2 general-purpose timer units ........................................................................... 13-2 13.3 general-purpose timer programming model .................................................. 13-2 13.3.1 timer mode registers (tmr0/tmr1) ........................................................ 13-3 13.3.2 timer reference registers (trr0/trr1) ................................................... 13-4 13.3.3 timer capture registers (tcr0/tcr1)....................................................... 13-4 13.3.4 timer counters (tcn0/tcn1) .................................................................... 13-5 13.3.5 timer event registers (ter0/ter1)........................................................... 13-5 13.4 code example................................................................................................... 13-6 13.5 calculating time-out values ........................................................................... 13-7 chapter 14 uart modules 14.1 overview........................................................................................................... 14-1 14.2 serial module overview ................................................................................... 14-2 14.3 register descriptions ........................................................................................ 14-2 14.3.1 uart mode registers 1 (umr1n).............................................................. 14-4 14.3.2 uart mode register 2 (umr2n) ............................................................... 14-6 14.3.3 uart status registers (usrn) ................................................................... 14-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xiv mcf5307 users manual contents paragraph number title page number 14.3.4 uart clock-select registers (ucsrn)...................................................... 14-8 14.3.5 uart command registers (ucrn) ............................................................ 14-9 14.3.6 uart receiver buffers (urbn) ............................................................... 14-11 14.3.7 uart transmitter buffers (utbn) ........................................................... 14-11 14.3.8 uart input port change registers (uipcrn).......................................... 14-12 14.3.9 uart auxiliary control register (uacrn)............................................. 14-12 14.3.10 uart interrupt status/mask registers (uisrn/uimrn).......................... 14-13 14.3.11 uart divider upper/lower registers (udun/udln) ............................ 14-14 14.3.12 uart interrupt vector register (uivrn)................................................. 14-15 14.3.13 uart input port register (uipn) .............................................................. 14-15 14.3.14 uart output port command registers (uop1n/uop0n) ....................... 14-15 14.4 uart module signal definitions .................................................................. 14-16 14.5 operation......................................................................................................... 14-18 14.5.1 transmitter/receiver clock source............................................................ 14-18 14.5.1.1 programmable divider............................................................................ 14-18 14.5.1.2 calculating baud rates........................................................................... 14-19 14.5.1.2.1 bclko baud rates ........................................................................... 14-19 14.5.1.2.2 external clock .................................................................................... 14-19 14.5.2 transmitter and receiver operating modes............................................... 14-19 14.5.2.1 transmitting ........................................................................................... 14-21 14.5.2.2 receiver .................................................................................................. 14-22 14.5.2.3 fifo stack ............................................................................................. 14-24 14.5.3 looping modes ........................................................................................... 14-25 14.5.3.1 automatic echo mode ............................................................................ 14-25 14.5.3.2 local loop-back mode .......................................................................... 14-25 14.5.3.3 remote loop-back mode....................................................................... 14-26 14.5.4 multidrop mode.......................................................................................... 14-26 14.5.5 bus operation ............................................................................................. 14-28 14.5.5.1 read cycles ............................................................................................ 14-28 14.5.5.2 write cycles ........................................................................................... 14-28 14.5.5.3 interrupt acknowledge cycles ............................................................... 14-28 14.5.6 programming .............................................................................................. 14-28 14.5.6.1 uart module initialization sequence .................................................. 14-29 chapter 15 parallel port (general-purpose i/o) 15.1 parallel port operation...................................................................................... 15-1 15.1.1 pin assignment register (par) ................................................................... 15-1 15.1.2 port a data direction register (paddr).................................................... 15-2 15.1.3 port a data register (padat) .................................................................... 15-2 15.1.4 code example............................................................................................... 15-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents xv part iv hardware interface chapter 16 mechanical data 16.1 package ............................................................................................................. 16-1 16.2 pinout ................................................................................................................ 16-1 16.3 mechanical diagram......................................................................................... 16-8 16.4 case drawing.................................................................................................... 16-9 chapter 17 signal descriptions 17.1 overview........................................................................................................... 17-1 17.2 mcf5307 bus signals ...................................................................................... 17-7 17.2.1 address bus .................................................................................................. 17-7 17.2.1.1 address bus (a[23:0]).............................................................................. 17-7 17.2.1.2 address bus (a[31:24]/pp[15:8]) ............................................................ 17-7 17.2.2 data bus (d[31:0]) ....................................................................................... 17-8 17.2.3 read/write (r/w )......................................................................................... 17-8 17.2.4 size (siz[1:0]) .............................................................................................. 17-8 17.2.5 transfer start (ts ) ........................................................................................ 17-9 17.2.6 address strobe (as) ..................................................................................... 17-9 17.2.7 transfer acknowledge (t a ) ......................................................................... 17-9 17.2.8 transfer in progress (tip /pp7)................................................................... 17-10 17.2.9 transfer type (tt[1:0]/pp[1:0]) ................................................................ 17-10 17.2.10 transfer modifier (tm[2:0]/pp[4:2])......................................................... 17-10 17.3 interrupt control signals................................................................................. 17-12 17.3.1 interrupt request (irq1 /irq2 , irq3 /irq6 , irq5 /irq4 , and irq7 )....... 17-12 17.4 bus arbitration signals................................................................................... 17-12 17.4.1 bus request (br ) ....................................................................................... 17-12 17.4.2 bus grant (bg ).......................................................................................... 17-12 17.4.3 bus driven (bd)......................................................................................... 17-13 17.5 clock and reset signals.................................................................................. 17-13 17.5.1 reset in (rsti )........................................................................................... 17-13 17.5.2 clock input (clkin).................................................................................. 17-13 17.5.3 bus clock output (bclko) ...................................................................... 17-13 17.5.4 reset out (rsto)....................................................................................... 17-13 17.5.5 data/configuration pins (d[7:0]) ............................................................... 17-13 17.5.5.1 d[7:5boot chip-select (cs0 ) configuration ......................................... 17-14 17.5.5.2 d7?auto acknowledge configuration (aa_config) ...................... 17-14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xvi mcf5307 users manual contents paragraph number title page number 17.5.5.3 d[6:5]?port size configuration (ps_config[1:0]) ........................... 17-14 17.5.6 d4?address configuration (addr_config) ....................................... 17-14 17.5.7 d[3:2]?frequency control pll (freq[1:0] ..........................................) 17-15 17.5.8 d[1:0]?divide control pclk to bclko (divide[1:0])....................... 17-15 17.6 chip-select module signals ........................................................................... 17-15 17.6.1 chip-select (cs[7:0]) ................................................................................. 17-16 17.6.2 byte enables/byte write enables (be[3:0]/bwe[3:0]) ............................ 17-16 17.6.3 output enable (oe) .................................................................................... 17-16 17.7 dram controller signals .............................................................................. 17-16 17.7.1 row address strobes (ras[1:0])............................................................... 17-16 17.7.2 column address strobes (cas[3:0]) ......................................................... 17-16 17.7.3 dram write (dramw)........................................................................... 17-17 17.7.4 synchronous dram column address strobe (scas) ............................. 17-17 17.7.5 synchronous dram row address strobe (sras)................................... 17-17 17.7.6 synchronous dram clock enable (scke) .............................................. 17-17 17.7.7 synchronous edge select (edgesel) ...................................................... 17-17 17.8 dma controller module signals.................................................................... 17-17 17.8.1 dma request (dreq[1:0]/pp[6:5]).......................................................... 17-18 17.9 serial module signals ..................................................................................... 17-18 17.9.1 transmitter serial data output (txd)........................................................ 17-18 17.9.2 receiver serial data input (rxd)............................................................... 17-18 17.9.3 clear to send (cts).................................................................................... 17-18 17.9.4 request to send (rts) ............................................................................... 17-18 17.10 timer module signals..................................................................................... 17-18 17.10.1 timer inputs (tin[1:0]).............................................................................. 17-19 17.10.2 timer outputs (tout1, tout0) .............................................................. 17-19 17.11 parallel i/o port (pp[15:0]) ............................................................................ 17-19 17.12 i2c module signals ........................................................................................ 17-19 17.12.1 i2c serial clock (scl)............................................................................... 17-19 17.12.2 i2c serial data (sda)................................................................................ 17-19 17.13 debug and test signals .................................................................................. 17-20 17.13.1 test mode (mtmod[3:0]) ........................................................................ 17-20 17.13.2 high impedance (hiz )................................................................................ 17-20 17.13.3 processor clock output (pstclk)............................................................ 17-20 17.13.4 debug data (ddata[3:0])........................................................................ 17-20 17.13.5 processor status (pst[3:0])........................................................................ 17-20 17.14 debug module/jtag signals......................................................................... 17-21 17.14.1 test reset/development serial clock (trst /dsclk) ............................ 17-21 17.14.2 test mode select/breakpoint (tms/bkpt ) .............................................. 17-22 17.14.3 test data input/development serial input (tdi/dsi) ............................... 17-22 17.14.4 test data output/development serial output (tdo/dso)....................... 17-22 17.14.5 test clock (tck) ....................................................................................... 17-23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents xvii chapter 18 bus operation 18.1 features ............................................................................................................. 18-1 18.2 bus and control signals ................................................................................... 18-1 18.3 bus characteristics............................................................................................ 18-2 18.4 data transfer operation ................................................................................... 18-3 18.4.1 bus cycle execution..................................................................................... 18-4 18.4.2 data transfer cycle states ........................................................................... 18-5 18.4.3 read cycle.................................................................................................... 18-7 18.4.4 write cycle ................................................................................................... 18-8 18.4.5 fast-termination cycles............................................................................... 18-9 18.4.6 back-to-back bus cycles ........................................................................... 18-10 18.4.7 burst cycles................................................................................................ 18-11 18.4.7.1 line transfers ......................................................................................... 18-12 18.4.7.2 line read bus cycles............................................................................. 18-12 18.4.7.3 line write bus cycles............................................................................ 18-14 18.4.7.4 transfers using mixed port sizes .......................................................... 18-15 18.5 misaligned operands ...................................................................................... 18-16 18.6 bus errors ....................................................................................................... 18-17 18.7 interrupt exceptions........................................................................................ 18-17 18.7.1 level 7 interrupts........................................................................................ 18-18 18.7.2 interrupt-acknowledge cycle..................................................................... 18-19 18.8 bus arbitration................................................................................................ 18-20 18.8.1 bus arbitration signals............................................................................... 18-21 18.9 general operation of external master transfers............................................ 18-21 18.9.1 two-device bus arbitration protocol (two-wire mode) ......................... 18-25 18.9.2 multiple external bus device arbitration protocol (three-wire mode)... 18-29 18.10 reset operation............................................................................................... 18-33 18.10.1 master reset ............................................................................................... 18-34 18.10.2 software watchdog reset........................................................................... 18-35 chapter 19 ieee 1149.1 test access port (jtag) 19.1 overview........................................................................................................... 19-1 19.2 jtag signal descriptions ............................................................................... 19-2 19.3 tap controller.................................................................................................. 19-3 19.4 jtag register descriptions ............................................................................. 19-4 19.4.1 jtag instruction shift register .................................................................. 19-5 19.4.2 idcode register ......................................................................................... 19-6 19.4.3 jtag boundary-scan register .................................................................... 19-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xviii mcf5307 users manual contents paragraph number title page number 19.4.4 jtag bypass register................................................................................ 19-10 19.5 restrictions ..................................................................................................... 19-10 19.6 disabling ieee standard 1149.1 operation ................................................... 19-11 19.7 obtaining the ieee standard 1149.1.............................................................. 19-12 chapter 20 electrical specifications 20.1 general parameters ........................................................................................... 20-1 20.2 clock timing specifications............................................................................. 20-2 20.3 input/output ac timing specifications........................................................... 20-3 20.4 reset timing specifications ........................................................................... 20-12 20.5 debug ac timing specifications................................................................... 20-12 20.6 timer module ac timing specifications ...................................................... 20-14 20.7 i 2 c input/output timing specifications......................................................... 20-15 20.8 uart module ac timing specifications ..................................................... 20-16 20.9 parallel port (general-purpose i/o) timing specifications ........................... 20-18 20.10 dma timing specifications........................................................................... 20-19 20.11 ieee 1149.1 (jtag) ac timing specifications ........................................... 20-20 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number illustrations xix 1-1 mcf5307 block diagram............................................................................................. 1-2 1-2 uart module block diagram..................................................................................... 1-9 1-3 pll module ................................................................................................................ 1- 12 1-4 coldfire mcf5307 programming model .................................................................. 1-13 2-1 coldfire enhanced pipeline ....................................................................................... 2-23 2-2 coldfire multiply-accumulate functionality diagram ............................................. 2-25 2-3 coldfire programming model.................................................................................... 2-27 2-5 status register (sr).................................................................................................... 2-30 2-6 vector base register (vbr)....................................................................................... 2-30 2-7 organization of integer data formats in data registers............................................ 2-32 2-8 organization of integer data formats in address registers ...................................... 2-32 2-9 memory operand addressing..................................................................................... 2-33 2-10 exception stack frame form...................................................................................... 2-49 3-1 coldfire mac multiplication and accumulation........................................................ 3-2 3-2 mac programming model ........................................................................................... 3-2 4-1 sram base address register (rambar) ................................................................. 4-3 4-2 unified cache organization ......................................................................................... 4-7 4-3 cache organization and line format ........................................................................... 4-8 4-4 cache?a: at reset, b: after invalidation, c and d: loading pattern ....................... 4-10 4-5 caching operation ...................................................................................................... 4-11 4-6 write-miss in copyback mode................................................................................... 4-16 4-7 cache locking ............................................................................................................ 4-2 0 4-8 cache control register (cacr) ................................................................................ 4-21 4-9 access control register format (acrn) ................................................................... 4-23 4-10 a n format .................................................................................................................. 4-24 4-11 cache line state diagram?copyback mode............................................................ 4-26 4-12 cache line state diagram?write-through mode.................................................... 4-26 5-1 processor/debug module interface............................................................................... 5-1 5-2 pstclk timing........................................................................................................... 5-3 5-3 example jmp instruction output on pst/ddata...................................................... 5-5 5-4 debug programming model ......................................................................................... 5-6 5-5 address attribute trigger register (aatr) ................................................................ 5-7 5-6 address breakpoint registers (ablr, abhr) ........................................................... 5-9 5-7 bdm address attribute register (baar)................................................................... 5-9 5-8 configuration/status register (csr).......................................................................... 5-10 5-9 data breakpoint/mask registers (dbr and dbmr)................................................. 5-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number xx mcf5307 users manual 5-10 program counter breakpoint register (pbr)............................................................. 5-14 5-11 program counter breakpoint mask register (pbmr) ............................................... 5-14 5-12 trigger definition register (tdr) ............................................................................. 5-15 5-13 bdm serial interface timing ..................................................................................... 5-18 5-14 receive bdm packet.................................................................................................. 5-19 5-15 transmit bdm packet ................................................................................................ 5-19 5-16 bdm command format ............................................................................................. 5-21 5-17 command sequence diagram..................................................................................... 5-22 5-19 rareg / rdreg command sequence............................................................................ 5-24 5-18 rareg / rdreg command format ............................................................................... 5-24 5-21 wareg / wdreg command sequence .......................................................................... 5-25 5-20 wareg / wdreg command format.............................................................................. 5-25 5-23 read command sequence.......................................................................................... 5-26 5-22 read command/result formats................................................................................. 5-26 5-24 write command format ............................................................................................ 5-27 5-25 write command sequence ........................................................................................ 5-28 5-26 dump command/result formats ................................................................................ 5-29 5-27 dump command sequence ......................................................................................... 5-30 5-28 fill command format................................................................................................ 5-31 5-29 fill command sequence............................................................................................ 5-32 5-31 go command sequence.............................................................................................. 5-33 5-30 go command format.................................................................................................. 5-33 5-33 nop command sequence ............................................................................................ 5-34 5-32 nop command format................................................................................................ 5-34 5-35 sync _ pc command sequence .................................................................................... 5-35 5-34 sync _ pc command format........................................................................................ 5-35 5-37 rcreg command sequence........................................................................................ 5-36 5-36 rcreg command/result formats............................................................................... 5-36 5-39 wcreg command sequence ....................................................................................... 5-37 5-38 wcreg command/result formats.............................................................................. 5-37 5-41 rdmreg command sequence..................................................................................... 5-38 5-40 rdmreg bdm command/result formats.................................................................... 5-38 5-43 wdmreg command sequence .................................................................................... 5-39 5-42 wdmreg bdm command format.............................................................................. 5-39 5-44 recommended bdm connector................................................................................. 5-42 6-1 sim block diagram...................................................................................................... 6-1 6-2 module base address register (mbar) ..................................................................... 6-4 6-3 reset status register (rsr) ......................................................................................... 6-5 6-4 mcf5307 embedded system recovery from unterminated access........................... 6-7 6-5 system protection control register (sypcr) ............................................................. 6-8 6-6 software watchdog interrupt vector register (swivr)............................................. 6-9 6-7 software watchdog service register (swsr)............................................................. 6-9 6-8 pin assignment register (par) ................................................................................. 6-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number illustrations xxi 6-9 default bus master register (mpark) ..................................................................... 6-11 6-10 round robin arbitration (park = 00)...................................................................... 6-12 6-11 park on master core priority (park = 01) ............................................................... 6-13 6-12 park on dma module priority (park = 10)............................................................. 6-13 6-13 park on current master priority (park = 01) ........................................................... 6-14 7-1 pll module block diagram ........................................................................................ 7-1 7-2 pll control register (pllcr).................................................................................... 7-3 7-3 clkin, pclk, pstclk, and bclko timing .......................................................... 7-5 7-4 reset and initialization timing..................................................................................... 7-6 7-5 pll power supply filter circuit .................................................................................. 7-6 8-1 i 2 c module block diagram .......................................................................................... 8-2 8-2 i 2 c standard communication protocol ........................................................................ 8-3 8-3 repeated start .......................................................................................................... 8-4 8-4 synchronized clock scl.............................................................................................. 8-5 8-5 i 2 c address register (iadr) ....................................................................................... 8-6 8-6 i 2 c frequency divider register (ifdr)....................................................................... 8-7 8-7 i 2 c control register (i2cr) ......................................................................................... 8-8 8-8 i 2 cr status register (i2sr) ......................................................................................... 8-9 8-9 i 2 c data i/o register (i2dr) ..................................................................................... 8-10 8-10 flow-chart of typical i 2 c interrupt routine ............................................................. 8-14 9-1 interrupt controller block diagram.............................................................................. 9-1 9-2 interrupt control registers (icr0?icr9) .................................................................... 9-3 9-3 autovector register (avr) .......................................................................................... 9-5 9-4 interrupt pending register (ipr) and interrupt mask register (imr) ......................... 9-7 9-5 interrupt port assignment register (irqpar) ............................................................ 9-7 10-1 connections for external memory port sizes ............................................................ 10-4 10-2 chip select address registers (csar0?csar7) ..................................................... 10-6 10-3 chip select mask registers (csmrn) ....................................................................... 10-7 10-4 chip-select control registers (cscr0?cscr7) ...................................................... 10-8 11-1 asynchronous/synchronous dram controller block diagram ............................... 11-2 11-2 dram control register (dcr) (asynchronous mode) ............................................ 11-5 11-3 dram address and control registers (dacr0/dacr1)........................................ 11-6 11-4 dram controller mask registers (dmr0 and dmr1)............................................ 11-7 11-5 basic non-page-mode operation rcd = 0, rncn = 1 (4-4-4-4) .......................... 11-11 11-6 basic non-page-mode operation rcd = 1, rncn = 0 (5-5-5-5) .......................... 11-12 11-7 burst page-mode read operation (4-3-3-3)............................................................. 11-13 11-8 burst page-mode write operation (4-3-3-3)............................................................ 11-13 11-9 continuous page-mode operation............................................................................ 11-14 11-10 write hit in continuous page mode......................................................................... 11-15 11-11 edo read operation (3-2-2-2) ................................................................................ 11-15 11-12 dram access delayed by refresh ......................................................................... 11-16 11-13 mcf5307 sdram interface.................................................................................... 11-18 11-14 using edgesel to change signal timing............................................................. 11-19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number xxii mcf5307 users manual 11-15 dram control register (dcr) (synchronous mode) ............................................ 11-19 11-16 dacr0 and dacr1 registers (synchronous mode).............................................. 11-20 11-17 dram controller mask registers (dmr0 and dmr1).......................................... 11-22 11-18 burst read sdram access ..................................................................................... 11-28 11-19 burst write sdram access .................................................................................... 11-29 11-20 synchronous, continuous page-mode access?consecutive reads....................... 11-30 11-21 synchronous, continuous page-mode access?read after write........................... 11-31 11-22 auto-refresh operation............................................................................................ 11-32 11-23 self-refresh operation ............................................................................................. 11-32 11-24 mode register set (mrs) command ......................................................................... 11-34 11-25 initialization values for dcr ................................................................................... 11-35 11-26 sdram configuration............................................................................................. 11-36 11-27 dacr register configuration.................................................................................. 11-36 11-28 dmr0 register ......................................................................................................... 11-3 7 11-29 mode register mapping to mcf5307 a[31:0] ........................................................ 11-38 12-1 dma signal diagram ................................................................................................. 12-1 12-2 dual-address transfer................................................................................................ 12-3 12-3 single-address transfers............................................................................................ 12-4 12-4 source address registers (sarn) .............................................................................. 12-6 12-5 destination address registers (darn) ...................................................................... 12-7 12-6 byte count registers (bcrn)?bcr24bit = 1 ........................................................ 12-7 12-7 bcrn?bcr24bit = 0.............................................................................................. 12-8 12-8 dma control registers (dcrn) ............................................................................... 12-8 12-9 dma status registers (dsrn) ................................................................................ 12-10 12-10 dma interrupt vector registers (divrn) ............................................................... 12-11 12-11 dreq timing constraints, dual-address dma transfer....................................... 12-15 12-12 dual-address, peripheral-to-sdram, lower-priority dma transfer ................... 12-16 12-13 single-address dma transfer ................................................................................. 12-17 13-1 timer block diagram ................................................................................................. 13-1 13-2 timer mode registers (tmr0/tmr1) ...................................................................... 13-3 13-3 timer reference registers (trr0/trr1) ................................................................. 13-4 13-4 timer capture register (tcr0/tcr1) ...................................................................... 13-5 13-5 timer counters (tcn0/tcn1)................................................................................... 13-5 13-6 timer event registers (ter0/ter1)......................................................................... 13-5 14-1 simplified block diagram .......................................................................................... 14-1 14-2 uart mode registers 1 (umr1n)............................................................................ 14-5 14-3 uart mode register 2 (umr2n) ............................................................................. 14-6 14-4 uart status register (usrn) ................................................................................... 14-7 14-5 uart clock-select register (ucsrn)...................................................................... 14-8 14-6 uart command register (ucrn)............................................................................ 14-9 14-7 uart receiver buffer (urb0) ............................................................................... 14-11 14-8 uart transmitter buffer (utb0)........................................................................... 14-12 14-9 uart input port change register (uipcrn).......................................................... 14-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number illustrations xxiii 14-10 uart auxiliary control register (uacrn) ........................................................... 14-13 14-11 uart interrupt status/mask registers (uisrn/uimrn)........................................ 14-13 14-12 uart divider upper register (udun)................................................................... 14-14 14-13 uart divider lower register (udln)................................................................... 14-14 14-14 uart interrupt vector register (uivrn) ............................................................... 14-15 14-15 uart input port register (uipn) ............................................................................ 14-15 14-17 uart block diagram showing external and internal interface signals ................ 14-16 14-16 uart output port command register (uop1/uop0) ........................................... 14-16 14-18 uart/rs-232 interface ........................................................................................... 14-17 14-19 clocking source diagram......................................................................................... 14-18 14-20 transmitter and receiver functional diagram......................................................... 14-20 14-21 transmitter timing diagram .................................................................................... 14-22 14-22 receiver timing........................................................................................................ 14- 23 14-23 automatic echo ........................................................................................................ 14-2 5 14-24 local loop-back ...................................................................................................... 14-26 14-25 remote loop-back ................................................................................................... 14-26 14-26 multidrop mode timing diagram ............................................................................ 14-27 14-27 uart mode programming flowchart ..................................................................... 14-30 15-1 parallel port pin assignment register (par) ............................................................ 15-1 15-2 port a data direction register (paddr).................................................................. 15-2 15-3 port a data register (padat) .................................................................................. 15-3 16-1 mechanical diagram................................................................................................... 16-9 16-2 mcf5307 case drawing (general view) ................................................................ 16-10 16-3 case drawing (details)............................................................................................. 16-11 17-1 mcf5307 block diagram with signal interfaces ...................................................... 17-2 18-1 signal relationship to bclko for non-dram access ........................................... 18-2 18-2 connections for external memory port sizes ............................................................ 18-4 18-3 chip-select module output timing diagram ............................................................ 18-4 18-4 data transfer state transition diagram ..................................................................... 18-6 18-5 read cycle flowchart................................................................................................. 18-7 18-6 basic read bus cycle................................................................................................. 18-8 18-7 write cycle flowchart................................................................................................ 18-9 18-8 basic write bus cycle ................................................................................................ 18-9 18-9 read cycle with fast termination ........................................................................... 18-10 18-10 write cycle with fast termination........................................................................... 18-10 18-11 back-to-back bus cycles ......................................................................................... 18-11 18-12 line read burst (2-1-1-1), external termination .................................................... 18-12 18-13 line read burst (2-1-1-1), internal termination ..................................................... 18-13 18-14 line read burst (3-2-2-2), external termination .................................................... 18-13 18-15 line read burst-inhibited, fast, external termination............................................ 18-14 18-16 line write burst (2-1-1-1), internal/external termination...................................... 18-14 18-17 line write burst (3-2-2-2) with one wait state, internal termination ................... 18-15 18-18 line write burst-inhibited, internal termination .................................................... 18-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number xxiv mcf5307 users manual 18-19 longword read from an 8-bit port, external termination...................................... 18-16 18-20 longword read from an 8-bit port, internal termination ....................................... 18-16 18-21 example of a misaligned longword transfer (32-bit port) .................................... 18-17 18-22 example of a misaligned word transfer (32-bit port) ............................................ 18-17 18-23 interrupt-acknowledge cycle flowchart ................................................................. 18-20 18-24 basic no-wait-state external master access .......................................................... 18-22 18-25 external master burst line access to 32-bit port.................................................... 18-24 18-26 mcf5307 two-wire mode bus arbitration interface............................................. 18-25 18-27 two-wire bus arbitration with bus request asserted............................................ 18-26 18-28 two-wire implicit and explicit bus mastership...................................................... 18-27 18-29 mcf5307 two-wire bus arbitration protocol state diagram................................ 18-28 18-30 three-wire implicit and explicit bus mastership.................................................... 18-30 18-31 three-wire bus arbitration...................................................................................... 18-31 18-32 three-wire bus arbitration protocol state diagram ............................................... 18-32 18-33 master reset timing................................................................................................. 18-34 18-34 software watchdog reset timing ............................................................................ 18-36 19-1 jtag test logic block diagram ............................................................................... 19-2 19-2 jtag tap controller state machine......................................................................... 19-4 19-4 disabling jtag in jtag mode ............................................................................... 19-11 19-5 disabling jtag in debug mode .............................................................................. 19-11 20-1 clock timing .............................................................................................................. 2 0-3 20-2 pstclk timing......................................................................................................... 20-3 20-3 ac timings?normal read and write bus cycles ................................................... 20-5 20-4 sdram read cycle with edgesel tied to buffered bclko.............................. 20-6 20-5 sdram write cycle with edgesel tied to buffered bclko............................. 20-7 20-6 sdram read cycle with edgesel tied high....................................................... 20-8 20-7 sdram write cycle with edgesel tied high...................................................... 20-9 20-8 sdram read cycle with edgesel tied low ..................................................... 20-10 20-9 sdram write cycle with edgesel tied low .................................................... 20-11 20-10 ac output timing?high impedance...................................................................... 20-11 20-11 reset timing............................................................................................................. 2 0-12 20-12 real-time trace ac timing .................................................................................... 20-13 20-13 bdm serial port ac timing .................................................................................... 20-13 20-14 timer module ac timing ........................................................................................ 20-14 20-15 i 2 c input/output timings......................................................................................... 20-16 20-16 uart0/1 module ac timing?uart mode......................................................... 20-17 20-17 general-purpose i/o timing..................................................................................... 20-18 20-18 dma timing ............................................................................................................ 20-1 9 20-19 ieee 1149.1 (jtag) ac timing ............................................................................. 20-21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
tables xxv tables table number title page number 1-1 user-level registers................................................................................................... 1-14 1-2 supervisor-level registers......................................................................................... 1-14 2-1 ccr field descriptions ............................................................................................. 2-28 2-2 movec register map ............................................................................................... 2-29 2-3 status field descriptions ............................................................................................ 2-30 2-4 integer data formats................................................................................................... 2-31 2-5 coldfire effective addressing modes........................................................................ 2-34 2-6 notational conventions .............................................................................................. 2-34 2-7 user-mode instruction set summary ......................................................................... 2-37 2-8 supervisor-mode instruction set summary................................................................ 2-40 2-9 misaligned operand references ................................................................................. 2-41 2-10 move byte and word execution times...................................................................... 2-42 2-11 move long execution times...................................................................................... 2-42 2-12 mac move execution times..................................................................................... 2-43 2-13 one-operand instruction execution times ................................................................ 2-43 2-14 two-operand instruction execution times................................................................ 2-44 2-15 miscellaneous instruction execution times............................................................... 2-45 2-16 general branch instruction execution times............................................................. 2-46 2-17 bcc instruction execution times................................................................................ 2-47 2-18 exception vector assignments................................................................................... 2-48 2-19 format field encoding ............................................................................................... 2-49 2-20 fault status encodings................................................................................................ 2-50 2-21 mcf5307 exceptions ................................................................................................. 2-50 3-1 mac instruction summary........................................................................................... 3-4 3-2 two-operand mac instruction execution times ....................................................... 3-5 3-3 mac move instruction execution times..................................................................... 3-6 4-1 rambar field description ........................................................................................ 4-3 4-2 examples of typical rambar settings ..................................................................... 4-6 4-3 valid and modified bit settings ................................................................................... 4-8 4-4 cacr field descriptions ........................................................................................... 4-21 4-5 acrn field descriptions............................................................................................ 4-23 4-6 cache line state transitions ...................................................................................... 4-27 4-7 cache line state transitions (current state invalid) ................................................. 4-28 4-8 cache line state transitions (current state valid) ................................................... 4-28 4-9 cache line state transitions (current state modified) ............................................. 4-29 5-1 debug module signals.................................................................................................. 5-2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xxvi mcf5307 users manual tables table number title page number 5-2 processor status encoding............................................................................................ 5-4 5-3 bdm/breakpoint registers........................................................................................... 5-7 5-4 aatr field descriptions ............................................................................................. 5-8 5-5 ablr field description ............................................................................................... 5-9 5-6 abhr field description............................................................................................... 5-9 5-7 baar field descriptions ........................................................................................... 5-10 5-8 csr field descriptions .............................................................................................. 5-11 5-9 dbr field descriptions.............................................................................................. 5-13 5-10 dbmr field descriptions .......................................................................................... 5-13 5-11 access size and operand data location .................................................................... 5-13 5-12 pbr field descriptions .............................................................................................. 5-14 5-13 pbmr field descriptions ........................................................................................... 5-14 5-14 tdr field descriptions .............................................................................................. 5-15 5-15 receive bdm packet field description ..................................................................... 5-19 5-16 transmit bdm packet field description ................................................................... 5-19 5-17 bdm command summary ......................................................................................... 5-20 5-18 bdm field descriptions ............................................................................................. 5-21 5-19 control register map.................................................................................................. 5-36 5-20 definition of drc encoding?read........................................................................... 5-38 5-21 ddata[3:0]/csr[bstat] breakpoint response.................................................... 5-40 5-22 pst/ddata specification for user-mode instructions............................................ 5-43 5-23 pst/ddata specification for supervisor-mode instructions.................................. 5-46 6-1 sim registers ............................................................................................................. . 6-3 6-2 mbar field descriptions ............................................................................................ 6-5 6-3 rsr field descriptions ................................................................................................ 6-6 6-4 sypcr field descriptions ........................................................................................... 6-8 6-5 pllipl settings ......................................................................................................... 6-10 6-6 mpark field descriptions........................................................................................ 6-11 7-1 pllcr field descriptions............................................................................................ 7-3 7-2 pll module input signals............................................................................................ 7-3 7-3 pll module output signals ......................................................................................... 7-4 8-1 i 2 c interface memory map........................................................................................... 8-6 8-2 i 2 c address register field descriptions ...................................................................... 8-6 8-3 ifdr field descriptions ............................................................................................... 8-7 8-4 i 2 cr field descriptions................................................................................................ 8-8 8-5 i 2 sr field descriptions ................................................................................................ 8-9 9-1 interrupt controller registers ....................................................................................... 9-2 9-2 interrupt control registers ........................................................................................... 9-2 9-3 icr n field descriptions ............................................................................................... 9-3 9-4 interrupt priority scheme.............................................................................................. 9-4 9-5 avr field descriptions................................................................................................ 9-6 9-6 autovector register bit assignments........................................................................... 9-6 9-7 ipr and imr field descriptions................................................................................... 9-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
tables xxvii tables table number title page number 9-8 irqpar field descriptions ......................................................................................... 9-8 10-1 chip-select module signals ....................................................................................... 10-1 10-2 byte enables/byte write enable signal settings ....................................................... 10-2 10-3 accesses by matches in cscrs and dacrs ............................................................. 10-3 10-4 d7/aa, automatic acknowledge of boot cs0.......................................................... 10-4 10-5 d[6:5]/ps[1:0], port size of boot cs0 ....................................................................... 10-4 10-6 chip-select registers.................................................................................................. 10-5 10-7 csar n field description ........................................................................................... 10-6 10-8 csmr n field descriptions ......................................................................................... 10-7 10-9 cscr n field descriptions.......................................................................................... 10-8 11-1 dram controller registers ....................................................................................... 11-3 11-2 sdram signal summary ......................................................................................... 11-4 11-3 dcr field descriptions (asynchronous mode)......................................................... 11-5 11-4 dacr0/dacr1 field description ............................................................................ 11-6 11-5 dmr0/dmr1 field descriptions............................................................................... 11-7 11-6 generic address multiplexing scheme ...................................................................... 11-8 11-7 dram addressing for byte-wide memories.......................................................... 11-10 11-8 dram addressing for 16-bit wide memories........................................................ 11-10 11-9 dram addressing for 32-bit wide memories........................................................ 11-11 11-10 sdram commands ................................................................................................. 11-17 11-11 synchronous dram signal connections ................................................................ 11-17 11-12 dcr field descriptions (synchronous mode) ......................................................... 11-19 11-13 dacr0/dacr1 field descriptions (synchronous mode)...................................... 11-21 11-14 dmr0/dmr1 field descriptions............................................................................. 11-23 11-15 mcf5307 to sdram interface (8-bit port, 9-column address lines).................. 11-24 11-16 mcf5307 to sdram interface (8-bit port,10-column address lines)................. 11-24 11-17 mcf5307 to sdram interface (8-bit port,11-column address lines)................. 11-24 11-18 mcf5307 to sdram interface (8-bit port,12-column address lines)................. 11-24 11-19 mcf5307 to sdram interface (8-bit port,13-column address lines)................. 11-25 11-20 mcf5307 to sdram interface (16-bit port, 8-column address lines)................ 11-25 11-21 mcf5307 to sdram interface (16-bit port, 9-column address lines)................ 11-25 11-22 mcf5307 to sdram interface (16-bit port, 10-column address lines).............. 11-25 11-23 mcf5307 to sdram interface (16-bit port, 11-column address lines).............. 11-25 11-24 mcf5307 to sdram interface (16-bit port, 12-column address lines).............. 11-26 11-25 mcf5307to sdram interface (16-bit port, 13-column-address lines) .............. 11-26 11-26 mcf5307 to sdram interface (32-bit port, 8-column address lines)................ 11-26 11-27 mcf5307 to sdram interface (32-bit port, 9-column address lines)................ 11-26 11-28 mcf5307 to sdram interface (32-bit port, 10-column address lines).............. 11-26 11-29 mcf5307 to sdram interface (32-bit port, 11-column address lines).............. 11-27 11-30 mcf5307 to sdram interface (32-bit port, 12-column address lines).............. 11-27 11-31 sdram hardware connections............................................................................... 11-27 11-32 sdram example specifications ............................................................................. 11-34 11-33 sdram hardware connections............................................................................... 11-35 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xxviii mcf5307 users manual tables table number title page number 11-34 dcr initialization values......................................................................................... 11-35 11-35 dacr initialization values...................................................................................... 11-36 11-36 dmr0 initialization values...................................................................................... 11-37 11-37 mode register initialization ..................................................................................... 11-38 12-1 dma signals .............................................................................................................. 12 -2 12-2 memory map for dma controller module registers................................................ 12-5 12-3 dcr n field descriptions............................................................................................ 12-8 12-4 dsrn field descriptions .......................................................................................... 12-10 13-1 general-purpose timer module memory map .......................................................... 13-3 13-2 tmr n field descriptions ........................................................................................... 13-4 13-3 tern field descriptions............................................................................................. 13-6 13-5 calculated time-out values (90-mhz processor clock) ........................................... 13-7 14-1 uart module programming model.......................................................................... 14-3 14-2 umr1 n field descriptions ......................................................................................... 14-5 14-3 umr2 n field descriptions ......................................................................................... 14-6 14-4 usr n field descriptions ............................................................................................ 14-7 14-5 ucsr n field descriptions.......................................................................................... 14-9 14-6 ucrn field descriptions............................................................................................ 14-9 14-7 uipcr n field descriptions ...................................................................................... 14-12 14-8 uacr n field descriptions ....................................................................................... 14-13 14-9 uisr n /uimr n field descriptions ........................................................................... 14-14 14-10 uivr n field descriptions ........................................................................................ 14-15 14-11 uip n field descriptions............................................................................................ 14-15 14-12 uop1/uop0 field descriptions ............................................................................... 14-16 14-13 uart module signals ............................................................................................. 14-17 14-14 uart module initialization sequence .................................................................... 14-29 15-1 parallel port pin descriptions ..................................................................................... 15-2 15-2 paddr field description .......................................................................................... 15-2 15-3 relationship between padat register and parallel port pin (pp) ........................... 15-3 16-1 pins 1?52 (left, top-to-bottom) ................................................................................ 16-1 16-2 pins 53?104 (bottom, left-to-right).......................................................................... 16-3 16-3 pins 105?156 (right, bottom-to-top)........................................................................ 16-4 16-4 pins 157?208 (top, right-to-left) ............................................................................. 16-6 16-5 dimensions ............................................................................................................... 16 -11 17-1 mcf5307 signal index............................................................................................... 17-3 17-2 data pin configuration ............................................................................................... 17-6 17-3 bus cycle size encoding............................................................................................ 17-7 17-4 bus cycle transfer type encoding............................................................................ 17-9 17-5 tm[2:0] encodings for tt = 00 (normal access)..................................................... 17-9 17-6 tm0 encoding for dma as master (tt = 01) ........................................................... 17-9 17-7 tm[2:1] encoding for dma as master (tt = 01) ................................................... 17-10 17-8 tm[2:0] encodings for tt = 10 (emulator access) ................................................ 17-10 17-9 tm[2:0] encodings for tt = 11 (interrupt level) ................................................... 17-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
tables xxix tables table number title page number 17-10 data pin configuration ............................................................................................. 17-12 17-11 d7 selection of cs0 automatic acknowledge ........................................................ 17-13 17-12 d6 and d5 selection of cs0 port size ..................................................................... 17-13 17-13 d4/addr_config, address pin assignment....................................................... 17-13 17-14 clkin frequency .................................................................................................... 17-13 17-15 bclko/pstclk divide ratios.............................................................................. 17-14 17-16 processor status signal encodings ........................................................................... 17-19 18-1 coldfire bus signal summary ................................................................................... 18-1 18-2 bus cycle size encoding............................................................................................ 18-3 18-3 accesses by matches in cscrs and dacrs ............................................................. 18-5 18-4 bus cycle states ......................................................................................................... 18 -6 18-5 allowable line access patterns ............................................................................... 18-12 18-6 mcf5307 arbitration protocol states ...................................................................... 18-20 18-7 coldfire bus arbitration signal summary............................................................... 18-21 18-8 cycles for basic no-wait-state external master access......................................... 18-23 18-9 cycles for external master burst line access to 32-bit port .................................. 18-24 18-10 mcf5307 two-wire bus arbitration protocol transition conditions.................... 18-28 18-11 three-wire bus arbitration protocol transition conditions ................................... 18-32 18-12 data pin configuration ............................................................................................. 18-35 19-1 jtag pin descriptions ............................................................................................... 19-3 19-2 jtag instructions....................................................................................................... 19- 5 19-3 idcode bit assignments.......................................................................................... 19-6 19-4 boundary-scan bit definitions................................................................................... 19-7 20-1 absolute maximum ratings ....................................................................................... 20-1 20-2 operating temperatures.............................................................................................. 20-1 20-3 dc electrical specifications ....................................................................................... 20-2 20-4 clock timing specification ........................................................................................ 20-2 20-5 input ac timing specification................................................................................... 20-3 20-6 output ac timing specification ................................................................................ 20-4 20-7 reset timing specification....................................................................................... 20-12 20-8 debug ac timing specification .............................................................................. 20-12 20-9 timer module ac timing specification.................................................................. 20-14 20-10 i 2 c input timing specifications between scl and sda......................................... 20-15 20-11 i 2 c output timing specifications between scl and sda ...................................... 20-15 20-12 uart module ac timing specifications ............................................................... 20-16 20-13 general-purpose i/o port ac timing specifications............................................... 20-18 20-14 dma ac timing specifications .............................................................................. 20-19 20-15 ieee 1149.1 (jtag) ac timing specifications ..................................................... 20-20 a-1 sim registers............................................................................................................... a-1 a-2 interrupt controller registers ...................................................................................... a-1 a-3 chip-select registers................................................................................................... a-2 a-4 dram controller registers ........................................................................................ a-3 a-5 general-purpose timer registers ................................................................................ a-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xxx mcf5307 users manual tables table number title page number a-6 uart0 control registers............................................................................................ a-4 a-7 uart1 control registers............................................................................................ a-6 a-8 parallel port memory map........................................................................................... a-7 a-9 i 2 c interface memory map.......................................................................................... a-8 a-10 dma controller registers........................................................................................... a-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
about this book xxxi about this book the primary objective of this user?s manual is to de ne the functionality of the mcf5307 processors for use by software and hardware developers. the information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. as with any technical documentation, it is the readers? responsibility to be sure they are using the most recent version of the documentation. to locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/cold re. audience this manual is intended for system software and hardware developers and applications programmers who want to develop products for the mcf5307. it is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the coldfire architecture. organization following is a summary and a brief description of the major sections of this manual: chapter 1, ?overview,? includes general descriptions of the modules and features incorporated in the mcf5307, focussing in particular on new features. part i is intended for system designers who need to understand the operation of the mcf5307 coldfire core. ? chapter 2, ?coldfire core,? provides an overview of the microprocessor core of the mcf5307. the chapter begins with a description of enhancements from the v2 coldfire core, and then fully describes the v3 programming model as it is implemented on the mcf5307. it also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. ? chapter 3, ?hardware multiply/accumulate (mac) unit,? describes the mcf5307 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. the mac is integrated into the operand execution pipeline (oep). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xxxii mcf5307 users manual organization ? chapter 4, ?local memory.? this chapter describes the mcf5307 implementation of the coldfire v3 local memory speci cation. it consists of the two following major sections. ? section 4.2, ?sram overview,? describes the mcf5307 on-chip static ram (sram) implementation. it covers general operations, con guration, and initialization. it also provides information and examples showing how to minimize power consumption when using the sram. ? section 4.7, ?cache overview,? describes the mcf5307 cache implementation, including organization, con guration, and coherency. it describes cache operations and how the cache interacts with other memory structures. ? chapter 5, ?debug support,? describes the revision c enhanced hardware debug support in the mcf5307. this revision of the coldfire debug architecture encompasses earlier revisions. part ii, ?system integration module (sim),? describes the system integration module, which provides overall control of the bus and serves as the interface between the coldfire core processor complex and internal peripheral devices. it includes a general description of the sim and individual chapters that describe components of the sim, such as the phase-lock loop (pll) timing source, interrupt controller for peripherals, con guration and operation of chip selects, and the sdram controller. ? chapter 6, ?sim overview,? describes the sim programming model, bus arbitration, and system-protection functions for the mcf5307. ? chapter 7, ?phase-locked loop (pll),? describes con guration and operation of the pll module. it describes in detail the registers and signals that support the pll implementation. ? chapter 8, ?i 2 c module,? describes the mcf5307 i 2 c module, including i 2 c protocol, clock synchronization, and the registers in the i 2 c programing model. it also provides extensive programming examples. ? chapter 9, ?interrupt controller,? describes operation of the interrupt controller portion of the sim. includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. ? chapter 10, ?chip-select module,? describes the mcf5307 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers. ? chapter 11, ?synchronous/asynchronous dram controller module,? describes con guration and operation of the synchronous/asynchronous dram controller component of the sim. it begins with a general description and brief glossary, and includes a description of signals involved in dram operations. the remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
about this book xxxiii organization part iii, ?peripheral module,? describes the operation and con guration of the mcf5307 dma, timer, uart, and parallel port modules, and describes how they interface with the system integration unit, described in part ii. ? chapter 12, ?dma controller module,? provides an overview of the dma controller module and describes in detail its signals and registers. the latter sections of this chapter describe operations, features, and supported data transfer modes in detail, showing timing diagrams for various operations. ? chapter 13, ?timer module,? describes con guration and operation of the two general-purpose timer modules, timer 0 and timer 1. it includes programming examples. ? chapter 14, ?uart modules,? describes the use of the universal asynchronous/synchronous receiver/transmitters (uarts) implemented on the mcf5307 and includes programming examples. ? chapter 15, ?parallel port (general-purpose i/o),? describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. it includes a code example for setting up the parallel port. part iv, ?hardware interface,? provides a pinout and both electrical and functional descriptions of the mcf5307 signals. it also describes how these signals interact to support the variety of bus operations shown in timing diagrams. ? chapter 16, ?mechanical data,? provides a functional pin listing and package diagram for the mcf5307. ? chapter 17, ?signal descriptions,? provides an alphabetical listing of mcf5307 signals. this chapter describes the mcf5307 signals. in particular, it shows which are inputs or outputs, how they are multiplexed, which signals require pull-up resistors, and the state of each signal at reset. ? chapter 18, ?bus operation,? describes data transfers, error conditions, bus arbitration, and reset operations. it describes transfers initiated by the mcf5307 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. note that chapter 11, ?synchronous/asynchronous dram controller module,? describes dram cycles. ? chapter 19, ?ieee 1149.1 test access port (jtag),? describes con guration and operation of the mcf5307 jtag test implementation. it describes the use of jtag instructions and provides information on how to disable jtag functionality. ? chapter 20, ?electrical speci cations,? describes ac and dc electrical speci cations and thermal characteristics for the mcf5307. because additional speeds may have become available since the publication of this book, consult motorola?s coldfire web page, http://www.motorola.com/cold re, to con rm that this is the latest information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xxxiv mcf5307 users manual suggested reading this manual includes the following appendix: appendix a, ?list of memory maps,? lists the entire address-map for mcf5307 memory-mapped registers. this manual also includes a glossary and an index. suggested reading this section lists additional reading that provides background for the information in this manual as well as general information about the coldfire architecture. general information the following documentation provides useful information about the coldfire architecture and computer architecture in general: coldfire documentation the coldfire documentation is available from the sources listed on the back cover of this manual. document order numbers are included in parentheses for ease in ordering. coldfire programmers reference manual, r1.0 (mcf5200prm/ad) user?s manuals?these books provide details about individual coldfire implementations and are intended to be used in conjunction with the coldfire programmers reference manual. these include the following: ? coldfire mcf5102 users manual (mcf5102um/ad) ? coldfire mcf5202 users manual (mcf5202um/ad) ? coldfire mcf5204 users manual (mcf5204um/ad) ? coldfire mcf5206 users manual (mcf5206eum/ad) ? coldfire mcf5206e users manual (mcf5206eum/ad) coldfire programmers reference manual, r1.0 (mcf5200prm/ad) using microprocessors and microcomputers: the motorola family, william c. wray, ross bannatyne, joseph d. green eld additional literature on coldfire implementations is being released as new processors become available. for a current list of coldfire documentation, refer to the world wide web at http://www.motorola.com/coldfire/. conventions this document uses the following notational conventions: mnemonics in text, instruction mnemonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
about this book xxxv acronyms and abbreviations italics italics indicate variable command parameters. book titles in text are set in italics. 0x0 pre x to denote hexadecimal number 0b0 pre x to denote binary number reg[field] abbreviations for registers are shown in uppercase. speci c bits, elds, or ranges appear in brackets. for example, rambar[ba] identi es the base address eld in the ram base address register. nibble a 4-bit data unit byte an 8-bit data unit word a 16-bit data unit longword a 32-bit data unit x in some contexts, such as signal encodings, x indicates a don?t care. n used to express an unde ned numerical value not logical operator & and logical operator | or logical operator acronyms and abbreviations table i lists acronyms and abbreviations used in this document. table i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion alu arithmetic logic unit avec autovector bdm background debug mode bist built-in self test bsdl boundary-scan description language codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing ea effective address edo extended data output (dram) fifo first-in, ?st-out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xxxvi mcf5307 users manual acronyms and abbreviations gpio general-purpose i/o i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ifp instruction fetch pipeline ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lifo last-in, ?st-out lru least recently used lsb least-signi?ant byte lsb least-signi?ant bit mac multiple accumulate unit mbar memory base address register msb most-signi?ant byte msb most-signi?ant bit mux multiplex nop no operation oep operand execution pipeline pc program counter pclk processor clock pll phase-locked loop plru pseudo least recently used por power-on reset pqfp plastic quad ?t pack risc reduced instruction set computing rx receive sim system integration module sof start of frame tap test access port ttl transistor-to-transistor logic tx transmit uart universal asynchronous/synchronous receiver transmitter table i. acronyms and abbreviated terms (continued) term meaning f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
about this book xxxvii terminology and notational conventions terminology and notational conventions table ii shows notational conventions used throughout this document. table ii notational conventions instruction operand syntax opcode wildcard cc logical condition (example: ne for not equal) register speci?ations an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rc any control register (example vbr is the vector base register) rm mac registers (acc, mac, mask) rn any address or data register rw destination register w (used for mac instructions only) ry,rx any source and destination registers, respectively xi index register i (can be an address or data register: ai, di) register names acc mac accumulator register ccr condition code register (lower byte of sr) macsr mac status register mask mac mask register pc program counter sr status register port name pstddata processor status/debug data port miscellaneous operands # immediate data following the 16-bit operation word of the instruction effective address y,x source and destination effective addresses, respectively assembly language program label list of registers for movem instruction (example: d3?0) shift operation: shift left (<<), shift right (>>) operand data size: byte (b), word (w), longword (l) bc both instruction and data caches dc data cache f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xxxviii mcf5307 users manual terminology and notational conventions ic instruction cache # identi?s the 4-bit vector number for trap instructions identi?s an indirect data address referencing memory identi?s an absolute address referencing memory d n signal displacement value, n bits wide (example: d16 is a 16-bit displacement) sf scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for mac operations) operations + arithmetic addition or postincrement indicator arithmetic subtraction or predecrement indicator x arithmetic multiplication / arithmetic division ~ invert; operand is logically complemented & logical and | logical or ^ logical exclusive or << shift left (example: d0 << 3 is shift d0 left 3 bits) >> shift right (example: d0 >> 3 is shift d0 right 3 bits) source operand is moved to destination operand two operands are exchanged sign-extended all bits of the upper portion are made equal to the high-order bit of the lower portion if then else test the condition. if true, the operations after ?hen are performed. if the condition is false and the optional ?lse clause is present, the operations after ?lse are performed. if the condition is false and else is omitted, the instruction performs no operation. refer to the bcc instruction description as an example. sub?lds and quali?rs {} optional operation () identi?s an indirect address d n displacement value, n-bits wide (example: d 16 is a 16-bit displacement) address calculated effective address (pointer) bit bit selection (example: bit 3 of d0) lsb least signi?ant bit (example: lsb of d0) lsb least signi?ant byte lsw least signi?ant word msb most signi?ant bit msb most signi?ant byte msw most signi?ant word table ii notational conventions (continued) instruction operand syntax f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
about this book xxxix terminology and notational conventions condition code register bit names c carry n negative v over?w x extend z zero table ii notational conventions (continued) instruction operand syntax f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xl mcf5307 users manual terminology and notational conventions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-1 chapter 1 overview this chapter is an overview of the mcf5307 coldfire processor. it includes general descriptions of the modules and features incorporated in the mcf5307. 1.1 features the mcf5307 integrated microprocessor combines a v3 coldfire processor core with the following components, as shown in figure 1-1: 8-kbyte uni ed cache 4-kbyte on-chip sram integer/fractional multiply-accumulate (mac) unit divide unit system debug interface dram controller for synchronous and asynchronous dram four-channel dma controller two general-purpose timers two uarts i 2 c? interface parallel i/o interface system integration module (sim) designed for embedded control applications, the mcf5307 delivers 75 dhrystone 2.1 mips at 90 mhz while minimizing system costs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-2 mcf5307 users manual features figure 1-1. mcf5307 block diagram dram controller chip-select module external bus interface software watchdog tw o two uarts dma i 2 c module jtag debug mac v3 coldfire processor complex system integration module (sim) 8-kbyte cache sram controller div eight-instruction fifo buffer operand execution pipeline (oep) instruction fetch pipeline (ifp) branch logic 32-bit data bus 4-entry store buffer 31 0 four 32-bit address bus ccr general- purpose 31 0 31 0 a0?7 d0?7 ied iag ic1 ic2 dsoc agex interrupt controller local memory bus pll clkin rsti pstclk rsto pclk bclko x n module cs [7:0] 88 8 8 10 icrs mbar imr channels general- purpose timers (sent off-chip cache controller acr0 acr1 cacr csars cscrs csmrs irq [1,3,5,7] 4 dram controller avr ipr irqpar swivr swsr sypcr rsr system control pll control pll base address mpark bus master park dmr0/1 dacr0/1 addr/cntrl mask dram control dcr parallel port pll control signals outputs 4-kbyte sram rambar and to on-chip peripherals) local instruction unit registers memory f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-3 features features common to many embedded applications, such as dmas, various dram controller interfaces, and on-chip memories, are integrated using advanced process technologies. the mcf5307 extends the legacy of motorola?s 68k family by providing a compatible path for 68k and coldfire customers in which development tools and customer code can be leveraged. in fact, customers moving from 68k to coldfire can use code translation and emulation tools that facilitate modifying 68k assembly code to the coldfire architecture. based on the concept of variable-length risc technology, the coldfire family combines the architectural simplicity of conventional 32-bit risc with a memory-saving, variable-length instruction set. in de ning the coldfire architecture for embedded processing applications, a 68k-code compatible core combines performance advantages of a risc architecture with the optimum code density of a streamlined, variable-length m68000 instruction set. by using a variable-length instruction set architecture, embedded system designers using coldfire risc processors enjoy signi cant advantages over conventional xed-length risc architectures. the denser binary code for coldfire processors consumes less memory than many xed-length instruction set risc processors available. this improved code density means more ef cient system memory use for a given application and allows use of slower, less costly memory to help achieve a target performance level. the mcf5307 is the rst standard product to implement the version 3 coldfire microprocessor core. to reach higher levels of frequency and performance, numerous enhancements were made to the v2 architecture. most notable are a deeper instruction pipeline, branch acceleration, and a uni ed cache, which together provide 75 (dhrystone 2.1) mips at 90 mhz. increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. the processor complex frequency is an integer multiple, 2 to 4 times, of the external bus frequency. the core clock can be stopped to support a low-power mode. serial communication channels are provided by an i 2 c interface module and two programmable full-duplex uarts. four channels of dma allow for fast data transfer using a programmable burst mode independent of processor execution. the two 16-bit general-purpose multimode timers provide separate input and output signals. for system protection, the processor includes a programmable 16-bit software watchdog timer. in addition, common system functions such as chip selects, interrupt control, bus arbitration, and an ieee 1149.1 jtag module are included. a sophisticated debug interface supports background-debug mode plus real-time trace and debug with expanded exibility of on-chip breakpoint registers. this interface is present in all coldfire standard products and allows common emulator support across the entire family of microprocessors. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-4 mcf5307 users manual mcf5307 features 1.2 mcf5307 features the following list summarizes mcf5307 features: coldfire processor core ? variable-length risc, clock-multiplied version 3 microprocessor core ? fully code compatible with version 2 processors ? two independent decoupled pipelines: four-stage instruction fetch pipeline (ifp) and two-stage operand execution pipeline (oep) ? eight-instruction fifo buffer provides decoupling between the pipelines ? branch prediction mechanisms for accelerating program execution ? 32-bit internal address bus supporting 4 gbytes of linear address space ? 32-bit data bus ? 16 user-accessible, 32-bit-wide, general-purpose registers ? supervisor/user modes for system protection ? vector base register to relocate exception-vector table ? optimized for high-level language constructs multiply and accumulate unit (mac) ? high-speed, complex arithmetic processing for dsp applications ? tightly coupled to the oep ? three-stage execute pipeline with one clock issue rate for 16 x 16 operations ? 16 x 16 and 32 x 32 multiplies support, all with 32-bit accumulate ? signed or unsigned integer support, plus signed fractional operands hardware integer divide unit ? unsigned and signed integer divide support ? tightly coupled to the oep ? 32/16 and 32/32 operation support producing quotient and/or remainder results 8-kbyte uni ed cache ? four-way set-associative organization ? operates at higher processor core frequency ? provides pipelined, single-cycle access to critical code and data ? supports write-through and copyback modes ? four-entry, 32-bit store buffer to improve performance of operand writes 4-kbyte sram ? programmable location anywhere within 4-gbyte linear address space ? higher core-frequency operation ? pipelined, single-cycle access to critical code or data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-5 mcf5307 features dma controller ? four fully programmable channels: two support external requests ? dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability ? source/destination address pointers that can increment or remain constant ? 24-bit transfer counter per channel ? operand packing and unpacking supported ? auto-alignment transfers supported for ef cient block movement ? bursting and cycle steal support ? two-bus-clock internal access ? automatic dma transfers from on-chip uarts using internal interrupts dram controller ? synchronous dram (sdram), extended-data-out (edo) dram, and fast page mode support ? up to 512 mbytes of dram ? programmable timer provides cas-before-ras refresh for asynchronous drams ? support for two separate memory blocks two uarts ? full-duplex operation ? programmable clock ? modem control signals available (cts , rts ) ? processor-interrupt capability dual 16-bit general-purpose multiple-mode timers ? 8-bit prescaler ? timer input and output pins ? processor-interrupt capability ? up to 22-ns resolution at 45 mhz i 2 c module ? interchip bus interface for eeproms, lcd controllers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master or slave modes support multiple masters ? automatic interrupt generation with programmable level system interface module (sim) ? chip selects provide direct interface to 8-, 16-, and 32-bit sram, rom, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-6 mcf5307 users manual mcf5307 features flash, and memory-mapped i/o devices ? eight fully programmable chip selects, each with a base address register ? programmable wait states and port sizes per chip select ? user-programmable processor clock/input clock frequency ratio ? programmable interrupt controller ? low interrupt latency ? four external interrupt request inputs ? programmable autovector generator ? software watchdog timer 16-bit general-purpose i/o interface ieee 1149.1 test (jtag) module system debug support ? real-time trace for determining dynamic execution path while in emulator mode ? background debug mode (bdm) for debug features while halted ? real-time debug support, including 6 user-visible hardware breakpoint registers supporting a variety of breakpoint con gurations ? supports comprehensive emulator functions through trace and breakpoint logic on-chip pll ? supports processor clock/bus clock ratios of 66/33, 66/22, 66/16.5, 90/45, 90/30, and 90/22.5 ? supports low-power mode product offerings ? 75 dhrystone 2.1 mips at 90 mhz ? implemented in 0.35 , triple-layer-metal process technology with 3.3-v operation (5.0-v compliant i/o pads) ? 208-pin plastic qfp package ? 0?70 c operating temperature 1.2.1 process the mcf5307 is manufactured in a 0.35- cmos process with triple-layer-metal routing technology. this process combines the high performance and low power needed for embedded system applications. inputs are 3.3-v tolerant; outputs are cmos or open-drain cmos with outputs operating from vdd + 0.5 v to gnd - 0.5 v, with guaranteed ttl-level speci cations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-7 coldfire module description 1.3 coldfire module description the following sections provide overviews of the various modules incorporated in the mcf5307. 1.3.1 coldfire core the version 4 coldfire core consists of two independent and decoupled pipelines to maximize performance?the instruction fetch pipeline (ifp) and the operand execution pipeline (oep). 1.3.1.1 instruction fetch pipeline (ifp) the four-stage instruction fetch pipeline (ifp) is designed to prefetch instructions for the operand execution pipeline (oep). because the fetch and execution pipelines are decoupled by a eight-instruction fifo buffer, the fetch mechanism can prefetch instructions in advance of their use by the oep, thereby minimizing the time stalled waiting for instructions. to maximize the performance of branch instructions, the version 3 ifp implements a branch prediction mechanism. backward branches are predicted to be taken. the prediction for forward branches is controlled by a bit in the condition code register (ccr). these predictions allow the ifp to redirect the fetch stream down the path predicted to be taken well in advance of the actual instruction execution. the result is signi cantly improved performance. 1.3.1.2 operand execution pipeline (oep) the prefetched instruction stream is gated from the fifo buffer into the two-stage oep. the oep consists of a traditional two-stage risc compute engine with a register le access feeding an arithmetic/logic unit (alu). the oep decodes the instruction, fetches the required operands and then executes the required function. 1.3.1.3 mac module the mac unit provides signal processing capabilities for the mcf5307 in a variety of applications including digital audio and servo control. integrated as an execution unit in the processor?s oep, the mac unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers, plus signed, xed-point fractional input operands. 1.3.1.4 integer divide module integrated into the oep, the divide module performs operations using signed and unsigned integers. the module supports word and longword divides producing quotients and/or remainders. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-8 mcf5307 users manual coldfire module description 1.3.1.5 8-kbyte uni?d cache the mcf5307 architecture includes an 8-kbyte uni ed cache. this four-way, set-associative cache provides pipelined, single-cycle access on cached instructions and operands. as with all coldfire caches, the cache controller implements a non-lockup, streaming design. the use of processor-local memories decouples performance from external memory speeds and increases available bandwidth for external devices or the on-chip 4-channel dma. the cache implements line- ll buffers to optimize 16-byte line burst accesses. additionally, the cache supports copyback, write-through, or cache-inhibited modes. a 4-entry, 32-bit buffer is used for cache line push operations and can be con gured for deferred write buffering in write-through or cache-inhibited modes. 1.3.1.6 internal 4-kbyte sram the 4-kbyte on-chip sram module provides pipelined, single-cycle access to memory regions mapped to these devices. the memory can be mapped to any 0-modulo-32k location in the 4-gbyte address space. the sram module is useful for storing time-critical functions, the system stack, or heavily-referenced data operands. 1.3.2 dram controller the mcf5307 dram controller provides a direct interface for up to two blocks of dram. the controller supports 8-, 16-, or 32-bit memory widths and can easily interface to pc-100 dimms. a unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. the controller operates in normal mode or in page mode and supports sdrams and edo drams. 1.3.3 dma controller the mcf5307 provides four fully programmable dma channels for quick data transfer. dual- and single-address modes support bursting and cycle steal. data transfers are 32 bits long with packing and unpacking supported along with an auto-alignment option for ef cient block transfers. automatic block transfers from on-chip serial uarts are also supported through the dma channels. 1.3.4 uart modules the mcf5307 contains two uarts, which function independently. either uart can be clocked by the system bus clock, eliminating the need for an external crystal. each uart module interfaces directly to the cpu, as shown in figure 1-2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-9 coldfire module description figure 1-2. uart module block diagram each uart module consists of the following major functional areas: serial communication channel 16-bit divider for clock generation internal channel control logic interrupt control logic each uart contains an programmable clock-rate generator. data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. the uarts include 4-byte and 2-byte fifo buffers. the uart modules also provide several error-detection and maskable-interrupt capabilities. modem support includes request-to-send (rts ) and clear-to-send (cts ) lines. bclko provides the time base through a programmable prescaler. the uart time scale can also be sourced from a timer input. full-duplex, auto-echo loopback, local loopback, and remote loopback modes allow testing of uart connections. the programmable uarts can interrupt the cpu on various normal or error-condition events. 1.3.5 timer module the timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer for use in any of three modes. one mode captures the timer value with an external event. another mode triggers an external signal or interrupts the cpu when the timer reaches a set value, while a third mode counts external events. the timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system bus cycle or an external clock input pin (tin). the programmable timer-output pin generates either an active-low pulse or toggles the output. 1.3.6 i 2 c module the i 2 c interface is a two-wire, bidirectional serial bus used for quick data exchanges between devices. the i 2 c minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over serial interrupt control logic cts rts rxd txd or external clock (tin) internal channel control logic programmable clock communications channel generation system integration module (sim) interrupt controller uart bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-10 mcf5307 users manual coldfire module description short distances among several devices. the i 2 c can operate in master, slave, or multiple-master modes. 1.3.7 system interface the mcf5307 processor provides a direct interface to 8-, 16-, and 32-bit flash, sram, rom, and peripheral devices through the use of fully programmable chip selects and write enables. support for burst roms is also included. through the on-chip pll, users can input a slower clock (16.6 to 45 mhz) that is internally multiplied to create the faster processor clock (33.3 to 90 mhz). 1.3.7.1 external bus interface the bus interface controller transfers information between the coldfire core or dma and memory, peripherals, or other devices on the external bus. the external bus interface provides up to 32 bits of address bus space, a 32-bit data bus, and all associated control signals. this interface implements an extended synchronous protocol that supports bursting operations. simple two-wire request/acknowledge bus arbitration between the mcf5307 processor and another bus master, such as an external dma device, is glueless with arbitration logic internal to the mcf5307 processor. multiple-master arbitration is also available with some simple external arbitration logic. 1.3.7.2 chip selects eight fully programmable chip select outputs support the use of external memory and peripheral circuits with user-de ned wait-state insertion. these signals interface to 8-, 16-, or 32-bit ports. the base address, access permissions, and internal bus transfer terminations are programmable with con guration registers for each chip select. cs0 also provides global chip select functionality of boot rom upon reset for initializing the mcf5307. 1.3.7.3 16-bit parallel port interface a 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin basis. 1.3.7.4 interrupt controller the interrupt controller provides user-programmable control of ten internal peripheral interrupts and implements four external xed interrupt-request pins. each internal interrupt can be programmed to any one of seven interrupt levels and four priority levels within each of these levels. additionally, the external interrupt request pins can be mapped to levels 1, 3, 5, and 7 or levels 2, 4, 6, and 7. autovector capability is available for both internal and external interrupts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-11 coldfire module description 1.3.7.5 jtag to help with system diagnostics and manufacturing testing, the mcf5307 processor includes dedicated user-accessible test logic that complies with the ieee 1149.1a standard for boundary-scan testability, often referred to as the joint test action group, or jtag. for more information, refer to the ieee 1149.1a standard. 1.3.8 system debug interface the coldfire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. through a standard debug interface, users can access real-time trace and debug information. this allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. the debug unit in the mcf5307 is a compatible upgrade to the mcf52xx debug module with added exibility in the breakpoint registers and a new command to view the program counter (pc). the on-chip breakpoint resources include a total of 6 programmable registers?a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit pc register plus a 32-bit pc mask register. these registers can be accessed through the dedicated debug serial communication channel or from the processor?s supervisor mode programming model. the breakpoint registers can be con gured to generate triggers by combining the address, data, and pc conditions in a variety of single or dual-level de nitions. the trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. the mcf5307?s new interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging. to support program trace, the version 3 debug module provides processor status (pst[3:0]) and debug data (ddata[3:0]) ports. these buses and the pstclk output provide execution status, captured operand data, and branch target addresses de ning processor activity at the cpu?s clock rate. 1.3.9 pll module the mcf5307 pll module is shown in figure 1-3. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-12 mcf5307 users manual programming model, addressing modes, and instruction set figure 1-3. pll module the pll module?s three modes of operation are described as follows. reset mode?when rsti is asserted, the pll enters reset mode. at reset, the pll asserts rst o from the mcf5307. the core:bus frequency ratio and other mcf5307 con guration information are sampled during reset. normal mode?in normal mode, the input frequency programmed at reset is clock-multiplied to provide the processor clock (pclk). reduced-power mode?in reduced-power mode, the pclk is disabled by executing a sequence that includes programming a control bit in the system con guration register (scr) and then executing the stop instruction. register contents are retained in reduced-power mode, so the system can be reenabled quickly when an unmasked interrupt or reset is detected. 1.4 programming model, addressing modes, and instruction set the coldfire programming model has two privilege levels?supervisor and user. the s bit in the status register (sr) indicates the privilege level. the processor identi es a logical address that differentiates between supervisor and user modes by accessing either the supervisor or user address space. user mode?when the processor is in user mode (sr[s] = 0), only a subset of registers can be accessed, and privileged instructions cannot be executed. typically, most application processing occurs in user mode. user mode is usually entered by executing a return from exception instruction (rte, assuming the value of sr[s] saved on the stack is 0) or a move, sr instruction (assuming sr[s] is 0). supervisor mode?this mode protects system resources from uncontrolled access by users. in supervisor mode, complete access is provided to all registers and the entire coldfire instruction set. typically, system programmers use the supervisor programming model to implement operating system functions and provide i/o pll clkin rsti divide bclko divide[1:0] freq[1:0] rsto pstclk pclk clkin x 4 by 2 divide by 2, 3, or 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-13 programming model, addressing modes, and instruction set control. the supervisor programming model provides access to the same registers as the user model, plus additional registers for con guring on-chip system resources, as described in section 1.4.3, ?supervisor registers.? exceptions (including interrupts) are handled in supervisor mode. 1.4.1 programming model figure 1-4 shows the mcf5307 programming model. figure 1-4. coldfire mcf5307 programming model 31 0 d0 data registers d1 d2 d3 d4 d5 d6 d7 31 0 a0 address registers a1 a2 a3 a4 a5 a6 a7 stack pointer pc program counter ccr condition code register 31 0 macsr mac status register acc mac accumulator mask mac mask register 15 31 19 (ccr) sr status register must be zeros vbr vector base register cacr cache control register acr0 access control register 0 acr1 access control register 1 rambar ram base address register mbar module base address register user registers supervisor registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-14 mcf5307 users manual programming model, addressing modes, and instruction set 1.4.2 user registers the user programming model is shown in figure 1-4 and summarized in table 1-1. 1.4.3 supervisor registers table 1-2 summarizes the mcf5307 supervisor-level registers. table 1-1. user-level registers register description data registers (d0?7) these 32-bit registers are for bit, byte, word, and longword operands. they can also be used as index registers. address registers (a0?7) these 32-bit registers serve as software stack pointers, index registers, or base address registers. the base address registers can be used for word and longword operations. a7 functions as a hardware stack pointer during stacking for subroutine calls and exception handling. program counter (pc) contains the address of the instruction currently being executed by the mcf5307 processor condition code register (ccr) the ccr is the lower byte of the sr. it contains indicator ?gs that re?ct the result of a previous operation and are used for conditional instruction execution. mac status register (macsr) de?es the operating con?uration of the mac unit and contains indicator ?gs from the results of mac instructions. accumulator (acc) general-purpose register used to accumulate the results of mac operations mask register (mask) general-purpose register provides an optional address mask for mac instructions that fetch operands from memory. it is useful in the implementation of circular queues in operand memory. table 1-2. supervisor-level registers register description status register (sr) the upper byte of the sr provides interrupt information in addition to a variety of mode indicators signaling the operating state of the coldfire processor. the lower byte of the sr is the ccr, as shown in figure 1-4. vector base register (vbr) de?es the upper 12 bits of the base address of the exception vector table used during exception processing. the low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1 mbyte address. cache con?uration register (cacr) de?es the operating modes of the version 4 cache memories. control ?lds con?uring the instruction, data, and branch cache are provided by this register, along with the default attributes for the 4-gbyte address space. access control registers (acr0/1) de?e address ranges and attributes associated with various memory regions within the 4-gbyte address space. each acr de?es the location of a given memory region and assigns attributes such as write-protection and cache mode (copyback, write-through, cacheability). additionally, cacr ?lds assign default attributes to the instruction and data memory spaces. ram base address register (rambar) provide the logical base address for the 4-kbyte sram module and de?e attributes and access types allowed for the sram. module base address register (mbar) de?es the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. overview 1-15 programming model, addressing modes, and instruction set 1.4.4 instruction set the coldfire instruction set supports high-level languages and is optimized for those instructions most commonly generated by compilers in embedded applications. table 2-8 provides an alphabetized listing of the coldfire instruction set opcodes, supported operation sizes, and assembler syntax. for two-operand instructions, the rst operand is generally the source operand and the second is the destination. because the coldfire architecture provides an upgrade path for 68k customers, its instruction set supports most of the common 68k opcodes. a majority of the instructions are binary compatible or optimized 68k opcodes. this feature, when coupled with the code conversion tools from third-party developers, generally minimizes software porting issues for customers with 68k applications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-16 mcf5307 users manual programming model, addressing modes, and instruction set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
p a r t i. mcf5 3 07 p r ocessor core i-xvii part i mcf5 3 07 p r ocessor core intended audience part i is intended for system designers who need a general understanding of the functionality supported by the mcf5307. it also describes the operation of the mcf5307 contents chapter 2, ?coldfire core,? provides an overview of the microprocessor core of the mcf5307. the chapter begins with a description of enhancements from the v2 coldfire core, and then fully describes the v3 programming model as it is implemented on the mcf5307. it also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. chapter 3, ?hardware multiply/accumulate (mac) unit,? describes the mcf5307 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. the mac is integrated into the operand execution pipeline (oep). chapter 4, ?local memory.? this chapter describes the mcf5307 implementation of the coldfire v3 local memory speci cation. it consists of the two following major sections. ? section 4.2, ?sram overview,? describes the mcf5307 on-chip static ram (sram) implementation. it covers general operations, con guration, and initialization. it also provides information and examples showing how to minimize power consumption when using the sram. ? section 4.7, ?cache overview,? describes the mcf5307 cache implementation, including organization, con guration, and coherency. it describes cache operations and how the cache interacts with other memory structures. chapter 5, ?debug support,? describes the revision c enhanced hardware debug support in the mcf5307. this revision of the coldfire debug architecture encompasses earlier revisions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
i-xviii mcf5307 users manual suggested reading the following literature may be helpful with respect to the topics in part i: coldfire programmers reference manual, r1.0 (mcf5200prm/ad) using microprocessors and microcomputers: the motorola family, william c. wray, ross bannatyne, joseph d. green eld acronyms and abbreviations table i-i contains acronyms and abbreviations are used in part i. table i-i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion alu arithmetic logic unit bdm background debug mode bist built-in self test bsdl boundary-scan description language codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing ea effective address edo extended data output (dram) fifo first-in, ?st-out gpio i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ifp instruction fetch pipeline ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lifo last-in, ?st-out lru least recently used lsb least-signi?ant byte lsb least-signi?ant bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
p a r t i. mcf5 3 07 p r ocessor core i-xix mac multiple accumulate unit mbar memory base address register msb most-signi?ant byte msb most-signi?ant bit mux multiplex nop no operation oep operand execution pipeline pc program counter pclk processor clock pll phase-locked loop plru pseudo least recently used por power-on reset pqfp plastic quad ?t pack risc reduced instruction set computing rx receive sim system integration module sof start of frame tap test access port ttl transistor-to-transistor logic tx transmit uart universal asynchronous/synchronous receiver transmitter table i-i. acronyms and abbreviated terms (continued) term meaning f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
i-xx mcf5307 users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-21 chapter 2 coldfire core this chapter provides an overview of the microprocessor core of the mcf5307. the chapter begins with a description of enhancements from the version 2 (v2) coldfire core, and then fully describes the v3 programming model as it is implemented on the mcf5307. it also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. 2.1 features and enhancements the mcf5307 is the rst standard product to contain a version 3 coldfire microprocessor core. to reach higher levels of frequency and performance, numerous enhancements were made to the v2 architecture. most notable are a deeper instruction pipeline, branch acceleration, and a uni ed cache, which together provide 75 (dhrystone 2.1) mips at 90 mhz. the mcf5307 core design emphasizes performance, and backward compatibility represents the next step on the coldfire performance roadmap. the following list summarizes mcf5307 features: variable-length risc, clock-multiplied version 3 microprocessor core two independent, decoupled pipelines?four-stage instruction fetch pipeline (ifp) and two-stage operand execution pipeline (oep) eight-instruction fifo buffer provides decoupling between the pipelines branch prediction mechanisms for accelerating program execution 32-bit internal address bus supporting 4 gbytes of linear address space 32-bit data bus 16 user-accessible, 32-bit-wide, general-purpose registers supervisor/user modes for system protection vector base register to relocate exception-vector table optimized for high-level language constructs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-22 mcf5307 users manual features and enhancements 2.1.1 clock-multiplied microprocessor core the mcf5307 incorporates a clock-multiplying phase-locked loop (pll). increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. the frequency of the processor complex can be 2x, 3x, or 4x the external bus speed. the processor, cache, integrated sram, and misalignment module operate at the higher speed clock (pclk); other system integrated modules operate at the speed of the bus clock (bclko). when combined with the enhanced pipeline structure of the version 3 coldfire core, the processor and its local memories provide a high level of performance for today?s demanding embedded applications. pclk can be disabled to minimize dissipation when a low-power mode is entered. this is described in section 7.2.3, ?reduced-power mode.? 2.1.2 enhanced pipelines the ifp prefetches instructions. the oep decodes instructions, fetches required operands, then executes the speci ed function. the two independent, decoupled pipeline structures maximize performance while minimizing core size. pipeline stages are shown in figure 2-1 and are summarized as follows: four-stage ifp (plus optional instruction buffer stage) ? instruction address generation (iag) calculates the next prefetch address. ? instruction fetch cycle 1 (ic1) initiates prefetch on the processor?s local instruction bus. ? instruction fetch cycle 2 (ic2) completes prefetch on the processor?s instruction local bus. ? instruction early decode (ied) generates time-critical decode signals needed for the oep. ? instruction buffer (ib) optional stage uses fifo queue to minimize effects of fetch latency. two-stage oep ? decode, select/operand fetch (dsoc) decodes the instruction and selects the required components for the effective address calculation, or the operand fetch cycle. ? address generation/execute (agex) calculates the oeprand address, or performs the execution of the instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-23 features and enhancements figure 2-1. coldfire enhanced pipeline 2.1.2.1 instruction fetch pipeline (ifp) because the fetch and execution pipelines are decoupled by an eight-instruction fifo buffer, the ifp can prefetch instructions before the oep needs them, minimizing stalls. 2.1.2.1.1 branch acceleration because the ifp and the oep are decoupled by the instruction buffer, the increased depth of the ifp is generally hidden from the oep?s instruction execution. the one exception is change-of- ow instructions such as unconditional branches or jumps, subroutine calls, and taken conditional branches. to minimize the effects of the increased depth of the ifp, the prefetched instruction stream is monitored for change-of- ow opcodes. when certain types of change-of- ow instructions are detected, the target instruction address is calculated, and fetching immediately begins in the target stream. instruction instruction fifo decode & select, address data[31:0] instruction fetch cycle 2 instruction iag ic1 ic2 ied ib dsoc agex address [31:0] instruction buffer address generation fetch cycle 1 early decode generation, execute operand fetch operand execution pipeline instruction fetch pipeline f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-24 mcf5307 users manual features and enhancements for example, if an unconditional bra instruction is detected, the ied calculates the target of the bra instruction, and the iag immediately begins fetching at the target address. because of the decoupled nature of the two pipelines, the target instruction is available to the oep immediately after the bra instruction, giving it a single-cycle execution time. the acceleration logic uses a static prediction algorithm when processing conditional branch (bcc) instructions. the default scheme is forward bcc instructions are predicted as not-taken, while backward bcc instructions are predicted as taken. a user-mode control bit, ccr[7], allows users to dynamically alter the prediction algorithm for forward bcc instructions. see section 2.2.1.5, ?condition code register (ccr). 2.1.2.2 operand execution pipeline (oep) the oep is a two-stage pipeline featuring a traditional risc datapath with a register le feeding an arithmetic/logic unit. for simple register-to-register instructions, the rst stage of the oep performs the instruction decode and fetching of the required register operands (oc), while the actual instruction execution is performed in the second stage (ex). for memory-to-register instructions, the instruction is effectively staged through the oep twice in the following way: the instruction is decoded and the components of the operand address are selected (ds). the operand address is generated using the ?execute engine? (ag). the memory operand is fetched while any register operand is simultaneously fetched (oc). the instruction is executed (ex). for register-to-memory operations, the stage functions (ds/oc, ag/ex) are effectively performed simultaneously allowing single-cycle execution. for read-modify-write instructions, the pipeline effectively combines a memory-to-register operation with a store operation. 2.1.2.2.1 illegal opcode handling to aid in conversion from m68000 code, every 16-bit operation word is decoded to ensure that each instruction is valid. if the processor attempts execution of an illegal or unsupported instruction, an illegal instruction exception (vector 4) is taken. 2.1.2.2.2 hardware multiply/accumulate (mac) unit the mac is an optional unit in version 3 that provides hardware support for a limited set of digital signal processing (dsp) operations used in embedded code, while supporting the integer multiply instructions in the coldfire microprocessor family. the mac features a three-stage execution pipeline, optimized for 16 x 16 multiplies. it is tightly coupled to the oep, which can issue a 16 x 16 multiply with a 32-bit accumulation plus fetch a 32-bit operand in a single cycle. a 32 x 32 multiply with a 32-bit accumulation requires three cycles before the next instruction can be issued. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-25 features and enhancements figure 2-2 shows basic functionality of the mac. a full set of instructions are provided for signed and unsigned integers plus signed, xed-point fractional input operands. figure 2-2. coldfire multiply-accumulate functionality diagram the mac provides functionality in the following three related areas, which are described in detail in chapter 3, ?hardware multiply/accumulate (mac) unit.? signed and unsigned integer multiplies multiply-accumulate operations with signed and unsigned fractional operands miscellaneous register operations 2.1.2.2.3 hardware divide unit the hardware divide unit performs the following integer division operations: 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder 32-bit operand/32-bit operand producing a 32-bit quotient 32-bit operand/32-bit operand producing a 32-bit remainder 2.1.3 debug module enhancements the coldfire processor core debug interface supports system integration in conjunction with low-cost development tools. real-time trace and debug information can be accessed through a standard interface, which allows the processor and system to be debugged at full speed without costly in-circuit emulators. the mcf5307 debug unit is a compatible upgrade to the mcf52xx debug module with enhancements that include: a new command to obtain the value of the program counter (pc) allowing oring of terms in creating breakpoints increased exibility of the breakpoint registers x +/- operand y operand x shift 0,1,-1 accumulator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-26 mcf5307 users manual programming model on-chip breakpoint resources include the following: con guration/status register (csr) background debug mode (bdm) address attributes register (baar) bus attributes and mask register (aatr) breakpoint registers. these can be used to de ne triggers combining address, data, and pc conditions in single- or dual-level de nitions. they include the following: ? pc breakpoint register (pbr) ? pc breakpoint mask register (pbmr) ? data operand address breakpoint registers (abhr/ablr) ? data breakpoint register (dbr) data breakpoint mask register (dbmr) trigger de nition register (tdr) can be programmed to generate a processor halt or initiate a debug interrupt exception. these registers can be accessed through the dedicated debug serial communication channel, or from the processor?s supervisor programming model, using the wdebug instruction. the enhancements of the revision b debug speci cation are fully backward-compatible with the a revision. for more information, see chapter 5, ?debug support.? 2.2 programming model the mcf5307 programming model consists of three instruction and register groups?user, mac (also user-mode), and supervisor, shown in figure 2-2. user mode programs are restricted to user and mac instructions and programming models. supervisor-mode system software can reference all user-mode and mac instructions and registers and additional supervisor instructions and control registers. the user or supervisor programming model is selected based on sr[s]. the following sections describe the registers in the user, mac, and supervisor programming models. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-27 programming model figure 2-3. coldfire programming model 2.2.1 user programming model as figure 2-3 shows, the user programming model consists of the following registers: 16 general-purpose 32-bit registers, d0?d7 and a0?a7 32-bit program counter 8-bit condition code register 2.2.1.1 data registers (d0?7) registers d0?d7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit) operations. they may also be used as index registers. 2.2.1.2 address registers (a0?6) the address registers (a0?a6) can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations. 31 0 d0 data registers d1 d2 d3 d4 d5 d6 d7 31 0 a0 address registers a1 a2 a3 a4 a5 a6 a7 stack pointer pc program counter ccr condition code register 31 0 macsr mac status register acc mac accumulator mask mac mask register 15 31 19 (ccr) sr status register must be zeros vbr vector base register cacr cache control register acr0 access control register 0 acr1 access control register 1 rambar ram base address register mbar module base address register user registers supervisor registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-28 mcf5307 users manual programming model 2.2.1.3 stack pointer (a7, sp) the processor core supports a single hardware stack pointer (a7) used during stacking for subroutine calls, returns, and exception handling. the stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register. the initial value of a7 is loaded from the reset exception vector, address 0x0000. the same register is used for user and supervisor modes, and may be used for word and longword operations. a subroutine call saves the program counter (pc) on the stack and the return restores the pc from the stack. the pc and the status register (sr) are saved on the stack during exception and interrupt processing. the return from exception instruction restores sr and pc values from the stack. 2.2.1.4 program counter (pc) the pc holds the address of the executing instruction. for sequential instructions, the processor automatically increments pc. when program ow changes, the pc is updated with the target instruction. for some instructions, the pc speci es the base address for pc-relative operand addressing modes. 2.2.1.5 condition code register (ccr) the ccr, figure 2-4, occupies sr[7?0], as shown in figure 2-3. ccr[4?0] are indicator ags based on results generated by arithmetic operations. table 2-1 describes the ccr eldsmac programming modelfigure 2-3 shows the registers in the mac portion of the user programming model. these registers are d escribed as follows:accumulator (acc)?this 32-bit, read/write, general-purpose register is used to accumulate the results of ma c operations. 76543210 field p x n z v c reset 0 00 unde?ed r/w r/w r r/w r/w r/w r/w r/w table 2-1. ccr field descriptions bits name description 7 p branch prediction bit. alters the static prediction algorithm used by the branch acceleration logic in the ifp on forward conditional branches. 0 predicted as not-taken. 1 predicted as taken. 6? reserved, should be cleared. 4 x extend condition code bit. assigned the value of the carry bit for arithmetic operations; otherwise not affected or set to a speci?d result. also used as an input operand for multiple-precision arithmetic. 3 n negative condition code bit. set if the msb of the result is set; otherwise cleared. 2 z zero condition code bit. set if the result equals zero; otherwise cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-29 programming model mask register (mask)?this 16-bit general-purpose register provides an optional address mask for mac instructions that fetch operands from memory. it is useful in the implementation of circular queues in operand memory. mac status register (macsr)?this 8-bit register de nes con guration of the mac unit and contains indicator ags affected by mac instructions. unless noted otherwise, macsr indicator ag settings are based on the nal result, that is, the result of the nal operation involving the product and accumulator. 2.2.2 supervisor programming model the mcf5307 supervisor programming model is shown in figure 2-3. typically, system programmers use the supervisor programming model to implement operating system functions and provide memory and i/o control. the supervisor programming model provides access to the user registers and additional supervisor registers, which include the upper byte of the status register (sr), the vector base register (vbr), and registers for con guring attributes of the address space connected to the version 3 processor core. most supervisor-mode registers are accessed by using the movec instruction with the control register de nitions in table 2-2. 2.2.2.1 status register (sr) the sr stores the processor status, the interrupt priority mask, and other control bits. supervisor software can read or write the entire sr; user software can read or write only sr[7?0], described in section 2.2.1.5, ?condition code register (ccr).? the control bits indicate processor states?trace mode (t), supervisor or user mode (s), and master or interrupt state (m). sr is set to 0x27 xx after reset. 1 v over?w condition code bit. set if an arithmetic over?w occurs, implying that the result cannot be represented in the operand size; otherwise cleared. 0 c carry condition code bit. set if a carry-out of the data operand msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. table 2-2. movec register map rc[11?] register de?ition 0x002 cache control register (cacr) 0x004 access control register 0 (acr0) 0x005 access control register 1 (acr1) 0x801 vector base register (vbr) 0xc04 ram base address register (rambar) 0xc0f module base address register (mbar) table 2-1. ccr field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-30 mcf5307 users manual programming model table 2-3 describes sr elds. 2.2.2.2 vector base register (vbr) the vbr holds the base address of the exception vector table in memory. the displacement of an exception vector is added to the value in this register to access the vector table. vbr[19?0] are not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-mbyte boundary. 2.2.2.3 cache control register (cacr) the cacr controls operation of both the instruction and data cache memory. it includes bits for enabling, freezing, and invalidating cache contents. it also includes bits for de ning the default cache mode and write-protect elds. see section 4.10.1, ?cache control register (cacr).? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 system byte condition code register (ccr) field t s m i p x n z v c reset 00100 111 0 00 r/w r/w r r/w r/w r r/w r/w r r/w r/w r/w r/w r/w figure 2-5. status register (sr) table 2-3. status field descriptions bits name description 15 t trace enable. when t is set, the processor performs a trace exception after every instruction. 13 s supervisor/user state. indicates whether the processor is in supervisor or user mode 0 user mode 1 supervisor mode 12 m master/interrupt state. cleared by an interrupt exception. it can be set by software during execution of the rte or move to sr instructions so the os can emulate an interrupt stack pointer. 10? i interrupt priority mask. de?es the current interrupt priority. interrupt requests are inhibited for all priority levels less than or equal to the current priority, except the edge-sensitive level-7 request, which cannot be masked. 7? ccr condition code register. see table 2-1. 313029282726252423222120191817161514131211109876543210 field exception vector table base address reset 0000_0000_0000_0000_0000_0000_0000_0000 r/w written from a bdm serial command or from the cpu using the movec instruction. vbr can be read from the debug module only. the upper 12 bits are returned, the low-order 20 bits are unde?ed. rc[11?] 0x801 figure 2-6. vector base register (vbr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-31 integer data formats 2.2.2.4 access control registers (acr0?cr1) the access control registers (acr0?acr1) de ne attributes for two user-de ned memory regions. attributes include de nition of cache mode, write protect and buffer write enables. see section 4.10.2, ?access control registers (acr0?acr1).? 2.2.2.5 ram base address register (rambar) the rambar register determines the base address location of the internal sram module and indicates the types of references mapped to it. the rambar includes a base address, write-protect bit, address space mask bits, and an enable. the ram base address must be aligned on a 0-modulo-32-kbyte boundary. see section 4.4.1, ?sram base address register (rambar).? 2.2.2.6 module base address register (mbar) the module base address register (mbar) de nes the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals. see section 6.2.2, ?module base address register (mbar).? 2.3 integer data formats table 2-4 lists the integer operand data formats. integer operands can reside in registers, memory, or instructions. the operand size for each instruction is either explicitly encoded in the instruction or implicitly de ned by the instruction operation. 2.4 organization of data in registers the following sections describe data organization within the data, address, and control registers. 2.4.1 organization of integer data formats in registers figure 2-7 shows the integer format for data registers. each integer data register is 32 bits wide. byte and word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. longword operands occupy the entire 32 bits of integer data registers. a data register that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations, respectively. the remaining table 2-4. integer data formats operand data format size bit 1 bit byte integer 8 bits word integer 16 bits longword integer 32 bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-32 mcf5307 users manual organization of data in registers high-order portion does not change. the least signi cant bit (lsb) of all integer sizes is zero, the most-signi cant bit (msb) of a longword integer is 31, the msb of a word integer is 15, and the msb of a byte integer is 7. the instruction set encodings do not allow the use of address registers for byte-sized operands. when an address register is a source operand, either the low-order word or the entire longword operand is used, depending on the operation size. word-length source operands are sign-extended to 32 bits and then used in the operation with anaddress register destination. when an address register is a destination, the entire register is affected, regardless of the operation size. figure 2-8 shows integer formats for address registers. the size of control registers varies according to function. some have unde ned bits reserved for future de nition by motorola. those particular bits read as zeros and must be written as zeros for future compatibility. all operations to the sr and ccr are word-size operations. for all ccr operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege mode. 2.4.2 organization of integer data formats in memory all coldfire processors use a big-endian addressing scheme. the byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. the address n of a longword data item corresponds to the address of the high-order word. the lower order word is located at address n + 2. the address n of a word data item corresponds to the address of the high-order byte. the lower order byte is located at address n + 1. this 31 30 1 0 msb lsb bit (0 bit number 31) 31 7 0 not used msb low order byte lsb byte (8 bits) 31 15 0 not used msb lower order word lsb word (16 bits) 31 0 msb longword lsb longword (32 bits) figure 2-7. organization of integer data formats in data registers 31 16 15 0 sign-extended 16-bit address operand 31 0 full 32-bit address operand figure 2-8. organization of integer data formats in address registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-33 addressing mode summary organization is shown in figure 2-9. 2.5 addressing mode summary addressing modes are categorized by how they are used. data addressing modes refer to data operands. memory addressing modes refer to memory operands. alterable addressing modes refer to alterable (writable) data operands. control addressing modes refer to memory operands without an associated size. these categories sometimes combine to form more restrictive categories. two combined classi cations are alterable memory (both alterable and memory) and data alterable (both alterable and data). twelve of the most commonly used effective addressing modes from the m68000 family are available on coldfire microprocessors. table 2-5 summarizes these modes and their categories; 31 23 15 7 0 longword 0x0000_0000 word 0x0000_0000 word 0x0000_0002 byte 0x0000_0000 byte 0x0000_0001 byte 0x0000_0002 byte 0x0000_0003 longword 0x0000_0004 word 0x0000_0004 word 0x0000_0006 byte 0x0000_0004 byte 0x0000_0005 byte 0x0000_0006 byte 0x0000_0007 . . . longword 0xffff_fffc word 0xffff_fffc word 0xffff_fffe byte 0xffff_fffc byte 0xffff_fffd byte 0xffff_fffe byte 0xffff_ffff figure 2-9. memory operand addressing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-34 mcf5307 users manual instruction set summary 2.6 instruction set summary the coldfire instruction set is a simpli ed version of the m68000 instruction set. the removed instructions include bcd, bit eld, logical rotate, decrement and branch, and integer multiply with a 64-bit result. nine new mac instructions have been added. table 2-6 lists notational conventions used throughout this manual. table 2-5. coldfire effective addressing modes addressing modes syntax mode field reg. field category data memory control alterable register direct data address dn an 000 001 reg. no. reg. no. x x x register indirect address address with postincrement address with predecrement address with displacement (an) (an)+ ?an) (d 16 , an) 010 011 100 101 reg. no. reg. no. reg. no. reg. no. x x x x x x x x x x x x x x address register indirect with index 8-bit displacement (d 8 , an, xi) 110 reg. no. x x x x program counter indirect with displacement (d 16 , pc) 111 010 x x x program counter indirect with index 8-bit displacement (d 8 , pc, xi) 111 011 x x x absolute data addressing short long (xxx).w (xxx).l 111 111 000 001 x x x x x x immediate # 111 100 x x table 2-6. notational conventions instruction operand syntax opcode wildcard cc logical condition (example: ne for not equal) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-35 instruction set summary register speci?ations an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rc any control register (example vbr is the vector base register) rm mac registers (acc, mac, mask) rn any address or data register rw destination register w (used for mac instructions only) ry,rx any source and destination registers, respectively xi index register i (can be an address or data register: ai, di) register names acc mac accumulator register ccr condition code register (lower byte of sr) macsr mac status register mask mac mask register pc program counter sr status register port name ddata debug data port pst processor status port miscellaneous operands # immediate data following the 16-bit operation word of the instruction effective address y,x source and destination effective addresses, respectively assembly language program label list of registers for movem instruction (example: d3?0) shift operation: shift left (<<), shift right (>>) operand data size: byte (b), word (w), longword (l) uc uni?d cache # identi?s the 4-bit vector number for trap instructions identi?s an indirect data address referencing memory identi?s an absolute address referencing memory dn signal displacement value, n bits wide (example: d16 is a 16-bit displacement) sf scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for mac operations) table 2-6. notational conventions (continued) instruction operand syntax f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-36 mcf5307 users manual instruction set summary operations + arithmetic addition or postincrement indicator arithmetic subtraction or predecrement indicator x arithmetic multiplication / arithmetic division ~ invert; operand is logically complemented & logical and | logical or ^ logical exclusive or << shift left (example: d0 << 3 is shift d0 left 3 bits) >> shift right (example: d0 >> 3 is shift d0 right 3 bits) source operand is moved to destination operand two operands are exchanged sign-extended all bits of the upper portion are made equal to the high-order bit of the lower portion if then else test the condition. if the condition is true, the operations in the then clause are performed. if the condition is false and the optional else clause is present, the operations in the else claue are performed. if the condition is false and the else clause is omitted, the instruction performs no operation. refer to the bcc instruction description as an example. sub?lds and quali?rs {} optional operation () identi?s an indirect address d n displacement value, n-bits wide (example: d 16 is a 16-bit displacement) address calculated effective address (pointer) bit bit selection (example: bit 3 of d0) lsb least signi?ant bit (example: lsb of d0) lsb least signi?ant byte lsw least signi?ant word msb most signi?ant bit msb most signi?ant byte msw most signi?ant word condition code register bit names table 2-6. notational conventions (continued) instruction operand syntax f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-37 instruction set summary 2.6.1 instruction set summary table 2-7 lists implemented user-mode instructions by opcode. p branch prediction c carry n negative v over?w x extend z zero table 2-7. user-mode instruction set summary instruction operand syntax operand size operation add dy,x y,dx .l .l source + destination destination adda y,ax .l source + destination destination addi #,dx .l immediate data + destination destination addq #,x .l immediate data + destination destination addx dy,dx .l source + destination + x destination and dy,x y,dx .l .l source & destination destination andi #,dx .l immediate data & destination destination asl dy,dx #,dx .l .l x/c (dx << dy) 0 x/c (dx << #) 0 asr dy,dx #,dx .l .l msb (dx >> dy) x/c msb (dx >> #) x/c bcc .b,.w if condition true, then pc + 2 + d n pc bchg dy,x #,x .b,.l .b,.l ~( of destination) z, bit of destination bclr dy,x #,x .b,.l .b,.l ~( of destination) z; 0 bit of destination bra .b,.w pc + 2 + d n pc bset dy,x #,x .b,.l .b,.l ~( of destination) z; 1 bit of destination bsr .b,.w sp ?4 sp; next sequential pc (sp); pc + 2 + d n pc btst dy,x #,x .b,.l .b,.l ~( of destination) z clr y,dx .b,.w,.l 0 destination cmp y,ax .l destination ?source cmpa y,dx .l destination ?source table 2-6. notational conventions (continued) instruction operand syntax f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-38 mcf5307 users manual instruction set summary cmpi y,dx .l destination ?immediate data divs y,dx y,dx .w .l dx /y dx {16-bit remainder; 16-bit quotient} dx /y dx {32-bit quotient} signed operation divu y,dx dy,x .w .l dx /y dx {16-bit remainder; 16-bit quotient} dx /y dx {32-bit quotient} unsigned operation eor dy,x .l source ^ destination destination eori #,dx .l immediate data ^ destination destination ext #,dx .b .w .w .l sign-extended destination destination extb dx .b .l sign-extended destination destination halt 1 none unsized enter halted state jmp y unsized address of pc jsr y unsized sp ?4 sp; next sequential pc (sp); pc lea y,ax .l ax link ax,# .w sp ?4 sp; ax (sp); sp ax; sp + d16 sp lsl dy,dx #,dx .l .l x/c (dx << dy) 0 x/c (dx << #) 0 lsr dy,dx #,dx .l .l 0 (dx >> dy) x/c 0 (dx >> #) x/c mac ry,rxsf .l + (.w .w) .l .l + (.l .l) .l acc + (ry rx){<< 1 | >> 1} acc acc + (ry rx){<< 1 | >> 1} acc; (y{&mask}) rw macl ry,rxsf,y,rw .l + (.w .w) .l, .l .l + (.l .l) .l, .l acc + (ry rx){<< 1 | >> 1} acc acc + (ry rx){<< 1 | >> 1} acc; (y{&mask}) rw move y,x .b,.w,.l y x move from mac mask,rx acc,rx macsr,rx .l rm rx macsr,ccr .l macsr ccr move to mac ry,acc ry,macsr ry,mask .l ry rm #,acc #,macsr #,mask .l # rm move from ccr ccr,dx .w ccr dx move to ccr dy,ccr #,ccr .b dy ccr # ccr movea y,ax .w,.l .l source destination table 2-7. user-mode instruction set summary (continued) instruction operand syntax operand size operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-39 instruction set summary movem #,x y,# .l .l listed registers destination source listed registers moveq #,dx .b .l sign-extended immediate data destination msac ry,rxsf .l - (.w .w) .l .l - (.l .l) .l acc ?(ry rx){<< 1 | >> 1} acc msacl ry,rxsf,y,rw .l - (.w .w) .l, .l .l - (.l .l) .l, .l acc ?(ry rx){<< 1 | >> 1} acc; (y{&mask}) rw muls y,dx .w x .w .l .l x .l .l source destination destination signed operation mulu y,dx .w x .w .l .l x .l .l source destination destination unsigned operation neg dx .l 0 ?destination destination negx dx .l 0 ?destination ?x destination nop none unsized synchronize pipelines; pc + 2 pc not dx .l ~ destination destination or y,dx dy,x .l source | destination destination ori #,dx .l immediate data | destination destination pea y .l sp ?4 sp; address of (sp) pulse none unsized set pst= 0x4 rems ,dx .l dx/y dw {32-bit remainder} signed operation remu ,dx .l dx/y dw {32-bit remainder} unsigned operation rts none unsized (sp) pc; sp + 4 sp scc dx .b if condition true, then 1s ? destination; else 0s destination sub y,dx dy,x .l .l destination ?source destination suba y,ax .l destination ?source destination subi #,dx .l destination ?immediate data destination subq #,x .l destination ?immediate data destination subx dy,dx .l destination ?source ?x destination swap dx .w msw of dx lsw of dx trap # unsized sp ?4 sp;pc (sp); sp ?2 sp;sr (sp); sp ?2 sp; format (sp); vector address pc trapf none # unsized .w .l pc + 2 pc pc + 4 pc pc + 6 pc table 2-7. user-mode instruction set summary (continued) instruction operand syntax operand size operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-40 mcf5307 users manual instruction timing table 2-8 describes supervisor-mode instructions. 2.7 instruction timing the timing data presented in this section assumes the following: the oep is loaded with the opword and all required extension words at the beginning of each instruction execution. this implies that the oep spends no time waiting for the ifp to supply opwords and/or extension words. the oep experiences no sequence-related pipeline stalls. for the mcf5307, the most common example of this type of stall involves consecutive store operations, excluding the movem instruction. for all store operations (except movem), tst y .b,.w,.l set condition codes unlk ax unsized ax sp; (sp) ax; sp + 4 sp wddata y .b,.w,.l y ddata port 1 by default the halt instruction is a supervisor-mode instruction; however, it can be con?ured to allow user-mode execution by setting csr[uhe]. table 2-8. supervisor-mode instruction set summary instruction operand syntax operand size operation cpushl (an) unsized invalidate instruction cache line push and invalidate data cache line push data cache line and invalidate (i,d)-cache lines halt 1 1 the halt instruction can be con?ured to allow user-mode execution by setting csr[uhe]. none unsized enter halted state move from sr sr, dx .w sr dx move to sr dy,sr #,sr .w source sr movec ry,rc .l ry rc rc register de?ition 0x002 cache control register (cacr) 0x004 access control register 0 (acr0) 0x005 access control register 1 (acr1) 0x006 access control register 2 (acr2) 0x007 access control register 3 (acr3) 0x801 vector base register (vbr) 0xc04 ram base address register 0 (rambar0) 0xc05 ram base address register 1 (rambar1) rte none unsized (sp+2) sr; sp+4 sp; (sp) pc; sp + format?ld ? sp stop # .w immediate data sr; enter stopped state wdebug y .l y debug module table 2-7. user-mode instruction set summary (continued) instruction operand syntax operand size operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-41 instruction timing certain hardware resources within the processor are marked as ?busy? for two clock cycles after the nal dsoc cycle of the store instruction. if a subsequent store instruction is encountered within this two-cycle window, it is stalled until the resource again becomes available. thus, the maximum pipeline stall involving consecutive store operations is two cycles. the oep can complete all memory accesses without memory causing any stall conditions. thus, timing details in this section assume an in nite zero-wait state memory attached to the core. all operand data accesses are assumed to be aligned on the same byte boundary as the operand size: ? 16-bit operands aligned on 0-modulo-2 addresses ? 32-bit operands aligned on 0-modulo-4 addresses operands that do not meet these guidelines are misaligned. table 2-9 shows how the core decomposes a misaligned operand reference into a series of aligned accesses. 2.7.1 move instruction execution times the execution times for the move.{b,w,l} instructions are shown in the next tables. table 2-12 shows the timing for the other generic move operations. note: for all tables in this chapter, the execution time of any instruction using the pc-relative effective addressing modes is equivalent to the time using comparable an-relative mode. et with { = (d16,pc)} equals et with { = (d16,an)} et with { = (d8,pc,xi*sf)} equals et with { = (d8,an,xi*sf)} the nomenclature ?(xxx).wl? refers to both forms of absolute addressing, (xxx).w and (xxx).l. table 2-9. misaligned operand references a[1:0] size bus operations additional c(r/w) 1 1 each timing entry is presented as c(r/w), described as follows: c is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all internal core cycles required to complete the instruction execution. r/w is the number of operand reads (r) and writes (w) required by the instruction. an operation performing a read-modify write function is denoted as (1/1). x1 word byte, byte 2(1/0) if read 1(0/1) if write x1 long byte, word, byte 3(2/0) if read 2(0/2) if write 10 long word, word 2(1/0) if read 1(0/1) if write f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-42 mcf5307 users manual instruction timing table 2-10 lists execution times for move.{b,w} instructions. table 2-11 lists timings for move.l. table 2-12 gives execution times for move.l instructions accessing program-visible registers of the mac unit, along with other move.l timings. execution times for moving contents of the acc or macsr into a destination location represent the best-case scenario when the store instruction is executed and there are no load or mac or msac instruction table 2-10. move byte and word execution times source destination rx (ax) (ax)+ -(ax) (d16,ax) (d8,ax,xi*sf) (xxx).wl dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) (ay)+ 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) -(ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) (d16,ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) (d8,ay,xi*sf) 5(1/0) 5(1/1) 5(1/1) 5(1/1) (xxx).w 4(1/0) 4(1/1) 4(1/1) 4(1/1) (xxx).l 4(1/0) 4(1/1) 4(1/1) 4(1/1) (d16,pc) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) (d8,pc,xi*sf) 5(1/0) 5(1/1) 5(1/1) 5(1/1) # 1(0/0) 2(0/1) 2(0/1) 2(0/1) table 2-11. move long execution times source destination rx (ax) (ax)+ -(ax) (d16,ax) (d8,ax,xi*sf) (xxx).wl dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) (ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) -(ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) (d16,ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) (d8,ay,xi*sf) 4(1/0) 4(1/1) 4(1/1) 4(1/1) (xxx).w 3(1/0) 3(1/1) 3(1/1) 3(1/1) (xxx).l 3(1/0) 3(1/1) 3(1/1) 3(1/1) (d16,pc) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) (d8,pc,xi*sf) 4(1/0) 4(1/1) 4(1/1) 4(1/1) # 1(0/0) 2(0/1) 2(0/1) 2(0/1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-43 instruction timing in the mac execution pipeline. 2.7.2 execution timings?ne-operand instructions table 2-13 shows standard timings for single-operand instructions. 2.7.3 execution timings?wo-operand instructions table 2-14 shows standard timings for two-operand instructions. table 2-12. mac move execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # move.l ,acc 1(0/0) 1(0/0) move.l ,macsr 2(0/0) 2(0/0) move.l ,mask 1(0/0) 1(0/0) move.l acc,rx 3(0/0) move.l macsr,ccr 3(0/0) move.l macsr,rx 3(0/0) move.l mask,rx 3(0/0) table 2-13. one-operand instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl #xxx clr.b 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) clr.w 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) clr.l 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) ext.w dx 1(0/0) ext.l dx 1(0/0) extb.l dx 1(0/0) neg.l dx 1(0/0) negx.l dx 1(0/0) not.l dx 1(0/0) scc dx 1(0/0) swap dx 1(0/0) tst.b 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) tst.w 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) tst.l 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-44 mcf5307 users manual instruction timing table 2-14. two-operand instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # add.l ,rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) add.l dy, 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) addi.l #imm,dx 1(0/0) addq.l #imm, 1(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) addx.l dy,dx 1(0/0) and.l ,rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) and.l dy, 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) andi.l #imm,dx 1(0/0) asl.l ,dx 1(0/0) 1(0/0) asr.l ,dx 1(0/0) 1(0/0) bchg dy, 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) 6(1/1) 5(1/1) bchg #imm, 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) bclr dy, 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) 6(1/1) 5(1/1) bclr #imm, 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) bset dy, 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) 6(1/1) 5(1/1) bset #imm, 2(0/0) 5(1/1) 5(1/1) 5(1/1) 5(1/1) btst dy, 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) btst #imm, 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) cmp.l ,rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) cmpi.l #imm,dx 1(0/0) divs.w ,dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) divu.w ,dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) divs.l ,dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) divu.l ,dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) eor.l dy, 1(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) eori.l #imm,dx 1(0/0) lea ,ax 1(0/0) 1(0/0) 2(0/0) 1(0/0) lsl.l ,dx 1(0/0) 1(0/0) lsr.l ,dx 1(0/0) 1(0/0) mac.w ry,rx 1(0/0) mac.l ry,rx 3(0/0) msac.w ry,rx 1(0/0) msac.l ry,rx 3(0/0) mac.w ry,rx,ea,rw 3(1/0) 3(1/0) 3(1/0) 3(1/0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-45 instruction timing 2.7.4 miscellaneous instruction execution times table 2-15 lists timings for miscellaneous instructions. mac.l ry,rx,ea,rw 5(1/0) 5(1/0) 5(1/0) 5(1/0) moveq #imm,dx 1(0/0) msac.w ry,rx,ea,rw 3(1/0) 3(1/0) 3(1/0) 3(1/0) msac.l ry,rx,ea,rw 5(1/0) 5(1/0) 5(1/0) 5(1/0) muls.w ,dx 3(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 3(0/0) mulu.w ,dx 3(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 3(0/0) muls.l ,dx 5(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) mulu.l ,dx 5(0/0) 8(1/0) 8(1/0) 8(1/0) 8(1/0) or.l ,rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) or.l dy, 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) or.l #imm,dx 1(0/0) rems.l ,dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) remu.l ,dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) sub.l ,rx 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) sub.l dy, 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) subi.l #imm,dx 1(0/0) subq.l #imm, 1(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) subx.l dy,dx 1(0/0) table 2-15. miscellaneous instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # cpushl (ax) 11(0/1) link.w ay,#imm 2(0/1) move.w ccr,dx 1(0/0) move.w ,ccr 1(0/0) 1(0/0) move.w sr,dx 1(0/0) move.w ,sr 9(0/0) 9(0/0) 1 movec ry,rc 11(0/1) movem.l 2 ,&list 2+n(n/0) 2+n(n/0) movem.l &list, 2+n(0/n) 2+n(0/n) table 2-14. two-operand instruction execution times (continued) opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-46 mcf5307 users manual instruction timing 2.7.5 branch instruction execution times table 2-16 shows general branch instruction timing. for the conditional branch opcodes (bcc), a static algorithm is used to determine the prediction state of the branch. this algorithm is: if bcc is a forward branch && ccr[7] == 0 then the bcc is predicted as not-taken nop 3(0/0) pea 2(0/1) 2(0/1) 3 3(0/1) 4 2(0/1) pulse 1(0/0) stop #imm 3(0/0) 5 trap #imm 18(1/2) trapf 1(0/0) trapf.w 1(0/0) trapf.l 1(0/0) unlk ax 3(1/0) wddata.l 7(1/0) 7(1/0) 7(1/0) 7(1/0) 8(1/0) 7(1/0) wdebug.l 10(2/0) 10(2/0) 1 if a move.w #imm,sr instruction is executed and #imm[13] = 1, the execution time is 1(0/0). 2 n is the number of registers moved by the movem opcode. 3 pea execution times are the same for (d16,pc). 4 pea execution times are the same for (d8,pc,xi*sf). 5 the execution time for stop is the time required until the processor begins sampling continuously for interrupts. table 2-16. general branch instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # bra 1(0/1) 1 1 assumes branch acceleration. depending on the pipeline status, execution times may vary from 1 to 3 cycles. bsr 1(0/1) 1 jmp 5(0/0) 5(0/0) 1 6(0/0) 1(0/0) 1 jsr 5(0/1) 5(0/1) 6(0/1) 1(0/1) 1 rte 14(2/0) rts 8(1/0) table 2-15. miscellaneous instruction execution times (continued) opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-47 exception processing overview if bcc is a forward branch && ccr[7] == 1 then the bcc is predicted as taken else if bcc is a backward branch then the bcc is predicted as taken table 2-17 shows timing for bcc instructions. 2.8 exception processing overview exception processing for coldfire processors is streamlined for performance. differences from previous m68000 family processors include the following: a simpli ed exception vector table reduced relocation capabilities using the vector base register a single exception stack frame format use of a single, self-aligning system stack pointer coldfire processors use an instruction restart exception model but require more software support to recover from certain access errors. see table 2-18 for details. exception processing can be de ned as the time from the detection of the fault condition until the fetch of the rst handler instruction has been initiated. it is comprised of the following four major steps: 1. the processor makes an internal copy of the sr and then enters supervisor mode by setting sr[s] and disabling trace mode by clearing sr[t]. the occurrence of an interrupt exception also forces sr[m] to be cleared and the interrupt priority mask to be set to the level of the current interrupt request. 2. the processor determines the exception vector number. for all faults except interrupts, the processor performs this calculation based on the exception type. for interrupts, the processor performs an interrupt-acknowledge (iack) bus cycle to obtain the vector number from a peripheral device. the iack cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address. 3. the processor saves the current context by creating an exception stack frame on the system stack. coldfire processors support a single stack pointer in the a7 address register; therefore, there is no notion of separate supervisor and user stack pointers. as a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. additionally, the processor uses a simpli ed table 2-17. bcc instruction execution times opcode predicted correctly as taken predicted correctly as not taken predicted incorrectly bcc 1(0/0) 1(0/0) 5(0/0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-48 mcf5307 users manual exception processing overview xed-length stack frame for all exceptions. the exception type determines whether the program counter in the exception stack frame de nes the address of the faulting instruction (fault) or of the next instruction to be executed (next). 4. the processor acquires the address of the rst instruction of the exception handler. the exception vector table is aligned on a 1-mbyte boundary. this instruction address is obtained by fetching a value from the table at the address de ned in the vector base register. the index into the exception table is calculated as 4 x vector_number. when the index value is generated, the vector table contents determine the address of the rst instruction of the desired handler. after the fetch of the rst opcode of the handler is initiated, exception processing terminates and normal instruction processing continues in the handler. coldfire processors support a 1024-byte vector table aligned on any 1-mbyte address boundary; see table 2-18. the table contains 256 exception vectors where the rst 64 are de ned by motorola; the remaining 192 are user-de ned interrupt vectors. table 2-18. exception vector assignments vector numbers vector offset (hex) stacked program counter 1 assignment 0 000 initial stack pointer 1 004 initial program counter 2 008 fault access error 3 00c fault address error 4 010 fault illegal instruction 5 014 fault divide by zero 6? 018?1c reserved 8 020 fault privilege violation 9 024 next trace 10 028 fault unimplemented line-a opcode 11 02c fault unimplemented line-f opcode 12 030 next debug interrupt 13 034 reserved 14 038 fault format error 15 03c next uninitialized interrupt 16?3 040?5c reserved 24 060 next spurious interrupt 25?1 064?7c next level 1? autovectored interrupts 32?7 080?bc next trap #0?5 instructions 48?0 0c0?f0 reserved 61 0f4 fault unsupported instruction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-49 exception processing overview coldfire processors inhibit sampling for interrupts during the rst instruction of all exception handlers. this allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register. 2.8.1 exception stack frame de?ition the exception stack frame is shown in figure 2-10. the rst longword of the exception stack frame contains the 16-bit format/vector word (f/v) and the 16-bit status register. the second longword contains the 32-bit program counter address. the 16-bit format/vector word contains three unique elds: format eld?this 4-bit eld at the top of the system stack is always written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format. see table 2-19. this eld records any longword misalignment of the stack pointer that may have existed when the exception occurred. fault status eld?the 4-bit eld, fs[3?0], at the top of the system stack is de ned for access and address errors along with interrupted debug service routines. see table 2-20. 62?3 0f8?fc reserved 64?55 100?fc next user-de?ed interrupts 1 the term ?ault refers to the pc of the instruction that caused the exception. the term ?ext refers to the pc of the instruction that immediately follows the instruction that caused the fault. 31 28 27 26 25 18 17 16 15 0 a7 format fs[3?] vector[7?] fs[10] status register + 0x04 program counter [31?] figure 2-10. exception stack frame form table 2-19. format field encoding original a7 at time of exception, bits 1? a7 at first instruction of handler format field bits 31?8 00 original a[7?] 0100 01 original a[7?] 0101 10 original a[7?0] 0110 11 original a[7?1] 0111 table 2-18. exception vector assignments (continued) vector numbers vector offset (hex) stacked program counter 1 assignment f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-50 mcf5307 users manual exception processing overview vector number?this 8-bit eld, vector[7?0], de nes the exception type. it is calculated by the processor for internal faults and is supplied by the peripheral for interrupts. see table 2-18. 2.8.2 processor exceptions table 2-21 describes mcf5307 exceptions. table 2-20. fault status encodings fs[3?] de?ition 0000 not an access or address error 0001-001x reserved 0100 error on instruction fetch 0101?11x reserved 1000 error on operand write 1001 attempted write to write-protected space 101x reserved 1100 error on operand read 1101?11x reserved table 2-21. mcf5307 exceptions exception description access error access errors are reported only in conjunction with an attempted store to write-protected memory. thus, access errors associated with instruction fetch or operand read accesses are not possible. address error caused by an attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target address is set), an attempted use of a word-sized index register (xi.w) or a scale factor of 8 on an indexed effective addressing mode, or attempted execution of an instruction with a full-format indexed addressing mode. illegal instruction on version 2 coldfire implementations, only some illegal opcodes were decoded and generated an illegal instruction exception. the version 3 processor decodes the full 16-bit opcode and generates this exception if execution of an unsupported instruction is attempted. additionally, attempting to execute an illegal line a or line f opcode generates unique exception types: vectors 10 and 11, respectively. coldfire processors do not provide illegal instruction detection on extension words of any instruction, including movec. attempting to execute an instruction with an illegal extension word causes unde?ed results. divide by zero attempted division by zero causes an exception (vector 5, offset = 0x014) except when the pc points to the faulting instruction (divu, divs, remu, rems). privilege violation caused by attempted execution of a supervisor mode instruction while in user mode. the coldfire programmer?s reference manual lists supervisor- and user-mode instructions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. coldfire core 2-51 exception processing overview trace exception coldfire processors provide instruction-by-instruction tracing. while the processor is in trace mode (sr[t] = 1), instruction completion signals a trace exception. this allows a debugger to monitor program execution. the only exception to this de?ition is the stop instruction. if the processor is in trace mode, the instruction before the stop executes and then generates a trace exception. in the exception stack frame, the pc points to the stop opcode. when the trace handler is exited, the stop instruction is executed, loading the sr with the immediate operand from the instruction. the processor then generates a trace exception. the pc in the exception stack frame points to the instruction after stop, and the sr re?cts the just-loaded value. if the processor is not in trace mode and executes a stop instruction where the immediate operand sets the trace bit in the sr, hardware loads the sr and generates a trace exception. the pc in the exception stack frame points to the instruction after stop, and the sr re?cts the just-loaded value. because coldfire processors do not support hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. as an example, consider a trap instruction executing in trace mode. the processor initiates the trap exception and passes control to the corresponding handler. if the system requires that a trace exception be processed, the trap exception handler must check for this condition (sr[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception. debug interrupt caused by a hardware breakpoint register trigger. rather than generating an iack cycle, the processor internally calculates the vector number (12). additionally, the m bit and the interrupt priority mask ?lds of the sr are unaffected by the interrupt. see section 2.2.2.1, ?tatus register (sr). rte and format error exceptions when an rte instruction executes, the processor ?st examines the 4-bit format ?ld to validate the frame type. for a coldfire processor, any attempted execution of an rte where the format is not equal to {4,5,6,7} generates a format error. the exception stack frame for the format error is created without disturbing the original exception frame and the stacked pc points to rte.the selection of the format value provides limited debug support for porting code from m68000 applications. on m68000 family processors, the sr was at the top of the stack. bit 30 of the longword addressed by the system stack pointer is typically zero; so, attempting an rte using this old format generates a format error on a coldfire processor. if the format ?ld de?es a valid type, the processor does the following: 1 reloads the sr operand. 2 fetches the second longword operand. 3 adjusts the stack pointer by adding the format value to the auto-incremented address after the ?st longword fetch. 4 transfers control to the instruction address de?ed by the second longword operand in the stack frame. trap executing trap always forces an exception and is useful for implementing system calls. the trap instruction may be used to change from user to supervisor mode. interrupt exception interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. autovectoring may optionally be con?ured through the system interface module (sim). see section 9.2.2, ?utovector register (avr). table 2-21. mcf5307 exceptions (continued) exception description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-52 mcf5307 users manual exception processing overview if a coldfire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. a reset is required to force the processor to exit this halted state. reset exception asserting the reset input signal (rsti ) causes a reset exception. reset has the highest exception priority; it provides for system initialization and recovery from catastrophic failure. when assertion of rsti is recognized, current processing is aborted and cannot be recovered. the reset exception places the processor in supervisor mode by setting sr[s] and disables tracing by clearing sr[t]. this exception also clears sr[m] and sets the processors interrupt priority mask in the sr to the highest level (level 7). next, the vbr is initialized to 0x0000_0000. con?uration registers controlling the operation of all processor-local memories (cache and ram modules on the mcf5307) are invalidated, disabling the memories. note: other implementation-speci? supervisor registers are also affected. refer to each of the modules in this manual for details on these registers. after rsti is negated, the processor waits 80 cycles before beginning the actual reset exception process. during this time, certain events are sampled, including the assertion of the debug breakpoint signal. if the processor is not halted, it initiates the reset exception by performing two longword read bus cycles. the longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the pc. after the initial instruction is fetched from memory, program execution begins at the address in the pc. if an access error or address error occurs before the ?st instruction executes, the processor enters the fault-on-fault halted state. unsupported instruction exception if the mcf5307 attempts to execute a valid instruction but the required optional hardware module is not present in the oep, a non-supported instruction exception is generated (vector 0x61). control is then passed to an exception handler that can then process the opcode as required by the system. table 2-21. mcf5307 exceptions (continued) exception description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. hardware multiply/accumulate (mac) unit 3-1 chapter 3 hardware multiply/accumulate (mac) unit this chapter describes the mcf5307 multiply/accumulate (mac) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. the mac is integrated into the operand execution pipeline (oep). 3.1 overview the mac unit provides hardware support for a limited set of digital signal processing (dsp) operations used in embedded code, while supporting the integer multiply instructions in the coldfire microprocessor family. the mac unit provides signal processing capabilities for the mcf5307 in a variety of applications including digital audio and servo control. integrated as an execution unit in the processor?s oep, the mac unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed, xed-point fractional input operands. the mac unit provides functionality in three related areas: signed and unsigned integer multiplies multiply-accumulate operations supporting signed, unsigned, and signed fractional operands miscellaneous register operations each of the three areas of support is addressed in detail in the succeeding sections. logic that supports this functionality is contained in a mac module, as shown in figure 3-1. the mac unit is tightly coupled to the oep and features a three-stage execution pipeline. to minimize silicon costs, the coldfire mac is optimized for 16 x 16 multiply instructions. the oep can issue a 16 x 16 multiply with a 32-bit accumulation and fetch a 32-bit operand in the same cycle. a 32 x 32 multiply with a 32-bit accumulation takes three cycles before the next instruction can be issued. figure 3-1 shows the basic functionality of the coldfire mac. a full set of instructions is provided for signed and unsigned integers plus signed, xed-point, fractional input operands. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-2 mcf5307 users manual overview figure 3-1. coldfire mac multiplication and accumulation the mac unit is an extension of the basic multiplier found on most microprocessors. it can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints. for example, small digital lters can tolerate some variance in the execution time of the algorithm; larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements exceeding the scope of any processor architecture and requiring a fully developed dsp implementation. the m68000 architecture was not designed for high-speed signal processing, and a large dsp engine would be excessive in an embedded environment. in striking a middle ground between speed, size, and functionality, the coldfire mac unit is optimized for a small set of operations that involve multiplication and cumulative additions. speci cally, the multiplier array is optimized for single-cycle, 16 x 16 multiplies producing a 32-bit result, with a possible accumulation cycle following. this is common in a large portion of signal processing applications. in addition, the coldfire core architecture has been modi ed to allow for an operand fetch in parallel with a multiply, increasing overall performance for certain dsp operations. 3.1.1 mac programming model figure 3-2 shows the registers in the mac portion of the user programming model. figure 3-2. mac programming model 31 0 macsr mac status register acc mac accumulator mask mac mask register x +/- operand y operand x shift 0,1,-1 accumulator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. hardware multiply/accumulate (mac) unit 3-3 overview these registers are described as follows: accumulator (acc)?this 32-bit, read/write, general-purpose register is used to accumulate the results of mac operations. mask register (mask)?this 16-bit general-purpose register provides an optional address mask for mac instructions that fetch operands from memory. it is useful in the implementation of circular queues in operand memory. mac status register (macsr)?this 8-bit register de nes con guration of the mac unit and contains indicator ags affected by mac instructions. unless noted otherwise, the setting of macsr indicator ags is based on the nal result, that is, the result of the nal operation involving the product and accumulator. 3.1.2 general operation the mac unit supports the coldfire integer multiply instructions (muls and mulu) and provides additional functionality for multiply-accumulate operations. the added mac instructions to the coldfire isa provide for the multiplication of two numbers, followed by the addition or subtraction of this number to or from the value contained in the accumulator. the product may be optionally shifted left or right one bit before the addition or subtraction takes place. hardware support for saturation arithmetic may be enabled to minimize software overhead when dealing with potential over ow conditions using signed or unsigned operands. these mac operations treat the operands as one of the following formats: signed integers unsigned integers signed, xed-point, fractional numbers to maintain compactness, the mac module is optimized for 16-bit multiplications. two 16-bit operands produce a 32-bit product. longword operations are performed by reusing the 16-bit multiplier array at the expense of a small amount of extra control logic. again, the product of two 32-bit operands is a 32-bit result. for longword integer operations, only the least signi cant 32 bits of the product are calculated. for fractional operations, the entire 63-bit product is calculated and then either truncated or rounded to a 32-bit result using the round-to-nearest (even) method. because the multiplier array is implemented in a 3-stage pipeline, mac instructions can have an effective issue rate of one clock for word operations, three for longword integer operations, and four for 32-bit fractional operations. arithmetic operations use register-based input operands, and summed values are stored internally in the accumulator. thus, an additional move instruction is necessary to store data in a general-purpose register. mac instructions can choose the upper or lower word of a register as the input, which helps ltering operations in which one data register is loaded with input data and another is loaded with coef cient data. two 16-bit mac operations can be performed without fetching additional operands between instructions by alternating the word choice f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-4 mcf5307 users manual overview during the calculations. the need to move large amounts of data quickly can limit throughput in dsp engines. however, data can be moved ef ciently by using the movem instruction, which automatically generates line-sized burst references and is ideal for lling registers quickly with input data, lter coef cients, and output data. loading an operand from memory into a register during a mac operation makes some dsp operations, especially ltering and convolution, more manageable. the macsr has a 4-bit operational mode eld and three condition ags. the operational mode bits control the over ow/saturation mode, whether operands are signed or unsigned, whether operands are treated as integers or fractions, and how rounding is performed. negative, zero and over ow ags are also provided. the three program-visible mac registers, a 32-bit accumulator (acc), the mac mask register (mask), and macsr, are described in section 3.1.1, ?mac programming model.? 3.1.3 mac instruction set summary the mac unit supports the integer multiply operations de ned by the baseline coldfire architecture, as well as the new multiply-accumulate instructions. table 3-1 summarizes the mac unit instruction set. 3.1.4 data representation the mac unit supports three basic operand types: table 3-1. mac instruction summary instruction mnemonic description multiply signed muls y,dx multiplies two signed operands yielding a signed result multiply unsigned mulu y,dx multiplies two unsigned operands yielding an unsigned result multiply accumulate mac ry,rxsf msac ry,rxsf multiplies two operands, then adds or subtracts the product to/from the accumulator multiply accumulate with load mac ry,rxsf,rw msac ry,rxsf,rw multiplies two operands, then adds or subtracts the product to/from the accumulator while loading a register with the memory operand load accumulator mov.l {ry,#imm},acc loads the accumulator with a 32-bit operand store accumulator mov.l acc,rx writes the contents of the accumulator to a register load macsr mov.l {ry,#imm},macsr writes a value to the macsr store macsr mov.l macsr,rx write the contents of macsr to a register store macsr to ccr mov.l macsr,ccr write the contents of macsr to the processors ccr register load mask mov.l {ry,#imm},mask writes a value to mask store mask mov.l mask,rx writes the contents of mask to a register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. hardware multiply/accumulate (mac) unit 3-5 mac instruction execution timings two?s complement signed integer: in this format, an n-bit operand represents a number within the range -2 (n-1) < operand < 2 (n-1) - 1. the binary point is to the right of the least signi cant bit. two?s complement unsigned integer: in this format, an n-bit operand represents a number within the range 0 < operand < 2 n - 1. the binary point is to the right of the least signi cant bit. two?s complement, signed fractional: in an n-bit number, the rst bit is the sign bit. the remaining bits signify the rst n-1 bits after the binary point. given an n-bit number, a n-1 a n-2 a n-3 ... a 2 a 1 a 0 , its value is given by the following formula: this format can represent numbers in the range -1 < operand < 1 - 2 (n-1) . for words and longwords, the greatest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x0x8000_0000, respectively. the most positive word is 0x7fff or (1 - 2 -15 ); the most positive longword is 0x7fff_ffff or (1 - 2 -31 ). 3.2 mac instruction execution timings table 3-2 shows standard timings for two-operand mac instructions. table 3-2. two-operand mac instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # mac.w ry,rx 1(0/0) mac.l ry,rx 3(0/0) msac.w ry,rx 1(0/0) msac.l ry,rx 3(0/0) mac.w ry,rx,ea,rw 1(1/0) 1(1/0) 1(1/0) 1(1/0) mac.l ry,rx,ea,rw 3(1/0) 3(1/0) 3(1/0) 3(1/0) msac.w ry,rx,ea,rw 1(1/0) 1(1/0) 1(1/0) 1(1/0) msac.l ry,rx,ea,rw 3(1/0) 3(1/0) 3(1/0) 3(1/0) muls.w ,dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0) mulu.w ,dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0) muls.l ,dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) mulu.l ,dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) 2 i1n ? + () ai ? i0 = n2 ? + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-6 mcf5307 users manual mac instruction execution timings table 3-3 shows standard timings for mac move instructions. table 3-3. mac move instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xi*sf) (xxx).wl # move.l ,acc 1(0/0) 1(0/0) move.l ,macsr 6(0/0) 6(0/0) move.l ,mask 5(0/0) 5(0/0) move.l acc,rx 1(0/0) move.l macsr,ccr 1(0/0) move.l macsr,rx 1(0/0) move.l mask,rx 1(0/0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-1 chapter 4 local memory this chapter describes the mcf5307 implementation of the coldfire version 3 local memory speci cation. it consists of two major sections. section 4.2, ?sram overview,? describes the mcf5307 on-chip static ram (sram) implementation. it covers general operations, con guration, and initialization. it also provides information and examples showing how to minimize power consumption when using the sram. section 4.7, ?cache overview,? describes the mcf5307 cache implementation, including organization, con guration, and coherency. it describes cache operations and how the cache interfaces with other memory structures. 4.1 interactions between local memory modules depending on con guration information, instruction fetches and data read accesses may be sent simultaneously to the ram and cache controllers. this approach is required because both controllers are memory-mapped devices and the hit/miss determination is made concurrently with the read data access. power dissipation can be minimized by con guring the rambars to mask unused address spaces whenever possible. if the access address is mapped into the region de ned by the ram (and this region is not masked), the ram provides the data back to the processor, and the cache data is discarded. accesses from the ram module are never cached. the complete de nition of the processor?s local bus priority scheme for read references is as follows: if (ram ?hits? ) ram supplies data to the processor else if (cache ?hits?) cache supplies data to the processor else system memory reference to access data for data write references, the memory mapping into the local memories is resolved before the appropriate destination memory is accessed. accordingly, only the targeted local memory is accessed for data write transfers. 4.2 sram overview the 4-kbyte on-chip sram module is connected to the internal b us and pr o vides pipelined, single-cycle access to memory mapped to the module. memory can be mapped to any f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-2 mcf5307 users manual sram operation 0-modulo-32k location in the 4-gbyte address space and con gured to respond to either instruction or data accesses.time-critical functions can be mapped into instruction the system stack. other heavily-referenced data can be mapped into memory. the following summarizes features of the mcf5307 sram implementation: 4-kbyte sram, organized as 1024 x 32 bits single-cycle throughput. when the pipeline is full, one access can occur per clock cycle. physical location on the processor?s high-speed local bus memory location programmable on any 0-modulo-32k address boundary byte, word, and longword address capabilities the ram base address register (rambar) de nes the logical base address, attributes, and access types for the sram module. 4.3 sram operation the sram module provides a general-purpose memory block that the coldfire processor can access with single-cycle throughput. the location of the memory block can be speci ed to any word-aligned address in the 4-gbyte address space by rambar[ba], described in section 4.4.1, ?sram base address register (rambar).? the memory is ideal for storing critical code or data structures or for use as the system stack. because the sram module connects physically to the processor?s high-speed local bus, it can service processor-initiated accesses or memory-referencing debug module commands. instruction fetches and data reads can be sent to both the cache and sram blocks simultaneously. if the reference is mapped into a region de ned by the sram, the sram provides data to the processor and any cache data is discarded. data accessed from the sram module are not cached. note also that the sram cannot be accessed by the on-chip dmas. the on-chip system con guration allows concurrent core and dma execution, where the core can reference code or data from the internal sram or cache while performing a dma transfer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-3 sram programming model accesses are attempted in the following order: 1. sram 2. cache (if space is de ned as cacheable) 3. external access 4.4 sram programming model the sram programming model consists of rambar. 4.4.1 sram base address register (rambar) the sram modules are con gured through the rambar, shown in figure 4-1. rambar holds the base address of the sram. the movec instruction provides write-only access to this register from the processor. rambar can be read or written from the debug module in a similar manner. all unde ned rambar bits are reserved. these bits are ignored during writes to the rambar and return zeros when read from the debug module. the valid bit, rambar[v], is cleared at reset, disabling the sram module. all other bits are unaffected. figure 4-1. sram base address register (rambar) rambar elds are described in detail in table 4-1. 31 15 14 9 8 7 6 5 4 3 2 1 0 field ba wp c/i sc sd uc ud v reset 0 r/w w for cpu; r/w for debug address cpu space + 0xc04 table 4-1. rambar field description bits name description 31?5 ba base address. de?es the sram modules word-aligned base address. the sram module occupies a 4-kbyte space de?ed by the contents of ba. sram may reside on any 32-kbyte boundary in the 4-gbyte address space. 14? reserved, should be cleared. 8 wp write protect. controls read/write properties of the sram. 0 allows read and write accesses to the sram module 1 allows only read accesses to the sram module. any attempted write reference generates an access error exception to the coldfire processor core. 7? reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-4 mcf5307 users manual sram initialization the mapping of a given access into the ram uses the following algorithm to determine if the access hits in the memory: if (rambar[0] = 1) if (requested address[31:15] = rambar[31:15]) if (requested address[14:12] = 0) if (asn of the requested type = 0) access is mapped to the ram module if (access = read) read the ram and return the data if (access = write) if (rambar[8] = 0) write the data into the ram else signal a write-protect access error as n refers to the ve address space mask bits: c/i, sc, sd, uc, and ud. 4.5 sram initialization after a hardware reset, the contents of the sram module are unde ned. the valid bit, rambar[v], is cleared, disabling the sram module. if the sram requires initialization with instructions or data, the following steps should be performed: 1. read the source data and write it to the sram. various instructions support this function, including memory-to-memory move instructions and the move multiple instruction (movem). movem is optimized to generate line-sized burst fetches on line-aligned addresses, so it generally provides maximum performance. 2. after the data is loaded into the sram, it may be appropriate to revise the rambar attribute bits, including the write-protect and address space mask elds. remember that the sram cannot be accessed by the on-chip dmas. the on-chip system con guration allows concurrent core and dma execution where the core can execute code 5? c/i, sc, sd, uc, ud address space masks (as n ). these ?lds allow certain types of accesses to be masked, or inhibited from accessing the sram module. these bits are useful for power management as described in section 4.6, ?ower management. in particular, c/i is typically set. the address space mask bits are follows: c/i = cpu space/interrupt acknowledge cycle mask. note that c/i must be set if ba = 0. sc = supervisor code address space mask sd = supervisor data address space mask uc = user code address space mask ud = user data address space mask for each as n bit: 0 an access to the sram module can occur for this address space 1 disable this address space from the sram module. if a reference using this address space is made, it is inhibited from accessing the sram module and is processed like any other non-sram reference. 0 v valid. enables/disables the sram module. v is cleared at reset. 0 rambar contents are not valid. 1 rambar contents are valid. table 4-1. rambar field description (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-5 sram initialization out of internal sram or cache during dma access. the coldfire processor or an external emulator using the debug module can perform these initialization functions. 4.5.1 sram initialization code the code segment below initializes the sram. the code sets the base address of the sram at 0x2000_0000 and then initializes the ram to zeros. rambase equ 0x20000000 ;set this variable to 0x20000000 ramvalid equ 0x00000035 move.l #rambase+ramvalid,d0 ;load rambase + valid bit into d0 movec.l d0, rambar ;load rambar and enable sram the following loop initializes the entire sram to zero: lea.l rambase,a0 ;load pointer to sram move.l #1024,d0 ;load loop counter into d0 sram_init_loop: clr.l (a0)+ ;clear 4 bytes of sram subq.l #1,d0 ;decrement loop counter bne.b sram_init_loop ;exit if done; else continue looping the following function copies the number of bytestomove from the source (*src) to the processor?s local ram at an offset relative to the sram base address de ned by destinationoffset. the bytestomove must be a multiple of 16. for best performance, source and destination sram addresses should be line-aligned (0-modulo-16). ; copytocpuram (*src, destinationoffset, bytestomove) rambase equ 0x20000000 ;sram base address ramflags equ 0x00000035 ;rambar valid + mask bits lea.l -12(a7),a7 ;allocate temporary space movem.l #0x1c,(a7) ;store d2/d3/d4 registers ; stack arguments and locations ; +0 saved d2 ; +4 saved d3 ; +8 saved d4 ; +12 returnpc ; +16 pointer to source operand ; +20 destinationoffset ; +24 bytestomove move.l rambase+ramflags,a0 ;define rambar contents movec.l a0,rambar ;load it move.l 16(a7),a0 ;load argument defining *src lea.l rambase,a1 ;memory pointer to ram base add.l 20(a7),a1 ;include destinationoffset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-6 mcf5307 users manual power management move.l 24(a7),d4 ;load byte count asr.l #4,d4 ;divide by 16 to convert to loop count .align 4 ;force loop on 0-mod-4 address loop: movem.l (a0),#0xf ;read 16 bytes from source movem.l #0xf,(a1) ;store into ram destination lea.l 16(a0),a0 ;increment source pointer lea.l 16(a1),a1 ;increment destination pointer subq.l #1,d4 ;decrement loop counter bne.b loop ;if done, then exit, else continue movem.l (a7),#0x1c ;restore d2/d3/d4 registers lea.l 12(a7),a7 ;deallocate temporary space rts 4.6 power management because processor memory references may be simultaneously sent to an sram module and cache, power can be minimized by con guring rambar address space masks as precisely as possible. for example, if an sram is mapped to the internal instruction bus and contains instruction data, setting the as n mask bits associated with operand references can decrease power dissipation. similarly, if the sram contains data, setting as n bits associated with instruction fetches minimizes power. table 4-2 shows typical rambar con gurations. . 4.7 cache overview this section describes the mcf5307 cache implementation, including organization, con guration, and coherency. it describes cache operations and how the cache interacts with other memory structures. the mcf5307 processor contains a nonblocking, 8-kbyte, 4-way set-associative, uni ed (instruction and data) cache with a 16-byte line size. the cache improves system performance by providing low-latency access to the instruction and data pipelines. this decouples processor performance from system memory performance, increasing bus availability for on-chip dma or external devices. figure 4-2 shows the organization and integration of the data cache. table 4-2. examples of typical rambar settings data contained in sram rambar[5?] code only 0x2b data only 0x35 both code and data 0x21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-7 cache organization figure 4-2. unified cache organization the cache supports operation of copyback, write-through, or cache-inhibited modes. the cache lock feature can be used to guarantee deterministic response for critical code or data areas. a nonblocking cache services read hits or write hits from the processor while a ll (caused by a cache allocation) is in progress. as figure 4-2 shows, instruction and data accesses use a single bus connected to the cache. all addresses from the processor to the cache are physical addresses. a cache hit occurs when an address matches a cache entry. for a read, the cache supplies data to the processor. for a write, the processor updates the cache. if an access does not match a cache entry (misses the cache) or if a write access must be written through to memory, the cache performs a bus cycle on the internal bus and correspondingly on the external bus by way of the system integration module (sim). the sram module does not implement bus snooping; cache coherency with other possible bus masters must be maintained in software. 4.8 cache organization a four-way set associative cache is organized as four ways (levels). there are 128 sets in the 8-kbyte cache with each line containing 16 bytes (4 longwords). entire cache lines are loaded from memory by burst-mode accesses that cache 4 longwords of data or instructions. all 4 longwords must be loaded for the cache line to be valid. figure 4-3 shows cache organization as well as terminology used. system address/ control cache control logic directory array data array data path coldfire address path control data address external bus data control data address integration module (sim) processor core f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-8 mcf5307 users manual cache organization figure 4-3. cache organization and line format a set is a group of four lines (one from each level, or way), corresponding to the same index into the cache array. 4.8.1 cache line states: invalid, valid-unmodi?d, and valid-modi?d as shown in table 4-3, a cache line can be invalid, valid-unmodi ed (often called exclusive), or valid-modi ed. a valid line can be explicitly invalidated by executing a cpushl instruction . table 4-3. valid and modified bit settings v m description 0 x invalid. invalid lines are ignored during lookups. 1 0 valid, unmodi?d. cache line has valid data that matches system memory. 1 1 valid, modi?d. cache line contains most recent data, data at system memory location is stale. way 0 way 1 way 2 way 3 line set 0 set 1 set 126 set 127 tag v m longword 0 longword 1 longword 2 longword 3 where: tag?1-bit address tag v?alid bit for line m?odified bit for line cache line format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-9 cache organization 4.8.2 the cache at start-up as figure 4-4 (a) shows, after power-up, cache contents are unde ned; v and m may be set on some lines even though the cache may not contain the appropriate data for start up. because reset and power-up do not invalidate cache lines automatically, the cache should be cleared explicitly by setting cacr[cinva] before the cache is enabled (b). after the entire cache is ushed, cacheable entries are loaded rst in way 0. if way 0 is occupied, the cacheable entry is loaded into the same set in way 1, as shown in figure 4-4 (d). this process is described in detail in section 4.9, ?cache operation.? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-10 mcf5307 users manual cache organization figure 4-4. cache?: at reset, b: after invalidation, c and d: loading pattern a:cache population at start-up b:cache after invalidation, before it is enabled c:cache after loads in way 0 d:first load in way 1 way 0 way 1 way 2 way 3 way 0 way 1 way 2 way 3 way 0 way 1 way 2 way 3 way 0 way 1 way 2 way 3 invalid (v = 0) valid, not modified (v = 1, m = 0) valid, modified (v = 1, m = 1) at reset, cache contents are indeterminate; v and m may be set. the cache should be cleared explicitly by setting cacr[cinva] before the cache is enabled. setting cacr[cinva] invalidates the entire cache. set 0 set 127 initial cacheable accesses to memory-?l positions in way 0. a line is loaded in way 1 only if that set is full in way 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-11 cache operation 4.9 cache operation figure 4-5 shows the general ow of a caching operation. figure 4-5. caching operation the following steps determine if a cache line is allocated for a given address: 1. the cache set index, a[10:4], selects one cache set. 2. a[31:11] and the cache set index are used as a tag reference or are used to update the cache line tag eld. note that a[31:11] can specify 21 possible addresses that can be mapped to one of the four ways. 3. the four tags from the selected cache set are compared with the tag reference. a cache hit occurs if a tag matches the tag reference and the v bit is set, indicating that the cache line contains valid data. if a cacheable write access hits in a valid cache line, the write can occur to the cache line without having to load it from memory. if the memory space is copyback, the updated cache line is marked modi ed (m = 1), because the new data has made the data in memory out of date. if the memory location is write-through, the write is passed on to system memory and the m bit is never used. note that the tag does not have tt or tm bits. to allocate a cache entry, the cache set index selects one of the cache?s 128 sets. the cache control logic looks for an invalid cache line to use for the new entry. if none is available, the cache controller uses a pseudo-round-robin replacement algorithm to choose the line to 0 3 4 10 11 31 index tag data/tag reference mux comparator 0 1 2 3 logical or hit 3 hit 2 hit 1 hit 0 hit line select set 0 set 1 set 127 address a[31:11] way 0 way 1 way 2 way 3 tag status lw0 lw1 lw2 lw3 tag status lw0 lw1 lw2 lw3 address set select a[10:4] data or instruction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-12 mcf5307 users manual cache operation be deallocated and replaced. first the cache controller looks for an invalid line, with way 0 the highest priority. if all lines have valid data, a 2-bit replacement counter is used to choose the way. after a line is allocated, the pointer increments to point to the next way. cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking. if cacr[hlck] = 1, the replacement pointer is restricted to way 2 or 3. as part of deallocation, a valid, unmodi ed cache line is invalidated. it is consistent with system memory, so memory does not need to be updated. to deallocate a modi ed cache line, data is placed in a push buffer (for an external cache line push) before being invalidated. after invalidation, the new entry can replace it. the old cache line may be written after the new line is read. when a cache line is selected to host a new cache entry, the following three things happen: 1. the new address tag bits a[31:11] are written to the tag. 2. the cache line is updated with the new memory data. 3. the cache line status changes to a valid state (v = 1). read cycles that miss in the cache allocate normally as previously described. write cycles that miss in the cache do not allocate on a cacheable write-through region, but do allocate for addresses in a cacheable copyback region . a copyback byte, word, longword, or line write miss causes the following: 1. the cache initiates a line ll or ush. 2. space is allocated for a new line. 3. v and m are both set to indicate valid and modi ed. 4. data is written in the allocated space. no write to memory occurs. note the following: read hits cannot change the status bits and no deallocation or replacement occurs; the data or instructions are read from the cache. if the cache hits on a write access, data is written to the appropriate portion of the accessed cache line. write hits in cacheable, write-through regions generate an external write cycle and the cache line is marked valid, but is never marked modi ed. write hits in cacheable copyback regions do not perform an external write cycle; the cache line is marked valid and modi ed (v = 1 and m = 1). misaligned accesses are broken into at least two cache accesses. validity is provided only on a line basis. unless a whole line is loaded on a cache miss, the cache controller does not validate data in the cache line. write accesses designated as cache-inhibited by the cacr or acr bypass the cache and perform a corresponding external write. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-13 cache operation normally, cache-inhibited reads bypass the cache and are performed on the external bus. the exception to this normal operation occurs when all of the following conditions are true during a cache-inhibited read: the cache-inhibited ll buffer bit, cacr[dnfb], is set. the access is an instruction read. the access is normal (that is, transfer type (tt) equals 0). in this case, an entire line is fetched and stored in the ll buffer. it remains valid there, and the cache can service additional read accesses from this buffer until either another ll or a cache-invalidate-all operation occurs. valid cache entries that match during cache-inhibited address accesses are neither pushed nor invalidated. such a scenario suggests that the associated cache mode for this address space was changed. to avoid this, it is generally recommended to use the cpushl instruction to push or invalidate the cache entry or set cacr[cinva] to invalidate the cache before switching cache modes. 4.9.1 caching modes for every memory reference generated by the processor or debug module, a set of effective attributes is determined based on the address and the acrs. caching modes determine how the cache handles an access. an access can be cacheable in either write-through or copyback mode; it can be cache-inhibited in precise or imprecise modes. for normal accesses, the acr n [cm] bit corresponding to the address of the access speci es the caching modes. if an address does not match an acr, the default caching mode is de ned by cacr[dcm]. the speci c algorithm is as follows: if (address == acr0-address including mask) effective attributes = acr0 attributes else if (address == acr1-address including mask) effective attributes = acr1 attributes else effective attributes = cacr default attributes addresses matching an acr can also be write-protected using acr[w]. addresses that do not match either acr can be write-protected using cacr[dw]. reset disables the cache and clears all cacr bits. as shown in figure 4-4, reset does not automatically invalidate cache entries; they must be invalidated through software. the acrs allow the defaults selected in the cacr to be overridden. in addition, some instructions (for example, cpushl) and processor core operations perform accesses that have an implicit caching mode associated with them. the following sections discuss the different caching accesses and their associated cache modes. 4.9.1.1 cacheable accesses if acr n [cm] or the default eld of the cacr indicates write-through or copyback, the access is cacheable. a read access to a write-through or copyback region is read from the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-14 mcf5307 users manual cache operation cache if matching data is found. otherwise, the data is read from memory and the cache is updated. when a line is being read from memory for either a write-through or copyback read miss, the longword within the line that contains the core-requested data is loaded rst and the requested data is given immediately to the processor, without waiting for the three remaining longwords to reach the cache. the following sections describe write-through and copyback modes in detail. 4.9.1.2 write-through mode write accesses to regions speci ed as write-through are always passed on to the external bus, although the cycle can be buffered, depending on the state of cacr[esb]. writes in write-through mode are handled with a no-write-allocate policy?that is, writes that miss in the cache are written to the external bus but do not cause the corresponding line in memory to be loaded into the cache. write accesses that hit always write through to memory and update matching cache lines. the cache supplies data to data-read accesses that hit in the cache; read misses cause a new cache line to be loaded into the cache. 4.9.1.3 copyback mode copyback regions are typically used for local data structures or stacks to minimize external bus use and reduce write-access latency. write accesses to regions speci ed as copyback that hit in the cache update the cache line and set the corresponding m bit without an external bus access. be sure to ush the cache using the cpushl instruction before invalidating the cache in copyback mode. modi ed cache data is written to memory only if the line is replaced because of a miss or a cpushl instruction pushes the line. if a byte, word, longword, or line write access misses in the cache, the required cache line is read from memory, thereby updating the cache. when a miss selects a modi ed cache line for replacement, the modi ed cache data moves to the push buffer. the replacement line is read into the cache and the push buffer contents are then written to memory. 4.9.2 cache-inhibited accesses memory regions can be designated as cache-inhibited, which is useful for memory containing targets such as i/o devices and shared data structures in multiprocessing systems. it is also important to not cache the mcf5307 memory mapped registers. if the corresponding acr n [cm] or cacr[dcm] indicates cache-inhibited, precise or imprecise, the access is cache-inhibited. the caching operation is identical for both cache-inhibited modes, which differ only regarding recovery from an external bus error. in determining whether a memory location is cacheable or cache-inhibited, the cpu checks memory-control registers in the following order: 1. rambar 2. acr0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-15 cache operation 3. acr1 4. if an access does not hit in the rambar or the acrs, the default is provided for all accesses in cacr. cache-inhibited write accesses bypass the cache and a corresponding external write is performed. cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the following conditions are true: the cache-inhibited ll-buffer bit, cacr[dnfb], is set. the access is an instruction read. the access is normal (that is, tt = 0). in this case, a fetched line is stored in the ll buffer and remains valid there; the cache can service additional read accesses from this buffer until another ll occurs or a cache-invalidate-all operation occurs. if acr n [cm] indicates cache-inhibited mode, precise or imprecise, the controller bypasses the cache and performs an external transfer. if a line in the cache matches the address and the mode is cache-inhibited, the cache does not automatically push the line if it is modi ed, nor does it invalidate the line if it is valid. before switching cache mode, execute a cpushl instruction or set cacr[cinva] to invalidate the entire cache. if acr n [cm] indicates precise mode, the sequence of read and write accesses to the region is guaranteed to match the instruction sequence. in imprecise mode, the processor core allows read accesses that hit in the cache to occur before completion of a pending write from a previous instruction. writes are not deferred past data-read accesses that miss the cache (that is, that must be read from the bus). precise operation forces data-read accesses for an instruction to occur only once by preventing the instruction from being interrupted after data is fetched. otherwise, if the processor is not in precise mode, an exception aborts the instruction and the data may be accessed again when the instruction is restarted. these guarantees apply only when acr n [cm] indicates precise mode and aligned accesses. cpu space-register accesses, such as movec, are treated as cache-inhibited and precise. 4.9.3 cache protocol the following sections describe the cache protocol for processor accesses and assumes that the data is cacheable (that is, write-through or copyback). 4.9.3.1 read miss a processor read that misses in the cache requests the cache controller to generate a bus transaction. this bus transaction reads the needed line from memory and supplies the required data to the processor core. the line is placed in the cache in the valid state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-16 mcf5307 users manual cache operation 4.9.3.2 write miss the cache controller handles processor writes that miss in the cache differently for write-through and copyback regions. write misses to copyback regions cause the cache line to be read from system memory, as shown in figure 4-6. figure 4-6. write-miss in copyback mode the new cache line is then updated with write data and the m bit is set for the line, leaving it in modi ed state. write misses to write-through regions write directly to memory without loading the corresponding cache line into the cache. 4.9.3.3 read hit on a read hit, the cache provides the data to the processor core and the cache line state remains unchanged. if the cache mode changes for a speci c region of address space, lines in the cache corresponding to that region that contain modi ed data are not pushed out to memory when a read hit occurs within that line. first execute a cpushl instruction or set cacr[cinva] before switching the cache mode. 4.9.3.4 write hit the cache controller handles processor writes that hit in the cache differently for write-through and copyback regions. for write hits to a write-through region, portions of cache lines corresponding to the size of the access are updated with the data. the data is cache line system v = 1 m = 0 1 . writing character x to 0x0b generates a write miss. data cannot be written to an invalid line. memory v = 0 m = 0 0x0c 0x00 0x08 0x04 2. the cache line (characters a?) is updated from system memory, and line is marked valid. x abcd efgh ijkl mnop 3. after the cache line is filled, the write that initiated the write miss (the character x) completes to 0x0b. v = 1 m = 1 0x0c 0x00 0x08 0x04 0x0c 0x00 0x08 0x04 abcd exgh ijkl mnop mcf5307 mcf5307 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-17 cache operation also written to external memory. the cache line state is unchanged. for copyback accesses, the cache controller updates the cache line and sets the m bit for the line. an external write is not performed and the cache line state changes to (or remains in) the modi ed state. 4.9.4 cache coherency the mcf5307 provides limited cache coherency support in multiple-master environments. both write-through and copyback memory update techniques are supported to maintain coherency between the cache and memory. the cache does not support snooping (that is, cache coherency is not supported while external or dma masters are using the bus). therefore, on-chip dmas of the mcf5307 cannot access local memory and do not maintain coherency with the uni ed cache. 4.9.5 memory accesses for cache maintenance the cache controller performs all maintenance activities that supply data from the cache to the core, including requests to the sim for reading new cache lines and writing modi ed lines to memory. the following sections describe memory accesses resulting from cache ll and push operations. chapter 18, ?bus operation,? describes required bus cycles in detail. 4.9.5.1 cache filling when a new cache line is required, a line read is requested from the sim, which generates a burst-read transfer by indicating a line access with the size signals, siz[1:0]. the responding device supplies 4 consecutive longwords of data. burst operations can be inhibited or enabled through the burst read/write enable bits (bstr/bstw) in the chip-select control registers (cscr0?cscr7). sim line accesses implicitly request burst-mode operations from memory. for more information regarding external bus burst-mode accesses, see chapter 18, ?bus operation.? the rst cycle of a cache-line read loads the longword entry corresponding to the requested address. subsequent transfers load the remaining longword entries. a burst operation is aborted by an a write-protection fault, which is the only possible access error. exception processing proceeds immediately. because the write cycle can be decoupled from the processor?s issuing of the operation, error signaling appears to be decoupled from the instruction that generated the write. accordingly, the pc in the exception stack frame represents the program location when the access error was signaled. see section 2.8.2, ?processor exceptions.? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-18 mcf5307 users manual cache operation 4.9.5.2 cache pushes cache pushes occur for line replacement and as required for the execution of the cpushl instruction. to reduce the requested data?s latency in the new line, the modi ed line being replaced is temporarily placed in the push buffer while the new line is fetched from memory. after the bus transfer for the new line completes, the modi ed cache line is written back to memory and the push buffer is invalidated. 4.9.5.2.1 push and store buffers the 16-byte push buffer reduces latency for requested new data on a cache miss by holding a displaced modi ed cache line while the new data is read from memory. if a cache miss displaces a modi ed line, a miss read reference is immediately generated. while waiting for the response, the current contents of the cache location load into the push buffer. when the burst-read bus transaction completes, the cache controller can generate the appropriate line-write bus transaction to write the push buffer contents into memory. in imprecise mode, the fifo store buffer can defer pending writes to maximize performance. the store buffer can support as many as four entries (16 bytes maximum) for this purpose. data writes destined for the store buffer cannot stall the core. the store buffer effectively provides a measure of decoupling between the pipeline?s ability to generate writes (one per cycle maximum) and the external bus?s ability to retire those writes. in imprecise mode, writes stall only if the store buffer is full and a write operation is on the internal bus. the internal write cycle is held, stalling the data execution pipeline. if the store buffer is not used (that is, store buffer disabled or cache-inhibited precise mode), external bus cycles are generated directly for each pipeline write operation. the instruction is held in the pipeline until external bus transfer termination is received. therefore, each write is stalled for 5 cycles, making the minimum write time equal to 6 cycles when the store buffer is not used. see section 2.1.2.2, ?operand execution pipeline (oep).? the store buffer enable bit, cacr[esb], controls the enabling of the store buffer. this bit can be set and cleared by the movec instruction. esb is zero at reset and all writes are performed in order (precise mode). acr n [cm] or cacr[dcm] generates the mode used when esb is set. cacheable write-through and cache-inhibited imprecise modes use the store buffer. the store buffer can queue data as much as 4 bytes wide per entry. each entry matches the corresponding bus cycle it generates; therefore, a misaligned longword write to a write-through region creates two entries if the address is to an odd-word boundary. it creates three entries if it is to an odd-byte boundary?one per bus cycle. 4.9.5.2.2 push and store buffer bus operation as soon as the push or store buffer has valid data, the internal bus controller uses the next available external bus cycle to generate the appropriate write cycles. in the event that f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-19 cache operation another cache ll is required (for example, cache miss to process) during the continued instruction execution by the processor pipeline, the pipeline stalls until the push and store buffers are empty, then generate the required external bus transaction. supervisor instructions, the nop instruction, and exception processing synchronize the processor core and guarantee the push and store buffers are empty before proceeding. note that the nop instruction should be used only to synchronize the pipeline. the preferred no-operation function is the tpf instruction. 4.9.6 cache locking ways 0 and 1 of the cache can be locked by setting cacr[hlck]. if the cache is locked, cache lines in ways 0 and 1 are not subject to being deallocated by normal cache operations. as figure 4-7 (b and c) shows, the algorithm for updating the cache and for identifying cache lines to be deallocated is otherwise unchanged. if ways 2 and 3 are entirely invalid, cacheable accesses are rst allocated in way 2. way 3 is not used until the location in way 2 is occupied. ways 0 and 1 are still updated on write hits (d in figure 4-7) and may be pushed or cleared only explicitly by using speci c cache push/invalidate instructions. however, new cache lines cannot be allocated in ways 0 and 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-20 mcf5307 users manual cache operation figure 4-7. cache locking a:ways 0 and 1 are ?led. ways 2 and 3 are invalid. b:cacr[dhlck] is set, locking ways 0 and 1. c:when a set in way 2 is occupied, the set in way 3 is used for a cacheable access. way 0 way 1 way 2 way 3 way 0 way 1 way 2 way 3 way 0 way 1 way 2 way 3 invalid (v = 0) valid, not modified (v = 1, m = 0) valid, modified (v = 1, m = 1) after reset, the cache is invalidated, ways 0 and 1 are then written with data that should not be deallocated. after cacr[hlck] is set, subsequent cache accesses go to ways 2 and 3. s et 0 s et 127 while the cache is locked and after a position in ways is full, the set in way 3 is updated. d:write hits to ways 0 and 1 update cache lines. way 0 way 1 way 2 way 3 while the cache is locked, ways 0 and 1 ca n be updated by write hits. in this example, memor y is con?ured as copyback, so updated cache lines are marked modi?d. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-21 cache registers 4.10 cache registers this section describes the mcf5307 implementation of the version 3 cache registers. 4.10.1 cache control register (cacr) the cacr in figure 4-8 contains bits for con guring the cache. it can be written by the movec register instruction and can be read or written from the debug facility. a hardware reset clears cacr, which disables the cache; however, reset does not affect the tags, state information, or data in the cache. table 4-4 describes cacr elds. 31 30 29 28 27 26 25 24 23 20 19 18 17 16 field ec esb dpi hlck cinva reset 0000_0000_0000_0000 r/w write (r/w by debug module) 15 14 13 12 11 10 9 8 7 0 field dnfb dcm dw reset 0000_0000_0000_0000 r/w write (r/w by debug module) rc 0x002 figure 4-8. cache control register (cacr) table 4-4. cacr field descriptions bits name description 31 ec enable cache. 0 cache disabled. the cache is not operational, but data and tags are preserved. 1 cache enabled. 30 reserved, should be cleared. 29 esb enable store buffer. 0 writes to write-through or noncachable in imprecise mode bypass the store buffer and generate bus cycles directly. section 4.9.5.2.1, ?ush and store buffers, describes the performance penalty for this. 1 the four-entry fifo store buffer is enabled; when imprecise mode is used, this buffer defers pending writes to write-through or cache-inhibited regions to maximize performance. cache-inhibited, precise-mode accesses always bypass the store buffer. 28 dpi disable cpushl invalidation. 0 normal operation. a cpushl instruction causes the selected line to be pushed if modi?d and then invalidated. 1 no clear operation. a cpushl instruction causes the selected line to be pushed if modi?d, then left valid. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-22 mcf5307 users manual cache registers 4.10.2 access control registers (acr0?cr1) the acrs, figure 4-9, assign control attributes, such as cache mode and write protection, to speci ed memory regions. registers are accessed with the movec instruction with the rc encodings in figure 4-9. for overlapping regions, acr0 takes priority. data transfers to and from these registers are longword transfers. bits 12?7, 4, 3, 1, and 0 are always read as zeros. 27 hlck half-cache lock mode 0 normal operation. the cache allocates the lowest invalid way. if all ways are valid, the cache allocates the way pointed at by the counter and then increments this counter modulo-4. 1 half-cache operation. the cache allocates to the lower invalid way of levels 2 and 3; if both are valid, the cache allocates to way 2 if the high-order bit of the round-robin counter is zero; otherwise, it allocates way 3 and increments the round-robin counter modulo-2. this locks the content of ways 0 and 1. ways 0 and 1 are still updated on write hits and may be pushed or cleared by speci? cache push/invalidate instructions. this implementation allows maximum use of available cache memory and provides the ?xibility of setting hlck before, during, or after allocations occur. 26?5 reserved, should be cleared. 24 cinva cache invalidate all. writing a 1 to this bit initiates entire cache invalidation. once invalidation is complete, this bit automatically returns to 0; it is not necessary to clear it explicitly. note the caches are not cleared on power-up or normal reset, as shown in figure 4-4. 0 no invalidation is performed. 1 initiate invalidation of the entire cache. the cache controller sequentially clears v and m bits in all sets. subsequent accesses stall until the invalidation is ?ished, at which point, this bit is automatically cleared. in copyback mode, the cache should be ?shed using a cpushl instruction before setting this bit. 23?1 reserved, should be cleared. 10 dnfb default noncacheable ?l buffer. determines if the ?l buffer can store noncacheable accesses 0 fill buffer not used to store noncacheable instruction accesses (16 or 32 bits). 1 fill buffer used to store noncacheable accesses. the ?l buffer is used only for normal (tt = 0) instruction reads of a noncacheable region. instructions are loaded into the ?l buffer by a burst access (same as a line ?l). they stay in the buffer until they are displaced, so subsequent accesses may not appear on the external bus. note that this feature can cause a coherency problem for self-modifying code. if dnfb = 1 and a cache-inhibited access uses the ?l buffer, instructions remain valid in the ?l buffer until a cache-invalidate-all instruction, another cache-inhibited burst, or a miss that initiates a ?l. a write to the line in the ?l buffer goes to the external bus without updating or invalidating the buffer. subsequent reads of that written data are serviced by the ?l buffer and receive stale information. 9? dcm default cache mode. selects the default cache mode and access precision as follows: 00 cacheable, write-through 01 cacheable, copy-back 10 cache-inhibited, precise exception model 11 cache-inhibited, imprecise exception model. precise and imprecise modes are described in section 4.9.2, ?ache-inhibited accesses. 7? reserved, should be cleared. 5 dw default write protect. use of this bit is described in section 4.9.1, ?aching modes. 0 read and write accesses permitted 1 write accesses not permitted 4? reserved, should be cleared. table 4-4. cacr field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-23 cache registers note: the sim mbar region should be mapped as cache-inhibited through an acr. table 4-5 describes acr n elds. i 31 2423 1615141312 76543 2 10 field address base address mask e s cm w reset uninitialized 0 uninitialized r/w write (r/w by debug module) rc acr0: 0x004; acr1: 0x005 figure 4-9. access control register format (acr n ) table 4-5. acr n field descriptions bits name description 31?4 address base address base. compared with address bits a[31:24]. eligible addresses that match are assigned the access control attributes of this register. 23?6 address mask address mask. setting a mask bit causes the corresponding address base bit to be ignored. the low-order mask bits can be set to de?e contiguous regions larger than 16 mbytes. the mask can de?e multiple noncontiguous regions of memory. 15 e enable. enables or disables the other acr n bits. 0 access control attributes disabled 1 access control attributes enabled 14?3 s supervisor mode. speci?s whether only user or supervisor accesses are allowed in this address range or if the type of access is a don? care. 00 match addresses only in user mode 01 match addresses only in supervisor mode 1x execute cache matching on all accesses 12? reserved; should be cleared. 6? cm cache mode. selects the cache mode and access precision. precise and imprecise modes are described in section 4.9.2, ?ache-inhibited accesses. 00 cacheable, write-through 01 cacheable, copyback 10 cache-inhibited, precise 11 cache-inhibited, imprecise 4? reserved, should be cleared. 2 w write protect. selects the write privilege of the memory region. 0 read and write accesses permitted 1 write accesses not permitted 1? reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-24 mcf5307 users manual cache management 4.11 cache management the cache can be enabled and con gured by using a movec instruction to access cacr. a hardware reset clears cacr, disabling the cache and removing all con guration information; however, reset does not affect the tags, state information, and data in the cache. set cacr[cinva] to invalidate the cache before enabling it. the privileged cpushl instruction supports cache management by selectively pushing and invalidating cache lines. the address register used with cpushl directly addresses the cache?s directory array. the cpushl instruction ushes a cache line. the value of cacr[dpi] determines whether cpushl invalidates a cache line after it is pushed. to push the entire cache, implement a software loop to index through all sets and through each of the four lines within each set (a total of 512 lines). the state of cacr[ec] does not affect the operation of cpushl or cacr[cinva]. disabling the cache by setting cacr[ec] makes the cache nonoperational without affecting tags, state information, or contents. the contents of a n used with cpushl specify cache row and line indexes. this differs from the mc68040 where a physical address is speci ed. figure 4-10 shows the a n format. the following code example ushes the entire cache: _cache_disable: nop move.w #0x2700,sr ;mask off irqs jsr _cache_flush ;flush the cache completely clr.l d0 movec d0,acr0 ;acr0 off movec d0,acr1 ;acr1 off move.l #0x01000000,d0 ;invalidate and disable cache movec d0,cacr rts _cache_flush: nop ;synchronize?flush store buffer moveq.l #0,d0 ;initialize way counter moveq.l #0,d1 ;initialize set counter move.l d0,a0 ;initialize cpushl pointer setloop: cpushl bc,(a0) ;push cache line a0 add.l #0x0010,a0 ;increment set index by 1 addq.l #1,d1 ;increment set counter cmpi.l #128,d1 ;are sets for this way done? bne setloop moveq.l #0,d1 ;set counter to zero again addq.l #1,d0 ;increment to next way 31 11 10 4 3 0 0 set index line index figure 4-10. a n format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-25 cache operation summary move.l d0,a0 ;set = 0, way = d0 cmpi.l #4,d0 ;flushed all the ways? bne setloop rts the following cacr loads assume the default cache mode is copyback. cacheloadandlock: move.l #0xa1000100,d0; enable and invalidate cache ... movec d0,cacr ; ... in the cacr the following code preloads half of the cache (4 kbytes). it assumes a contiguous block of data is to be mapped into the cache, starting at a 0-modulo-4k address. move.l #256,d0 ;256 16-byte lines in 4k space lea data_,a0 ; load pointer defining data area cacheloop: tst.b (a0) ;touch location + load into data cache lea 16(a0),a0 ;increment address to next line subq.l #1,d0 ;decrement loop counter bne.b cacheloop ;if done, then exit, else continue ; a 4k region has been loaded into levels 0 and 1 of the 8k cache. lock it! move.l #0xa8000100,d0 ;set the cache lock bit ... movec d0,cacr ; ... in the cacr rts align 16 4.12 cache operation summary this section gives operational details for the cache and presents cache-line state diagrams. 4.12.1 cache state transitions using the v and m bits, the cache supports a line-based protocol allowing individual cache lines to be invalid, valid, or modi ed. to maintain memory coherency, the cache supports both write-through and copyback modes, speci ed by the corresponding acr[cm], or cacr[dcm] if no acr matches. read or write misses to copyback regions cause the cache controller to read a cache line from memory into the cache. if available, tag and data from memory update an invalid line in the selected set. the line state then changes from invalid to valid by setting the v bit. if all lines in the row are already valid or modi ed, the pseudo-round-robin replacement algorithm selects one of the four lines and replaces the tag and data. before replacement, modi ed lines are temporarily buffered and later copied back to memory after the new line has been read from memory. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-26 mcf5307 users manual cache operation summary figure 4-11 shows the three possible cache line states and possible processor-initiated transitions for memory con gured as copyback. transitions are labeled with a capital letter indicating the previous state and a number indicating the speci c case listed in table 4-11. figure 4-11. cache line state diagram?opyback mode figure 4-12 shows the two possible states for a cache line in write-through mode. figure 4-12. cache line state diagram?rite-through mode table 4-6 describes cache line transitions and the accesses that cause them. invalid cd1?pu ci3?pu valid v = 1 modified read miss write miss ci5?inva ci6?pushl & dpi ci7?pushl & dpi cv1?pu read miss cv2?pu read hit cv7?pushl & dpi cd2?pu read hit cd3?pu write miss cd4?pu write hit cd5?inva cd6?pushl & dpi cv3?pu write miss cv4?pu write hit ci1?pu read miss cv5?inva cv6?pushl & dpi v = 0 m = 0 v = 1 m = 1 cd7?pushl & dpi wi1?pu read miss invalid valid wi3?pu write miss wi5?inva wi6?pushl & dpi wi7?pushl & dpi wv1?pu read miss wv2?pu read hit wv3?pu write miss wv4?pu write hit wv7?pushl & dpi wv5?inva wv6?pushl & dpi v = 0 v = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-27 cache operation summary table 4-6. cache line state transitions access current state invalid (v = 0) valid (v = 1, m = 0) modi?d (v = 1, m = 1) read miss (c,w)i1 read line from memory and update cache; supply data to processor; go to valid state. (c,w)v1 read new line from memory and update cache; supply data to processor; stay in valid state. cd1 push modi?d line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; go to valid state. read hit (c,w)i2 not possible. (c,w)v2 supply data to processor; stay in valid state. cd2 supply data to processor; stay in modi?d state. write miss (copy- back) ci3 read line from memory and update cache; write data to cache; go to modi?d state. cv3 read new line from memory and update cache; write data to cache; go to modi?d state. cd3 push modi?d line to buffer; read new line from memory and update cache; write push buffer contents to memory; stay in modi?d state. write miss (write- through) wi3 write data to memory; stay in invalid state. wv3 write data to memory; stay in valid state. wd3 write data to memory; stay in modi?d state. cache mode changed for the region corresponding to this line. to avoid this state, execute a cpushl instruction or set cacr[cinva] before switching modes. write hit (copy- back) ci4 not possible. cv4 write data to cache; go to modi?d state. cd4 write data to cache; stay in modi?d state. write hit (write- through) wi4 not possible. wv4 write data to memory and to cache; stay in valid state. wd4 write data to memory and to cache; go to valid state. cache mode changed for the region corresponding to this line. to avoid this state, execute a cpushl instruction or set cacr[cinva] before switching modes. cache invalidate (c,w)i5 no action; stay in invalid state. (c,w)v5 no action; go to invalid state. cd5 no action (modi?d data lost); go to invalid state. cache push (c,w)i6 (c,w)i7 no action; stay in invalid state. (c,w)v6 no action; go to invalid state. cd6 push modi?d line to memory; go to invalid state. (c,w)v7 no action; stay in valid state. cd7 push modi?d line to memory; go to valid state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-28 mcf5307 users manual cache operation summary the following tables present the same information as table 4-6, organized by the current state of the cache line. in table 4-7 the current state is invalid. in table 4-8 the current state is valid. table 4-7. cache line state transitions (current state invalid) access response read miss (c,w)i1 read line from memory and update cache; supply data to processor; go to valid state. read hit (c,w)i2 not possible write miss (copyback) ci3 read line from memory and update cache; write data to cache; go to modi?d state. write miss (write-through) wi3 write data to memory; stay in invalid state. write hit (copyback) ci4 not possible write hit (write-through) wi4 not possible cache invalidate (c,w)i5 no action; stay in invalid state. cache push (c,w)i6 no action; stay in invalid state. cache push (c,w)i7 no action; stay in invalid state. table 4-8. cache line state transitions (current state valid) access response read miss (c,w)v1 read new line from memory and update cache; supply data to processor; stay in valid state. read hit (c,w)v2 supply data to processor; stay in valid state. write miss (copyback) cv3 read new line from memory and update cache; write data to cache; go to modi?d state. write miss (write-through) wv3 write data to memory; stay in valid state. write hit (copyback) cv4 write data to cache; go to modi?d state. write hit (write-through) wv4 write data to memory and to cache; stay in valid state. cache invalidate (c,w)v5 no action; go to invalid state. cache push (c,w)v6 no action; go to invalid state. cache push (c,w)v7 no action; stay in valid state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. local memory 4-29 cache initialization code in the current state is modi ed. 4.13 cache initialization code the following example sets up the cache for flash or rom space only. move.l#0x81000300,d0 //enable cache, invalidate it, //default mode is cache-inhibited imprecise movecd0, cacr move.l #0xff00c000,d0//cache flash space, enable, //ignore fc2, cacheable, writethrough movecd0,acr0 table 4-9. cache line state transitions (current state modified) access response read miss cd1 push modi?d line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; go to valid state. read hit cd2 supply data to processor; stay in modi?d state. write miss (copyback) cd3 push modi?d line to buffer; read new line from memory and update cache; write push buffer contents to memory; stay in modi?d state. write miss (write-through) wd3 write data to memory; stay in modi?d state. cache mode changed for the region corresponding to this line. to avoid this state, execute a cpushl instruction or set cacr[cinva] before switching modes. write hit (copyback) cd4 write data to cache; stay in modi?d state. write hit (write-through) wd4 write data to memory and to cache; go to valid state. cache mode changed for the region corresponding to this line. to avoid this state, execute a cpushl instruction or set cacr[cinva] before switching modes. cache invalidate cd5 no action (modi?d data lost); go to invalid state. cache push cd6 push modi?d line to memory; go to invalid state. cache push cd7 push modi?d line to memory; go to valid state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-30 mcf5307 users manual cache initialization code f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-1 chapter 5 debug support this chapter describes the revision b enhanced hardware debug support in the mc5307. this revision of the coldfire debug architecture encompasses the earlier revision. 5.1 overview the debug module is shown in figure 5-1. figure 5-1. processor/debug module interface debug support is divided into three areas: real-time trace support?the ability to determine the dynamic execution path through an application is fundamental for debugging. the coldfire solution implements an 8-bit parallel output bus that reports processor execution status and data to an external emulator system. see section 5.3, ?real-time trace support.? background debug mode (bdm)?provides low-level debugging in the coldfire processor complex. in bdm, the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers. the external emulator uses a three-pin, serial, full-duplex channel. see section 5.5, ?background debug mode (bdm),? and section 5.4, ?programming model.? real-time debug support?bdm requires the processor to be halted, which many real-time embedded applications cannot do. debug interrupts let real-time systems execute a unique service routine that can quickly save the contents of key registers and variables and return the system to normal operation. the emulator can access saved data because the hardware supports concurrent operation of the processor and bdm-initiated commands. see section 5.6, ?real-time debug support.? coldfire cpu core debug module high-speed communication port dsclk, dsi, dso control bkpt local bus trace port pst[3:0], ddata[3:0] pstclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-2 mcf5307 users manual signal description the version 2 coldfire core implemented the original debug architecture, now called revision a. based on feedback from customers and third-party developers, enhancements have been added to succeeding generations of coldfire cores. the version 3 core implements revision b of the debug architecture, providing more exibility for con guring the hardware breakpoint trigger registers and removing the restrictions involving concurrent bdm processing while hardware breakpoint registers are active. 5.2 signal description table 5-1 describes debug module signals. all coldfire debug signals are unidirectional and related to a rising edge of the processor core?s clock signal. the standard 26-pin debug connector is shown in section 5.7, ?motorola-recommended bdm pinout.? table 5-1. debug module signals signal description development serial clock (dsclk) internally synchronized input. (the logic level on dsclk is validated if it has the same value on two consecutive rising clkin edges.) clocks the serial communication port to the debug module. maximum frequency is 1/5 the processor clk speed. at the synchronized rising edge of dsclk, the data input on dsi is sampled and dso changes state. development serial input (dsi) internally synchronized input that provides data input for the serial communication port to the debug module. development serial output (dso) provides serial output communication for debug module responses. dso is registered internally. breakpoint (bkpt ) input used to request a manual breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. halt status is re?cted on processor status/debug data signals (pst[3:0]) as the value 0xf. if csr[bkd] is set (disabling normal bkpt functionality), asserting bkpt generates a debug interrupt exception in the processor. processor status clock (pstclk) delayed version of the processor clock. its rising edge appears in the center of valid pst and ddata output. see figure 5-2. pstclk indicates when the development system should sample pst and ddata values. if real-time trace is not used, setting csr[pcd] keeps pstclk, pst and ddata outputs from toggling without disabling triggers. non-quiescent operation can be reenabled by clearing csr[pcd], although the emulator must resynchronize with the pst and ddata outputs. pstclk starts clocking only when the ?st non-zero pst value (0xc, 0xd, or 0xf) occurs during system reset exception processing. table 5-2 describes pst values. chapter 7, ?hase-locked loop (pll), describes pstclk generation. debug data (ddata[3:0]) these output signals display the hardware register breakpoint status as a default, or optionally, captured address and operand values. the capturing of data values is controlled by the setting of the csr. additionally, execution of the wddata instruction by the processor captures operands which are displayed on ddata. these signals are updated each processor cycle. processor status (pst[3:0]) these output signals report the processor status. table 5-2 shows the encoding of these signals. these outputs indicate the current status of the processor pipeline and, as a result, are not related to the current bus transfer. the pst value is updated each processor cycle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-3 real-time trace support figure 5-2 shows pstclk timing with respect to pst and ddata. figure 5-2. pstclk timing 5.3 real-time trace support real-time trace, which de nes the dynamic execution path, is a fundamental debug function. the coldfire solution is to include a parallel output port providing encoded processor status and data to an external development system. this port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (pst), and the other allows operand data to be displayed (debug data , ddata). the processor status may not be related to the current bus transfer. external development systems can use pst outputs with an external image of the program to completely track the dynamic execution path. this tracking is complicated by any change in ow, especially when branch target address calculation is based on the contents of a program-visible register (variant addressing). ddata outputs can be con gured to display the target address of such instructions in sequential nibble increments across multiple processor clock cycles, as described in section 5.3.1, ?begin execution of taken branch (pst = 0x5).? two 32-bit storage elements form a fifo buffer connecting the processor?s high-speed local bus to the external development system through pst[3:0] and ddata[3:0]. the buffer captures branch target addresses and certain data values for eventual display on the ddata port, one nibble at a time starting with the lsb. execution speed is affected only when both storage elements contain valid data to be dumped to the ddata port. the core stalls until one fifo entry is available. table 5-2 shows the encoding of these signals. pstclk pst or d data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-4 mcf5307 users manual real-time trace support 5.3.1 begin execution of taken branch (pst = 0x5) pst is 0x5 when a taken branch is executed. for some opcodes, a branch target address may be displayed on ddata depending on the csr settings. csr also controls the number of address bytes displayed, which is indicated by the pst marker value immediately preceding the ddata nibble that begins the data output. table 5-2. processor status encoding pst[3:0] de?ition hex binary 0x0 0000 continue execution. many instructions execute in one processor cycle. if an instruction requires more clock cycles, subsequent clock cycles are indicated by driving pst outputs with this encoding. 0x1 0001 begin execution of one instruction. for most instructions, this encoding signals the ?st clock cycle of an instructions execution. certain change-of-?w opcodes, plus the pulse and wddata instructions, generate different encodings. 0x2 0010 reserved 0x3 0011 entry into user-mode. signaled after execution of the instruction that caused the coldfire processor to enter user mode. 0x4 0100 begin execution of pulse and wddata instructions. pulse de?es logic analyzer triggers for debug and/or performance analysis. wddata lets the core write any operand (byte, word, or longword) directly to the ddata port, independent of debug module con?uration. when wddata is executed, a value of 0x4 is signaled on the pst port, followed by the appropriate marker, and then the data transfer on the ddata port. transfer length depends on the wddata operand size. 0x5 0101 begin execution of taken branch. for some opcodes, a branch target address may be displayed on ddata depending on the csr settings. csr also controls the number of address bytes displayed, indicated by the pst marker value preceding the ddata nibble that begins the data output. see section 5.3.1, ?egin execution of taken branch (pst = 0x5). 0x6 0110 reserved 0x7 0111 begin execution of return from exception (rte) instruction. 0x8 0xb 1000 1011 indicates the number of bytes to be displayed on the ddata port on subsequent clock cycles. the value is driven onto the pst port one clock pstclk cycle before the data is displayed on ddata. 0x8 begin 1-byte transfer on ddata. 0x9 begin 2-byte transfer on ddata. 0xa begin 3-byte transfer on ddata. 0xb begin 4-byte transfer on ddata. 0xc 1100 exception processing. exceptions that enter emulation mode (debug interrupt or optionally trace) generate a different encoding, as described below. because the 0xc encoding de?es a multiple-cycle mode, pst outputs are driven with 0xc until exception processing completes. 0xd 1101 entry into emulator mode. displayed during emulation mode (debug interrupt or optionally trace). because this encoding de?es a multiple-cycle mode, pstoutputs are driven with 0xd until exception processing completes. 0xe 1110 processor is stopped. appears in multiple-cycle format when the mcf5307 executes a stop instruction. the coldfire processor remains stopped until an interrupt occurs, thus pst outputs display 0xe until the stopped mode is exited . 0xf 1111 processor is halted. because this encoding de?es a multiple-cycle mode, the pst outputs display 0xf until the processor is restarted or reset. (see section 5.5.1, ?pu halt? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-5 programming model bytes are displayed in least-to-most-signi cant order. the processor captures only those target addresses associated with taken branches which use a variant addressing mode, that is, rte and rts instructions, jmp and jsr instructions using address register indirect or indexed addressing modes, and all exception vectors. the simplest example of a branch instruction using a variant address is the compiled code for a c language case statement. typically, the evaluation of this statement uses the variable of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. for such change-of- ow operations, the mcf5307 uses the debug pins to output the following sequence of information on successive processor clock cycles: 1. use pst (0x5) to identify that a taken branch was executed. 2. using the pst pins, optionally signal the target address to be displayed sequentially on the ddata pins. encodings 0x9?0xb identify the number of bytes displayed . 3. the new target address is optionally available on subsequent cycles using the ddata port. the number of bytes of the target address displayed on this port is con gurable (2, 3, or 4 bytes). another example of a variant branch instruction would be a jmp (a0) instruction. figure 5-3 shows when the pst and ddata outputs that indicate when a jmp (a0) executed, assuming the csr was programmed to display the lower 2 bytes of an address. figure 5-3. example jmp instruction output on pst/ddata pst is driven with a 0x5 in the rst cycle and 0x9 in the second. the 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. thus, the 4 subsequent ddata nibbles display the lower 2 bytes of address register a0 in least-to-most-signi cant nibble order. the pst output after the jmp instruction completes depends on the target instruction. the pst can continue with the next instruction before the address has completely displayed on ddata because of the ddata fifo. if the fifo is full and the next instruction has captured values to display on ddata, the pipeline stalls (pst = 0x0) until space is available in the fifo. 5.4 programming model in addition to the existing bdm commands that provide access to the processor?s registers and the memory subsystem, the debug module contains nine registers to support the required functionality. these registers are also accessible from the processor?s supervisor ddata pstclk 0x0 0x0 a[3:0] 0x5 0x9 pst a[7:4] a[11:8] a[15:12] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-6 mcf5307 users manual programming model programming model by executing the wdebug instruction. thus, the breakpoint hardware in the debug module can be accessed by the external development system using the debug serial interface or by the operating system running on the processor core. software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent. hardware provides a locking mechanism in the csr to allow the external development system to disable any attempted writes by the processor to the breakpoint registers (setting csr[ipw]). bdm commands must not be issued if the mcf5307 is using the wdebug instruction to access debug module registers or the resulting behavior is unde ned. these registers, shown in figure 5-4, are treated as 32-bit quantities, regardless of the number of implemented bits. figure 5-4. debug programming model these registers are accessed through the bdm port by new bdm commands, wdmreg and rdmreg , described in section 5.5.3.3, ?command set descriptions.? these commands contain a 5-bit eld, drc, that speci es the register, as shown in table 5-3. pc breakpoint mask register pc breakpoint register data breakpoint register data breakpoint mask register trigger definition register configuration/status register bdm address attribute register note: each debug register is accessed as a 32-bit register; shaded ?lds above are not used (don? care). all debug control registers are writable from the external development system or the cpu via the wdebug instruction. csr is write-only from the programming model. it can be read or written through the bdm port using the rdmreg and wdmreg commands . address attribute trigger register address low breakpoint register address high breakpoint register 31 15 7 0 31 15 7 0 31 15 0 31 15 0 31 15 0 31 15 0 31 15 0 31 15 0 aatr ablr abhr baar csr dbr dbmr pbr pbmr tdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-7 programming model note: debug control registers can be written by the external development system or the cpu through the wdebug instruction. csr is write-only from the programming model. it can be read or written through the bdm port using the rdmreg and wdmreg commands. 5.4.1 address attribute trigger register (aatr) the address attribute trigger register (aatr) de nes address attributes and a mask to be matched in the trigger. the register value is compared with address attribute signals from the processor?s local high-speed bus, as de ned by the setting of the trigger de nition register (tdr). table 5-4 describes aatr elds . table 5-3. bdm/breakpoint registers drc[4?] register name abbreviation initial state page 0x00 con?uration/status register csr 0x0010_0000 p. 5-10 0x01?x04 reserved 0x05 bdm address attribute register baar 0x0000_0005 p. 5-9 0x06 address attribute trigger register aatr 0x0000_0005 p. 5-7 0x07 trigger de?ition register tdr 0x0000_0000 p. 5-14 0x08 program counter breakpoint register pbr p. 5-13 0x09 program counter breakpoint mask register pbmr p. 5-13 0x0a?x0b reserved 0x0c address breakpoint high register abhr p. 5-8 0x0d address breakpoint low register ablr p. 5-8 0x0e data breakpoint register dbr p. 5-12 0x0f data breakpoint mask register dbmr p. 5-12 1514131211109876543210 field rm szm ttm tmm r sz tt tm reset 0000_0000_0000_0101 r/w write only. aatr is accessible in supervisor mode as debug control register 0x06 using the wdebug instruction and through the bdm port using the wdmreg command. drc[4?] 0x06 figure 5-5. address attribute trigger register (aatr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-8 mcf5307 users manual programming model 5.4.2 address breakpoint registers (ablr, abhr) the address breakpoint low and high registers (ablr, abhr), figure 5-6, de ne regions in the processor?s data address space that can be used as part of the trigger. these register values are compared with the address for each transfer on the processor?s high-speed local bus. the trigger de nition register (tdr) identi es the trigger as one of three cases: 1. identically the value in ablr 2. inside the range bound by ablr and abhr inclusive 3. outside that same range table 5-4. aatr field descriptions bits name description 15 rm read/write mask. setting rm masks r in address comparisons. 14?3 szm size mask. setting an szm bit masks the corresponding sz bit in address comparisons. 12?1 ttm transfer type mask. setting a ttm bit masks the corresponding tt bit in address comparisons. 10? tmm transfer modi?r mask. setting a tmm bit masks the corresponding tm bit in address comparisons. 7 r read/write. r is compared with the r/w signal of the processors local bus. 6? sz size. compared to the processors local bus size signals. 00 longword 01 byte 10 word 11 reserved 4? tt transfer type. compared with the local bus transfer type signals. 00 normal processor access 01 reserved 10 emulator mode access 11 acknowledge/cpu space access these bits also de?e the tt encoding for bdm memory commands. in this case, the 01 encoding indicates an external or dma access (for backward compatibility). these bits affect the tm bits. 2? tm transfer modi?r. compared with the local bus transfer modi?r signals, which give supplemental information for each transfer type. tt = 00 (nor mal mode): 000 explicit cache line push 001 user data access 010 user code access 011 reserved 100 reserved 101 supervisor data access 110 supervisor code access 111 reserved tt = 10 (em ulator mode): 0xx?00 reserved 101 emulator mode data access 110 emulator mode code access 111 reserved tt = 11 (ac kno wledge/cpu space tr ansf ers): 000 cpu space access 001?11 interrupt acknowledge levels 1? these bits also de?e the tm encoding for bdm memory commands (for backward compatibility). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-9 programming model table 5-5 describes ablr elds. table 5-6 describes abhr elds . 5.4.3 bdm address attribute register (baar) the baar de nes the address space for memory-referencing bdm commands. see figure 5-7. the reset value of 0x5 sets supervisor data as the default address space. table 5-7 describes baar elds . 31 0 field address reset r/w write only. abhr is accessible in supervisor mode as debug control register 0x0c using the wdebug instruction and via the bdm port using the rdmreg and wdmreg commands. ablr is accessible in supervisor mode as debug control register 0x0d using the wdebug instruction and via the bdm port using the wdmreg command. drc[4?] 0x0d (ablr); 0x0c (abhr) figure 5-6. address breakpoint registers (ablr, abhr) table 5-5. ablr field description bits name description 31? address low address. holds the 32-bit address marking the lower bound of the address breakpoint range. breakpoints for speci? addresses are programmed into ablr. table 5-6. abhr field description bits name description 31? address high address. holds the 32-bit address marking the upper bound of the address breakpoint range. 76543210 field r sz tt tm reset 0000_0101 r/w write only. baar[r,sz] are loaded directly from the bdm command; baar[tt,tm] can be programmed as debug control register 0x05 from the external development system. for compatibility with rev. a, baar is loaded each time aatr is written. drc[4?] 0x05 figure 5-7. bdm address attribute register (baar) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-10 mcf5307 users manual programming model 5.4.4 con?uration/status register (csr) the con guration/status register (csr) de nes the debug con guration for the processor and memory subsystem and contains status information from the breakpoint logic. table 5-8 describes csr elds. table 5-7. baar field descriptions bits name description 7 r read/write 0 write 1 read 6? sz size 00 longword 01 byte 10 word 11 reserved 4? tt transfer type. see the tt de?ition in table 5-4. 2? tm transfer modi?r. see the tm de?ition in table 5-4. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field bstat fof trg halt bkpt hrl bkd ipw reset 0000 0 0 0 0 0001 0 r/w 1 r rrr r r r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field map trc emu ddc uhe btb 2 npl ipi ssm reset 0 0 0 00 0 00 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w drc[4?] 0x00 1 csr is write-only from the programming model. it can be read from and written to through the bdm port. csr is accessible in supervisor mode as debug control register 0x00 using the wdebug instruction and through the bdm port using the rdmreg and wdmreg commands. 2 bit 7 is reserved for motorola use and must be written as a zero. figure 5-8. configuration/status register (csr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-11 programming model table 5-8. csr field descriptions bit name description 31?8 bstat breakpoint status. provides read-only status information concerning hardware breakpoints. bstat is cleared by a tdr write or by a csr read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled. 0000 no breakpoints enabled 0001 waiting for level-1 breakpoint 0010 level-1 breakpoint triggered 0101 waiting for level-2 breakpoint 0110 level-2 breakpoint triggered 27 fof fault-on-fault. if fof is set, a catastrophic halt occurred and forced entry into bdm. 26 trg hardware breakpoint trigger. if trg is set, a hardware breakpoint halted the processor core and forced entry into bdm. reset and the debug go command clear trg. 25 halt processor halt. if halt is set, the processor executed a halt and forced entry into bdm. reset and the debug go command reset halt. 24 bkpt breakpoint assert. if bkpt is set, bkpt was asserted, forcing the processor into bdm. reset and the debug go command clears this bit. 23?0 hrl hardware revision level. indicates the level of debug module functionality. an emulator could use this information to identify the level of functionality supported. 0000 initial debug functionality (revision a) 0001 revision b (this is the only valid value for the mcf5307) 19 reserved, should be cleared. 18 bkd breakpoint disable. used to disable the normal bkpt input functionality and to allow the assertion of bkpt to generate a debug interrupt. 0 normal operation 1 bkpt is edge-sensitive: a high-to-low edge on bkpt signals a debug interrupt to the processor. the processor makes this interrupt request pending until the next sample point, when the exception is initiated. in the coldfire architecture, the interrupt sample point occurs once per instruction. there is no support for nesting debug interrupts. 17 pcd pstclk disable. setting pcd disables generation of pstclk, pst and ddata outputs and forces them to remain quiescent. 16 ipw inhibit processor writes. setting ipw inhibits processor-initiated writes to the debug modules programming model registers. ipw can be modi?d only by commands from the external development system. 15 map force processor references in emulator mode. 0 all emulator-mode references are mapped into supervisor code and data spaces. 1 the processor maps all references while in emulator mode to a special address space, tt = 10, tm = 101 or 110. 14 trc force emulation mode on trace exception. if trc = 1, the processor enters emulator mode when a trace exception occurs. 13 emu force emulation mode. if emu = 1, the processor begins executing in emulator mode. see section 5.6.1.1, ?mulator mode. 12?1 ddc debug data control. controls operand data capture for ddata, which displays the number of bytes de?ed by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple clock cycles). see table 5-2. 00 no operand data is displayed. 01 capture all write data. 10 capture all read data. 11 capture all read and write data. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-12 mcf5307 users manual programming model 5.4.5 data breakpoint/mask registers (dbr, dbmr) the data breakpoint registers, figure 5-9, specify data patterns used as part of the trigger into debug mode. only dbr bits not masked with a corresponding zero in dbmr are compared with the data from the processor?s local bus, as de ned in tdr. 10 uhe user halt enable. selects the cpu privilege level required to execute the halt instruction. 0 halt is a supervisor-only instruction. 1 halt is a supervisor/user instruction. 9? btb branch target bytes. de?es the number of bytes of branch target address ddata displays. 00 0 bytes 01 lower 2 bytes of the target address 10 lower 3 bytes of the target address 11 entire 4-byte target address see section 5.3.1, ?egin execution of taken branch (pst = 0x5). 7 reserved, should be cleared. 6 npl non-pipelined mode. determines whether the core operates in pipelined or mode or not. 0 pipelined mode 1 nonpipelined mode. the processor effectively executes one instruction at a time with no overlap. this adds at least 5 cycles to the execution time of each instruction. instruction folding is disabled. given an average execution latency of 1.6, throughput in non-pipeline mode would be 6.6, approximately 25% or less of pipelined performance. regardless of the npl state, a triggered pc breakpoint is always reported before the triggering instruction executes. in normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is imprecise. in non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise. an address or data breakpoint should always occur before the next instruction begins execution. therefore the occurrence of the address/data breakpoints should be guaranteed. 5 ipi ignore pending interrupts. 1 core ignores any pending interrupt requests signalled while in single-instruction-step mode. 0 core services any pending interrupt requests that were signalled while in single-step mode. 4 ssm single-step mode. setting ssm puts the processor in single-step mode. 0 normal mode. 1 single-step mode. the processor halts after execution of each instruction. while halted, any bdm command can be executed. on receipt of the go command, the processor executes the next instruction and halts again. this process continues until ssm is cleared. 3? reserved, should be cleared. 31 0 field data (dbr); mask (dbmr) reset uninitialized r/w dbr is accessible in supervisor mode as debug control register 0x0e, using the wdebug instruction and through the bdm port using the rdmreg and wdmreg commands. dbmr is accessible in supervisor mode as debug control register 0x0f using the wdebug instruction and via the bdm port using the wdmreg command. drc[4?] 0x0e (dbr), 0x0f (dbmr) figure 5-9. data breakpoint/mask registers (dbr and dbmr) table 5-8. csr field descriptions (continued) bit name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-13 programming model table 5-9 describes dbr elds. table 5-10 describes dbmr elds. the dbr supports both aligned and misaligned references. table 5-11 shows relationships between processor address, access size, and location within the 32-bit data bus. 5.4.6 program counter breakpoint/mask registers (pbr, pbmr) the pc breakpoint register (pbr) de nes an instruction address for use as part of the trigger. this register?s contents are compared with the processor?s program counter register when tdr is con gured appropriately. pbr bits are masked by clearing corresponding pbmr bits. results are compared with the processor?s program counter register, as de ned in tdr. figure 5-10 shows the pc breakpoint register. table 5-9. dbr field descriptions bits name description 31? data data breakpoint value. contains the value to be compared with the data value from the processors local bus as a breakpoint trigger. table 5-10. dbmr field descriptions bits name description 31? mask data breakpoint mask. the 32-bit mask for the data breakpoint trigger. clearing a dbr bit allows the corresponding dbr bit to be compared to the appropriate bit of the processors local data bus. setting a dbmr bit causes that bit to be ignored. table 5-11. access size and operand data location a[1:0] access size operand location 00 byte d[31:24] 01 byte d[23:16] 10 byte d[15:8] 11 byte d[7:0] 0x word d[31:16] 1x word d[15:0] xx longword d[31:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-14 mcf5307 users manual programming model table 5-12 describes pbr elds. figure 5-11 shows pbmr. table 5-13 describes pbmr elds. 5.4.7 trigger de?ition register (tdr) the tdr, shown in table 5-12, con gures the operation of the hardware breakpoint logic that corresponds with the abhr/ablr/aatr, pbr/pbmr, and dbr/dbmr registers within the debug module. the tdr controls the actions taken under the de ned conditions. breakpoint logic may be con gured as a one- or two-level trigger. tdr[31?16] de ne the second-level trigger and bits 15?0 de ne the rst-level trigger. 31 10 field program counter reset r/w write. pc breakpoint register is accessible in supervisor mode using the wdebug instruction and through the bdm port using the rdmreg and wdmreg commands using values shown in section 5.5.3.3, ?ommand set descriptions. drc[4?] 0x08 figure 5-10. program counter breakpoint register (pbr) table 5-12. pbr field descriptions bits name description 31? address pc breakpoint address. the 32-bit address to be compared with the pc as a breakpoint trigger. 31 0 field mask reset r/w write. pbmr is accessible in supervisor mode as debug control register 0x09 using the wdebug instruction and via the bdm port using the wdmreg command. drc[4?] 0x09 figure 5-11. program counter breakpoint mask register (pbmr) table 5-13. pbmr field descriptions bits name description 31? mask pc breakpoint mask. a zero in a bit position causes the corresponding pbr bit to be compared to the appropriate pc bit. set pbmr bits cause pbr bits to be ignored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-15 programming model note: the debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable tdr (by clearing tdr[29,13] before de ning triggers. a write to tdr clears the csr trigger status bits, csr[bstat]. section table 5-14., ?tdr field descriptions,? describes how to handle multiple breakpoint conditions. table 5-14 describes tdr elds. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field trc ebl edlw edwl edwu edll edlm edum eduu di eai ear eal epc pci reset 0000_0000_0000_0000 151413 12 11 10 9 8 7 6 543210 field lxt ebl edlw edwl edwu edll edlm edum eduu di eai ear eal epc pci reset 0000_0000_0000_0000 r/w write only. accessible in supervisor mode as debug control register 0x07 using the wdebug instruction and through the bdm port using the wdmreg command. drc[4?] 0x07 figure 5-12. trigger definition register (tdr) table 5-14. tdr field descriptions bits name description 31?0 trc trigger response control. determines how the processor responds to a completed trigger condition. the trigger response is always displayed on ddata. 00 display on ddata only 01 processor halt 10 debug interrupt 11 reserved 15:14 lxt level-x trigger. this is a rev. b function. the level-x trigger bit determines the logic operation for the trigger between the pc_condition and the (address_range & data_condition) where the inclusion of a data condition is optional. the coldfire debug architecture supports the creation of single or double-level triggers. tdr[15] 0 level-2 trigger = pc_condition & address_range & data_condition 1 level-2 trigger = pc_condition | (address_range & data_condition) tdr[14] 0 level-1 trigger = pc_condition & address_range & data_condition 1 level-1 trigger = pc_condition | (address_range & data_condition) 29/13 ebl enable breakpoint. global enable for the breakpoint trigger. setting tdr[ebl] enables a breakpoint trigger. clearing it disables all breakpoints. second-level trigger first-level trigger f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-16 mcf5307 users manual background debug mode (bdm) 5.5 background debug mode (bdm) the coldfire family implements a low-level system debugger in the microprocessor hardware. communication with the development system is handled through a dedicated, high-speed serial command interface. the coldfire architecture implements the bdm controller in a dedicated hardware module. although some bdm operations, such as cpu register accesses, require the cpu to be halted, other bdm commands, such as memory accesses, can be executed while the processor is running. 5.5.1 cpu halt although many bdm operations can occur in parallel with cpu operations, unrestricted bdm operation requires the cpu to be halted. the sources that can cause the cpu to halt are listed below in order of priority: 1. a catastrophic fault-on-fault condition automatically halts the processor. 28?2 12? ed x setting an ed x bit enables the corresponding data breakpoint condition based on the size and placement on the processors local data bus. clearing all ed x bits disables data breakpoints. 28/12 edlw data longword. entire processors local data bus. 27/11 edwl lower data word. 26/10 edwu upper data word. 25/9 edll lower lower data byte. low-order byte of the low-order word. 24/8 edlm lower middle data byte. high-order byte of the low-order word. 23/7 edum upper middle data byte. low-order byte of the high-order word. 22/6 eduu upper upper data byte. high-order byte of the high-order word. 21/5 di data breakpoint invert. provides a way to invert the logical sense of all the data breakpoint comparators. this can develop a trigger based on the occurrence of a data value other than the dbr contents. 20?8/ 4? ea x enable address bits. setting an ea bit enables the corresponding address breakpoint. clearing all three bits disables the breakpoint. 20/4 eai enable address breakpoint inverted. breakpoint is based outside the range between ablr and abhr. 19/3 ear enable address breakpoint range. the breakpoint is based on the inclusive range de?ed by ablr and abhr. 18/2 eal enable address breakpoint low. the breakpoint is based on the address in the ablr. 17/1 epc enable pc breakpoint. if set, this bit enables the pc breakpoint. 16/0 pci breakpoint invert. if set, this bit allows execution outside a given region as de?ed by pbr and pbmr to enable a trigger. if cleared, the pc breakpoint is de?ed within the region de?ed by pbr and pbmr. table 5-14. tdr field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-17 background debug mode (bdm) 2. a hardware breakpoint can be con gured to generate a pending halt condition similar to the assertion of bkpt . this type of halt is always rst made pending in the processor. next, the processor samples for pending halt and interrupt conditions once per instruction. when a pending condition is asserted, the processor halts execution at the next sample point. see section 5.6.1, ?theory of operation.? 3. the execution of a halt instruction immediately suspends execution. attempting to execute halt in user mode while csr[uhe] = 0 generates a privilege violation exception. if csr[uhe] = 1, halt can be executed in user mode. after halt executes, the processor can be restarted by serial shifting a go command into the debug module. execution continues at the instruction after halt. 4. the assertion of the bkpt input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. the processor samples for these conditions once during the execution of each instruction. if there is a pending halt condition at the sample time, the processor suspends execution and enters the halted state. the assertion of bkpt should be considered in the following two special cases: after the system reset signal is negated, the processor waits for 16 processor clock cycles before beginning reset exception processing. if the bkpt input is asserted within eight cycles after rsti is negated, the processor enters the halt state, signaling halt status (0xf) on the pst outputs. while the processor is in this state, all resources accessible through the debug module can be referenced. this is the only chance to force the processor into emulation mode through csr[emu]. after system initialization, the processor?s response to the go command depends on the set of bdm commands performed while it is halted for a breakpoint. speci cally, if the pc register was loaded, the go command causes the processor to exit halted state and pass control to the instruction address in the pc, bypassing normal reset exception processing. if the pc was not loaded, the go command causes the processor to exit halted state and continue reset exception processing. the coldfire architecture also handles a special case of bkpt being asserted while the processor is stopped by execution of the stop instruction. for this case, the processor exits the stopped mode and enters the halted state, at which point, all bdm commands may be exercised. when restarted, the processor continues by executing the next sequential instruction, that is, the instruction following the stop opcode. csr[27?24] indicates the halt source, showing the highest priority source for multiple halt conditions. 5.5.2 bdm serial interface when the cpu is halted and pst re ects the halt status, the development system can send unrestricted commands to the debug module. the debug module implements a synchronous protocol using two inputs (dsclk and dsi) and one output (dso), where dsclk and f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-18 mcf5307 users manual background debug mode (bdm) dsi must meet the required input setup and hold timings and the dso is speci ed as a delay relative to the rising edge of the processor clock. see table 5-1. the development system serves as the serial communication channel master and must generate dsclk. the serial channel operates at a frequency from dc to 1/5 of the processor frequency. the channel uses full-duplex mode, where data is sent and received simultaneously by both master and slave devices. the transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. as shown in figure 5-13, all state transitions are enabled on a rising edge of the processor clock when dsclk is high; that is, dsi is sampled and dso is driven. figure 5-13. bdm serial interface timing dsclk and dsi are synchronized inputs. dsclk acts as a pseudo clock enable and is sampled on the rising edge of the processor clk as well as the dsi. dso is delayed from the dsclk-enabled clk rising edge (registered after a bdm state machine state change). all events in the debug module?s serial state machine are based on the processor clock rising edge. dsclk must also be sampled low (on a positive edge of clk) between each bit exchange. the msb is transferred rst. because dso changes state based on an internally-recognized rising edge of dsclk, dsdo cannot be used to indicate the start of a serial transfer. the development system must count clock cycles in a given transfer. c1?c4 are described as follows: c1?first synchronization cycle for dsi (dsclk is high). c2?second synchronization cycle for dsi (dsclk is high). c3?bdm state machine changes state depending upon dsi and whether the entire input data transfer has been transmitted. c4?dso changes to next value. note: a not-ready response can be ignored except during a memory-referencing cycle. otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. pstclk dsclk cpu clk next state bdm state machine dso dsi current state current next past current c1 c2 c3 c4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-19 background debug mode (bdm) 5.5.2.1 receive packet format the basic receive packet, figure 5-14, consists of 16 data bits and 1 status bit. table 5-15 describes receive bdm packet elds. 5.5.2.2 transmit packet format the basic transmit packet, figure 5-15, consists of 16 data bits and 1 control bit. table 5-16 describes transmit bdm packet elds. 5.5.3 bdm command set table 5-17 summarizes the bdm command set. subsequent paragraphs contain detailed descriptions of each command. issuing a bdm command when the processor is accessing debug module registers using the wdebug instruction causes unde ned behavior. 16 15 0 s data field [15:0] figure 5-14. receive bdm packet table 5-15. receive bdm packet field description bits name description 16 s status. indicates the status of cpu-generated messages listed below. the not-ready response can be ignored unless a memory-referencing cycle is in progress. otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. s data message 0 xxxx valid data transfer 0 0xffff status ok 1 0x0000 not ready with response; come again 1 0x0001 error?erminated bus cycle; data invalid 1 0xffff illegal command 15? data data. contains the message to be sent from the debug module to the development system. the response message is always a single word, with the data ?ld encoded as shown above. 16 15 0 c d[15:0] figure 5-15. transmit bdm packet table 5-16. transmit bdm packet field description bits name description 16 c control. this bit is reserved. command and data transfers initiated by the development system should clear c. 15? data contains the data to be sent from the development system to the debug module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-20 mcf5307 users manual background debug mode (bdm) unassigned command opcodes are reserved by motorola. all unused command formats within any revision level perform a nop and return the illegal command response . 5.5.3.1 coldfire bdm command format all coldfire family bdm commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in figure 5-16. table 5-17. bdm command summary command mnemonic description cpu state 1 1 general command effect and/or requirements on cpu operation: - halted. the cpu must be halted to perform this command. - steal. command generates bus cycles that can be interleaved with bus accesses. - parallel. command is executed in parallel with cpu activity. section command (hex) read a/d register rareg / rdreg read the selected address or data register and return the results through the serial interface. halted 5.5.3.3.1 0x218 {a/d, reg[2:0]} write a/d register wareg / wdreg write the data operand to the speci?d address or data register. halted 5.5.3.3.2 0x208 {a/d, reg[2:0]} read memory location read read the data at the memory location speci?d by the longword address. steal 5.5.3.3.3 0x1900?yte 0x1940?ord 0x1980?word write memory location write write the operand data to the memory location speci?d by the longword address. steal 5.5.3.3.4 0x1800?yte 0x1840?ord 0x1880?word dump memory block dump used with read to dump large blocks of memory. an initial read is executed to set up the starting address of the block and to retrieve the ?st result. a dump command retrieves subsequent operands. steal 5.5.3.3.5 0x1d00?yte 0x1d40?ord 0x1d80?word fill memory block fill used with write to ?l large blocks of memory. an initial write is executed to set up the starting address of the block and to supply the ?st operand. a fill command writes subsequent operands. steal 5.5.3.3.6 0x1c00?yte 0x1c40?ord 0x1c80?word resume execution go the pipeline is ?shed and re?led before resuming instruction execution at the current pc. halted 5.5.3.3.7 0x0c00 no operation nop perform no operation; may be used as a null command. parallel 5.5.3.3.8 0x0000 output the current pc sync _ pc capture the current pc and display it on the pst/ddata output pins. parallel 5.5.3.3.9 0x0001 read control register rcreg read the system control register. halted 5.5.3.3.10 0x2980 write control register wcreg write the operand data to the system control register. halted 5.5.3.3.11 0x2880 read debug module register rdmreg read the debug module register. parallel 5.5.3.3.12 0x2d {0x4 2 drc[4:0]} 2 0x4 is a three-bit ?ld. write debug module register wdmreg write the operand data to the debug module register. parallel 5.5.3.3.13 0x2c {0x4 2 drc[4:0]} f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-21 background debug mode (bdm) table 5-18 describes bdm elds. 5.5.3.1.1 extension words as required some commands require extension words for addresses and/or immediate data. addresses require two extension words because only absolute long addressing is permitted. longword accesses are forcibly longword-aligned and word accesses are forcibly word-aligned. immediate data can be 1 or 2 words long. byte and word data each requires a single extension word and longword data requires two extension words. operands and addresses are transferred most-signi cant word rst. in the following descriptions of the bdm command set, the optional set of extension words is de ned as address, data, or operand data. 5.5.3.2 command sequence diagrams the command sequence diagram in figure 5-17 shows serial bus traf c for commands. each bubble represents a 17-bit bus transfer. the top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module?s response to the previous development system commands. command and result transactions overlap to minimize latency. 15 1098765432 0 operation 0 r/w op size 0 0 a/d register extension word(s) figure 5-16. bdm command format table 5-18. bdm field descriptions bit name description 15?0 operation speci?s the command. these values are listed in table 5-17. 9 0 reserved 8 r/w direction of operand transfer. 0 data is written to the cpu or to memory from the development system. 1 the transfer is from the cpu to the development system. 7? operand size operand data size for sized operations. addresses are expressed as 32-bit absolute values. note that a command performing a byte-sized memory read leaves the upper 8 bits of the response data unde?ed. referenced data is returned in the lower 8 bits of the response. operand size bit values 00 byte 8 bits 01 word 16 bits 10 longword 32 bits 11 reserved 5? 00 reserved 3 a/d address/data. determines whether the register ?ld speci?s a data or address register. 0 indicates a data register. 1 indicates an address register. 2? register contains the register number in commands that operate on processor registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-22 mcf5307 users manual background debug mode (bdm) figure 5-17. command sequence diagram the sequence is as follows: in cycle 1, the development system command is issued ( read in this example). the debug module responds with either the low-order results of the previous command or a command complete status of the previous command, if no results are required. in cycle 2, the development system supplies the high-order 16 address bits. the debug module returns a not-ready response unless the received command is decoded as unimplemented, which is indicated by the illegal command encoding. if this occurs, the development system should retransmit the command. note: a not-ready response can be ignored except during a memory-referencing cycle. otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. in cycle 3, the development system supplies the low-order 16 address bits. the debug module always returns a not-ready response. at the completion of cycle 3, the debug module initiates a memory read operation. any serial transfers that begin during a memory access return a not-ready response. commands transmitted to the debug module command code transmitted during this cycle high-order 16 bits of memory address low-order 16 bits of memory address sequence taken if operation has not completed data unused from this transfer sequence taken if illegal command is received by debug module results from previous command responses from the debug module nonserial-related activity ms addr "not ready" xxx "illegal" ls addr "not ready" next cmd "not ready" read (long) ??? next cmd "not ready" xxx "not ready" xxxxx xxx berr ms result next cmd ls result read memory location next command code sequence taken if bus error occurs on memory access high- and low-order 16 bits of result xxx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-23 background debug mode (bdm) results are returned in the two serial transfer cycles after the memory access completes. for any command performing a byte-sized memory read operation, the upper 8 bits of the response data are unde ned and the referenced data is returned in the lower 8 bits. the next command?s opcode is sent to the debug module during the nal transfer. if a memory or register access is terminated with a bus error, the error status (s = 1, data = 0x0001) is returned instead of result data. 5.5.3.3 command set descriptions the following sections describe the commands summarized in table 5-17. note: the bdm status bit (s) is 0 for normally completed commands; s = 1 for illegal commands, not-ready responses, and transfers with bus-errors. section 5.5.2, ?bdm serial interface,? describes the receive packet format. motorola reserves unassigned command opcodes for future expansion. unused command formats in any revision level perform a nop and return an illegal command response. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-24 mcf5307 users manual background debug mode (bdm) 5.5.3.3.1 read a/d register ( rareg / rdreg ) read the selected address or data register and return the 32-bit result. a bus error response is returned if the cpu core is not halted. command/result formats: command sequence: figure 5-19. rareg / rdreg command sequence operand data: none result data: the contents of the selected register are returned as a longword value, most-signi cant word rst. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command 0x2 0x1 0x8 a/d register result d[31:16] d[15:0] figure 5-18. rareg / rdreg command format xxx ms result next cmd ls result rareg/rdreg ??? xxx berr next cmd "not ready" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-25 background debug mode (bdm) 5.5.3.3.2 write a/d register ( wareg / wdreg ) the operand longword data is written to the speci ed address or data register. a write alters all 32 register bits. a bus error response is returned if the cpu core is not halted. command format: command sequence figure 5-21. wareg / wdreg command sequence operand data longword data is written into the speci ed address or data register. the data is supplied most-signi cant word rst. result data command complete status is indicated by returning 0xffff (with s cleared) when the register write is complete. 1514131211109876543210 0x2 0x0 0x8 a/d register d[31:16] d[15:0] figure 5-20. wareg / wdreg command format ms data "not ready" xxx ls data "not ready" next cmd "not ready" wdreg/wareg ??? next cmd "cmd complete" berr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-26 mcf5307 users manual background debug mode (bdm) 5.5.3.3.3 read memory location ( read ) read data at the longword address. address space is de ned by baar[tt,tm]. hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. command/result formats: command sequence: figure 5-23. read command sequence operand data the only operand is the longword address of the requested location. result data word results return 16 bits of data; longword results return 32. bytes are returned in the lsb of a word result, the upper byte is unde ned. 0x0001 (s = 1) is returned if a bus error occurs. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte command 0x1 0x9 0x0 0x0 a[31:16] a[15:0] result xxxxxxxx d[7:0] word command 0x1 0x9 0x4 0x0 a[31:16] a[15:0] result d[15:0] longword command 0x1 0x9 0x8 0x0 a[31:16] a[15:0] result d[31:16] d[15:0] figure 5-22. read command/result formats ms addr "not ready" ls addr "not ready" read (b/w) ??? next cmd "not ready" xxx "not ready" xxx xxx berr result next cmd read memory location ms addr "not ready" ls addr "not ready" read (long) ??? next cmd "not ready" xxx "not ready" xxx xxx berr ms result xxx read memory location next cmd ls result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-27 background debug mode (bdm) 5.5.3.3.4 write memory location ( write ) write data to the memory location speci ed by the longword address. the address space is de ned by baar[tt,tm]. hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. command formats: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 byte 0x1 0x8 0x0 0x0 a[31:16] a[15:0] x x x x x x x x d[7:0] word 0x1 0x8 0x4 0x0 a[31:16] a[15:0] d[15:0] longword 0x1 0x8 0x8 0x0 a[31:16] a[15:0] d[31:16] d[15:0] figure 5-24. write command format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-28 mcf5307 users manual background debug mode (bdm) command sequence: figure 5-25. write command sequence operand data this two-operand instruction requires a longword absolute address that speci es a location to which the data operand is to be written. byte data is sent as a 16-bit word, justi ed in the lsb; 16- and 32-bit operands are sent as 16 and 32 bits, respectively result data command complete status is indicated by returning 0xffff (with s cleared) when the register write is complete. a value of 0x0001 (with s set) is returned if a bus error occurs. ms addr "not ready" ls addr "not ready" write (b/w) ??? next cmd "not ready" xxx "not ready" xxx xxx berr "cmd complete" next cmd write memory location data "not ready" ms addr "not ready" ls addr "not ready" write (long) ??? next cmd "not ready" xxx "not ready" xxx xxx berr "cmd complete" next cmd write memory location ms data "not ready" ls data "not ready" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-29 background debug mode (bdm) 5.5.3.3.5 dump memory block ( dump ) dump is used with the read command to access large blocks of memory. an initial read is executed to set up the starting address of the block and to retrieve the rst result. if an initial read is not executed before the rst dump , an illegal command response is returned. the dump command retrieves subsequent operands. the initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. subsequent dump commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register. note: dump does not check for a valid address; it is a valid command only when preceded by nop , read , or another dump command. otherwise, an illegal command response is returned. nop can be used for intercommand padding without corrupting the address pointer. the size eld is examined each time a dump command is processed, allowing the operand size to be dynamically altered. command/result formats: 1514131211109876543210 byte command 0x1 0xd 0x0 0x0 result xxxxxxxx d[7:0] word command 0x1 0xd 0x4 0x0 result d[15:0] longword command 0x1 0xd 0x8 0x0 result d[31:16] d[15:0] figure 5-26. dump command/result formats f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-30 mcf5307 users manual background debug mode (bdm) command sequence: figure 5-27. dump command sequence operand data: none result data: requested data is returned as either a word or longword. byte data is returned in the least-signi cant byte of a word result. word results return 16 bits of signi cant data; longword results return 32 bits. a value of 0x0001 (with s set) is returned if a bus error occurs. xxx "not ready" next cmd result xxx berr xxx "illegal" next cmd "not ready" next cmd "not ready" read memory location dump (b/w) ??? xxx "not ready" next cmd ms result xxx berr xxx "illegal" next cmd "not ready" next cmd "not ready" read memory location dump (long) ??? next cmd ls result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-31 background debug mode (bdm) 5.5.3.3.6 fill memory block ( fill ) a fill command is used with the write command to access large blocks of memory. an initial write is executed to set up the starting address of the block and to supply the rst operand. the fill command writes subsequent operands. the initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register after the memory write. subsequent fill commands use this address, perform the write, increment it by the current operand size, and store the updated address in the temporary register. if an initial write is not executed preceding the rst fill command, the illegal command response is returned. note: the fill command does not check for a valid address? fill is a valid command only when preceded by another fill , a nop , or a write command. otherwise, an illegal command response is returned. the nop command can be used for intercommand padding without corrupting the address pointer. the size eld is examined each time a fill command is processed, allowing the operand size to be altered dynamically. command formats: 1514131211109876543210 byte 0x1 0xc 0x0 0x0 xxxxxxxx d[7:0] word 0x1 0xc 0x4 0x0 d[15:0] longword 0x1 0xc 0x8 0x0 d[31:16] d[15:0] figure 5-28. fill command format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-32 mcf5307 users manual background debug mode (bdm) command sequence: figure 5-29. fill command sequence operand data: a single operand is data to be written to the memory location. byte data is sent as a 16-bit word, justi ed in the least-signi cant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively. result data: command complete status (0xffff) is returned when the register write is complete. a value of 0x0001 (with s set) is returned if a bus error occurs. next cmd "not ready" "not ready" xxx berr "cmd complete" data "not ready" xxx next cmd xxx "illegal" next cmd "not ready" fill (long) ??? write memory location next cmd "not ready" xxx "not ready" xxx berr "cmd complete" ms data "not ready" next cmd xxx "illegal" next cmd "not ready" ls data "not ready" write memory location fill (b/w) ??? fill (long) fill (b/w) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-33 background debug mode (bdm) 5.5.3.3.7 resume execution ( go ) the pipeline is ushed and re lled before normal instruction execution resumes. prefetching begins at the current address in the pc and at the current privilege level. if any register (such as the pc or sr) is altered by a bdm command while the processor is halted, the updated value is used when prefetching resumes. if a go command is issued and the cpu is not halted, the command is ignored. command sequence: figure 5-31. go command sequence operand data: none result data: the command-complete response (0xffff) is returned during the next shift operation. 1514131211109876543210 0x0 0xc 0x0 0x0 figure 5-30. go command format go ??? next cmd "cmd complete" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-34 mcf5307 users manual background debug mode (bdm) 5.5.3.3.8 no operation ( nop ) nop performs no operation and may be used as a null command where required. command formats: command sequence: figure 5-33. nop command sequence operand data: none result data: the command-complete response, 0xffff (with s cleared), is returned during the next shift operation. 15 12 11 8 7 4 3 0 0x0 0x0 0x0 0x0 figure 5-32. nop command format nop ??? next cmd "cmd complete" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-35 background debug mode (bdm) 5.5.3.3.9 synchronize pc to the pst/ddata lines ( sync _ pc ) the sync _ pc command captures the current pc and displays it on the pst / ddata outputs. after the debug module receives the command, it sends a signal to the coldfire processor that the current pc must be displayed. the processor then forces an instruction fetch at the next pc with the address being captured in the ddata logic under control of csr[btb]. the speci c sequence of pst and ddata values is as follows: 1. debug signals a sync _ pc command is pending. 2. cpu completes the current instruction. 3. cpu forces an instruction fetch to the next pc, generates a pst = 0x5 value indicating a taken branch and signals the capture of ddata. 4. the instruction address corresponding to the pc is captured. 5. the pst marker (0x9?0xb) is generated and displayed as de ned by csr[btb] followed by the captured pc address. the sync _ pc command can be used to dynamically access the pc for performance monitoring. the execution of this command is considerably less obtrusive to the real-time operation of an application than a halt - cpu / read - pc / resume command sequence. command formats: command sequence: figure 5-35. sync _ pc command sequence operand data: none result data: command complete status (0xffff) is returned when the register write is complete. 15 12 11 8 7 4 3 0 0x0 0x0 0x0 0x1 figure 5-34. sync _ pc command format nop ??? next cmd "cmd complete" sync_pc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-36 mcf5307 users manual background debug mode (bdm) 5.5.3.3.10 read control register ( rcreg ) read the selected control register and return the 32-bit result. accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. the second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the speci ed control register. the 12-bit rc eld is the same as that used by the movec instruction. command/result formats: rc encoding: command sequence: figure 5-37. rcreg command sequence operand data: the only operand is the 32-bit rc control register select eld. result data: control register contents are returned as a longword, most-signi cant word rst. the implemented portion of registers smaller than 32 bits is guaranteed correct; other bits are unde ned. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command 0x2 0x9 0x8 0x0 0x0 0x0 0x0 0x0 0x0 rc result d[31:16] d[15:0] figure 5-36. rcreg command/result formats table 5-19. control register map rc register de?ition rc register de?ition 0x002 cache control register (cacr) 0x805 mac mask register (mask) 1 0x004 access control register 0 (acr0) 0x806 mac accumulator (acc) 1 0x005 access control register 1 (acr1) 0x80e status register (sr) 0x801 vector base register (vbr) 0x80f program register (pc) 0x804 mac status register (macsr) 1 1 available if the optional mac unit is present. 0xc04 ram base address register (rambar) ext word "not ready" ext word "not ready" rcreg ??? next cmd "not ready" xxx "not ready" xxx xxx berr ms result read memory location next cmd ls result xxx ms addr control register ms addr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-37 background debug mode (bdm) 5.5.3.3.11 write control register ( wcreg ) the operand (longword) data is written to the speci ed control register. the write alters all 32 register bits. command/result formats: command sequence: figure 5-39. wcreg command sequence operand data: this instruction requires two longword operands. the rst selects the register to which the operand data is to be written; the second contains the data. result data: successful write operations return 0xffff. bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 rc result d[31:16] d[15:0] figure 5-38. wcreg command/result formats ext word "not ready" ext word "not ready" wcreg ??? next cmd "not ready" xxx "not ready" xxx xxx berr "cmd complete" next cmd write memory location ms data "not ready" ls data "not ready" control register write ms addr ms addr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-38 mcf5307 users manual background debug mode (bdm) 5.5.3.3.12 read debug module register ( rdmreg ) read the selected debug module register and return the 32-bit result. the only valid register selection for the rdmreg command is csr (drc = 0x00). note that this read of the csr clears the trigger status bits (csr[bstat]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled. command/result formats: table 5-20 shows the de nition of drc encoding. command sequence: figure 5-41. rdmreg command sequence operand data: none result data: the contents of the selected debug register are returned as a longword value. the data is returned most-signi cant word rst. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command 0x2 0xd 0x4 1 1 note 0x4 is a 3-bit eld drc result d[31:16] d[15:0] figure 5-40. rdmreg bdm command/result formats table 5-20. definition of drc encoding?ead drc[4:0] debug register de?ition mnemonic initial state page 0x00 con guration/status csr 0x0 p. 5-10 0x01 0x1f reserved xxx ms result xxx "illegal" next cmd ls result next cmd "not ready" rdmreg ??? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-39 real-time debug support 5.5.3.3.13 write debug module register ( wdmreg ) the operand (longword) data is written to the speci ed debug module register. all 32 bits of the register are altered by the write. dsclk must be inactive while the debug module register writes from the cpu accesses are performed using the wdebug instruction. command format: table 5-3 shows the de nition of the drc write encoding. command sequence: figure 5-43. wdmreg command sequence operand data: longword data is written into the speci ed debug register. the data is supplied most-signi cant word rst. result data: command complete status (0xffff) is returned when register write is complete. 5.6 real-time debug support the coldfire family provides support debugging real-time applications. for these types of embedded systems, the processor must continue to operate during debug. the foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can generally tolerate small intrusions into the real-time operation. the debug module provides three types of breakpoints?pc with mask, operand address range, and data with mask. these breakpoints can be con gured into one- or two-level triggers with the exact trigger response also programmable. the debug module programming model can be written from either the external development system using the debug serial interface or from the processor?s supervisor programming model using the wdebug instruction. only csr is readable using the external development system. figure 5-42. wdmreg bdm command format 1514131211109876543210 0x2 0xc 0x4 1 1 note: 0x4 is a three-bit eld drc d[31:16] d[15:0] ms data "not ready" xxx "illegal" ls data "not ready" next cmd "not ready" wdmreg ??? next cmd "cmd complete" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-40 mcf5307 users manual real-time debug support 5.6.1 theory of operation breakpoint hardware can be con gured to respond to triggers in several ways. the response desired is programmed into tdr. as shown in table 5-21, when a breakpoint is triggered, an indication (csr[bstat]) is provided on the ddata output port when it is not displaying captured processor status, operands, or branch addresses. the breakpoint status is also posted in csr. note that csr[bstat] is cleared by a csr read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. status is also cleared by writing to tdr. bdm instructions use the appropriate registers to load and con gure breakpoints. as the system operates, a breakpoint trigger generates the response de ned in tdr. pc breakpoints are treated in a precise manner?exception recognition and processing are initiated before the excepting instruction is executed. all other breakpoint events are recognized on the processor?s local bus, but are made pending to the processor and sampled like other interrupt conditions. as a result, these interrupts are imprecise. in systems that tolerate the processor being halted, a bdm-entry can be used. with tdr[trc] = 01, a breakpoint trigger causes the core to halt (pst = 0xf). if the processor core cannot be halted, the debug interrupt can be used. with this con guration, tdr[trc] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher than the nonmaskable level-7 interrupt request. as with all interrupts, it is made pending until the processor reaches a sample point, which occurs once per instruction. again, the hardware forces the pc breakpoint to occur before the targeted instruction executes. this is possible because the pc breakpoint is enabled when interrupt sampling occurs. for address and data breakpoints, reporting is considered imprecise because several instructions may execute after the triggering address or data is detected. as soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. this event is signaled externally by the assertion of a unique pst value (pst = 0xd) for multiple cycles. the core enters emulator mode when exception processing begins. after the standard 8-byte exception stack is created, the processor table 5-21. ddata[3:0]/csr[bstat] breakpoint response ddata[3:0]/csr[bstat] 1 1 encodings not shown are reserved for future use. breakpoint status 0000/0000 no breakpoints enabled 0010/0001 waiting for level-1 breakpoint 0100/0010 level-1 breakpoint triggered 1010/0101 waiting for level-2 breakpoint 1100/0110 level-2 breakpoint triggered f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-41 real-time debug support fetches a unique exception vector, 12, from the vector table. execution continues at the instruction address in the vector corresponding to the breakpoint triggered. all interrupts are ignored while the processor is in emulator mode. the debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program-visible registers into a reserved memory area. when debug interrupt operations complete, the rte instruction executes and the processor exits emulator mode. after the debug interrupt handler completes execution, the external development system can use bdm commands to read the reserved memory locations. the generation of another debug interrupt during the rst instruction after the rte exits emulator mode is inhibited. this behavior is consistent with the existing logic involving trace mode where the rst instruction executes before another trace exception is generated. thus, all hardware breakpoints are disabled until the rst instruction after the rte completes execution, regardless of the programmed trigger response. 5.6.1.1 emulator mode emulator mode is used to facilitate non-intrusive emulator functionality. this mode can be entered in three different ways: setting csr[emu] forces the processor into emulator mode. emu is examined only if rsti is negated and the processor begins reset exception processing. it can be set while the processor is halted before reset exception processing begins. see section 5.5.1, ?cpu halt.? a debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins. setting csr[trc] forces the processor into emulation mode when trace exception processing begins. while operating in emulation mode, the processor exhibits the following properties: all interrupts are ignored, including level-7 interrupts. if csr[map] = 1, all caching of memory and the sram module are disabled. all memory accesses are forced into a specially mapped address space signaled by tt = 0x2, tm = 0x5 or 0x6. this includes stack frame writes and the vector fetch for the exception that forced entry into this mode. the rte instruction exits emulation mode. the processor status output port provides a unique encoding for emulator mode entry (0xd) and exit (0x7). 5.6.2 concurrent bdm and processor operation the debug module supports concurrent operation of both the processor and most bdm commands. bdm commands may be executed while the processor is running, except those following operations that access processor/memory registers: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-42 mcf5307 users manual motorola-recommended bdm pinout read/write address and data registers read/write control registers for bdm commands that access memory, the debug module requests the processor?s local bus. the processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. after the debug module bus cycle, the processor reclaims the bus. breakpoint registers must be carefully con gured in a development system if the processor is executing. the debug module contains no hardware interlocks, so tdr should be disabled while breakpoint registers are loaded, after which tdr can be written to de ne the exact trigger. this prevents spurious breakpoint triggers. because there are no hardware interlocks in the debug unit, no bdm operations are allowed while the cpu is writing the debug?s registers (dsclk must be inactive). 5.7 motorola-recommended bdm pinout the coldfire bdm connector, figure 5-44, is a 26-pin berg connector arranged 2 x 13. figure 5-44. recommended bdm connector 5.8 processor status, ddata de?ition this section speci es the coldfire processor and debug module?s generation of the processor status (pst) and debug data (ddata) output on an instruction basis. in general, the pst/ddata output for an instruction is de ned as follows: pst = 0x1, {pst = [0x89b], ddata= operand} where the {...} de nition is optional operand information de ned by the setting of the csr. 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 developer reserved 1 gnd gnd reset pad-voltage 2 gnd pst2 pst0 ddata2 ddata0 motorola reserved gnd core-voltage bkpt dsclk developer reserved 1 dsi dso pst3 pst1 ddata3 ddata1 gnd motorola reserved clk_cpu ta 2 supplied by target 1 pins reserved for bdm developer use. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-43 processor status, ddata de?ition the csr provides capabilities to display operands based on reference type (read, write, or both). additionally, for certain change-of- ow branch instructions, another csr eld provides the capability to display {0x2, 0x3, 0x4} bytes of the target instruction address. for both situations, an optional pst value {0x8, 0x9, 0xb} provides the marker identifying the size and presence of valid data on the ddata output. 5.8.1 user instruction set table 5-22 shows the pst/ddata speci cation for user-mode instructions. rn represents any {dn, an} register. in this de nition, the ?y? suf x generally denotes the source and ?x? denotes the destination operand. for a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. the ?dd? nomenclature refers to the ddata outputs. table 5-22. pst/ddata specification for user-mode instructions instruction operand syntax pst/ddata add.l y,rx pst = 0x1, {pst = 0xb, dd = source operand} add.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} addi.l #imm,dx pst = 0x1 addq.l #imm,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} addx.l dy,dx pst = 0x1 and.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} and.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} andi.l #imm,dx pst = 0x1 asl.l {dy,#imm},dx pst = 0x1 asr.l {dy,#imm},dx pst = 0x1 bcc.{b,w} if taken, then pst = 0x5, else pst = 0x1 bchg #imm,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bchg dy,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bclr #imm,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bclr dy,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bra.{b,w} pst = 0x5 bset #imm,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bset dy,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bsr.{b,w} pst = 0x5, {pst = 0xb, dd = destination operand} btst #imm,x pst = 0x1, {pst = 0x8, dd = source operand} btst dy,x pst = 0x1, {pst = 0x8, dd = source operand} clr.b x pst = 0x1, {pst = 0x8, dd = destination operand} clr.l x pst = 0x1, {pst = 0xb, dd = destination operand} clr.w x pst = 0x1, {pst = 0x9, dd = destination operand} f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-44 mcf5307 users manual processor status, ddata de?ition cmp.l y,rx pst = 0x1, {pst = 0xb, dd = source operand} cmpi.l #imm,dx pst = 0x1 divs.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} divs.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} divu.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} divu.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} eor.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} eori.l #imm,dx pst = 0x1 ext.l dx pst = 0x1 ext.w dx pst = 0x1 extb.l dx pst = 0x1 jmp x pst = 0x5, {pst = [0x9ab], dd = target address} 1 jsr x pst = 0x5, {pst = [0x9ab], dd = target address}, {pst = 0x b , dd = destination operand} 1 lea y,ax pst = 0x1 link.w ay,#imm pst = 0x1, {pst = 0xb, dd = destination operand} lsl.l {dy,#imm},dx pst = 0x1 lsr.l {dy,#imm},dx pst = 0x1 mac.l pst = 0x1 mac.l ry,rx pst = 0x1 mac.l ry,rx,ea,rw pst = 0x1, {pst = 0xb, dd = source operand} mac.w pst = 0x1 mac.w ry,rx pst = 0x1 mac.w ry,rx,ea,rw pst = 0x1, {pst = 0xb, dd = source operand} move.b y,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} move.l y,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} move.l y,acc pst = 0x1 move.l y,macsr pst = 0x1 move.l y,mask pst = 0x1 move.l acc,rx pst = 0x1 move.l macsr,ccr pst = 0x1 move.l macsr,rx pst = 0x1 move.l mask,rx pst = 0x1 move.w y,x pst = 0x1, {pst = 0x9, dd = source}, {pst = 0x9, dd = destination} move.w ccr,dx pst = 0x1 move.w {dy,#imm},ccr pst = 0x1 table 5-22. pst/ddata specification for user-mode instructions (continued) instruction operand syntax pst/ddata f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-45 processor status, ddata de?ition movem.l #list,x pst = 0x1, {pst = 0xb, dd = destination},... 2 movem.l y,#list pst = 0x1, {pst = 0xb, dd = source},... 2 moveq #imm,dx pst = 0x1 msac.l ry,rx pst = 0x1 msac.l ry,rx,ea,rw pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} msac.w ry,rx pst = 0x1 msac.w ry,rx,ea,rw pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} muls.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} muls.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} mulu.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} mulu.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} neg.l dx pst = 0x1 negx.l dx pst = 0x1 nop pst = 0x1 not.l dx pst = 0x1 or.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} or.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} ori.l #imm,dx pst = 0x1 pea y pst = 0x1, {pst = 0xb, dd = destination operand} pulse pst = 0x4 rems.l y,dx:dw pst = 0x1, {pst = 0xb, dd = source operand} remu.l y,dx:dw pst = 0x1, {pst = 0xb, dd = source operand} rts pst = 0x1, {pst = 0xb, dd = source operand}, pst = 0x5, {pst = [0x9ab], dd = target address} scc dx pst = 0x1 sub.l y,rx pst = 0x1, {pst = 0xb, dd = source operand} sub.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} subi.l #imm,dx pst = 0x1 subq.l #imm,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} subx.l dy,dx pst = 0x1 swap dx pst = 0x1 trap #imm pst = 0x1 3 trapf pst = 0x1 tst.b x pst = 0x1, {pst = 0x8, dd = source operand} tst.l x pst = 0x1, {pst = 0xb, dd = source operand} tst.w x pst = 0x1, {pst = 0x9, dd = source operand} table 5-22. pst/ddata specification for user-mode instructions (continued) instruction operand syntax pst/ddata f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-46 mcf5307 users manual processor status, ddata de?ition exception processing pst = 0xc, {pst = 0xb, dd = destination},// stack frame {pst = 0xb, dd = destination},// stack frame {pst = 0xb, dd = source},// vector read pst = 0x5, {pst = [0x9ab], dd = target}// pc of handler the pst/ddata speci cation for the reset exception is shown below: exception processing pst = 0xc, pst = 0x5,{pst = [0x9ab], dd = target} // pc of handler the initial references at address 0 and 4 are never captured nor displayed since these accesses are treated as instruction fetches. for all types of exception processing, the pst = 0xc value is driven at all times, unless the pst output is needed for one of the optional marker values or for the taken branch indicator (0x5). 5.8.2 supervisor instruction set the supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below. the pst/ddata speci cation for these opcodes is shown in table 5-23. unlk ax pst = 0x1, {pst = 0xb, dd = destination operand} wddata.b y pst = 0x4, {pst = 0x8, dd = source operand wddata.l y pst = 0x4, {pst = 0xb, dd = source operand wddata.w y pst = 0x4, {pst = 0x9, dd = source operand 1 for jmp and jsr instructions, the optional target instruction address is displayed only for those effective address elds de ning variant addressing modes. this includes the following x values: (an), (d16,an), (d8,an,xi), (d8,pc,xi). 2 for move multiple instructions (movem), the processor automatically generates line-sized transfers if the operand address reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. for these line-sized transfers, the operand data is never captured nor displayed, regardless of the csr value. the automatic line-sized burst transfers are provided to maximize performance during these sequential memory access operations. 3 during normal exception processing, the pst output is driven to a 0xc indicating the exception processing state. the exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed. table 5-23. pst/ddata specification for supervisor-mode instructions instruction operand syntax pstddata cpushl pst = 0x1 halt pst = 0x1, pst = 0xf move.w sr,dx pst = 0x1 move.w {dy,#imm},sr pst = 0x1, {pst = 3} table 5-22. pst/ddata specification for user-mode instructions (continued) instruction operand syntax pst/ddata f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 5. debug support 5-47 processor status, ddata de?ition the move-to-sr and rte instructions include an optional pst = 0x3 value, indicating an entry into user mode. additionally, if the execution of a rte instruction returns the processor to emulator mode, a multiple-cycle status of 0xd is signaled. similar to the exception processing mode, the stopped state (pst = 0xe) and the halted state (pst = 0xf) display this status throughout the entire time the coldfire processor is in the given mode. movec ry,rc pst = 0x1 rte pst = 0x7, {pst = 0xb, dd = source operand}, {pst = 3}, { pst = 0xb, dd = source operand}, pst = 0x5, {[pst = 0x9ab], dd = target address} stop #imm pst = 0x1, pst = 0xe wdebug y pst = 0x1, {pst = 0xb, dd = source, pst = 0xb, dd = source} table 5-23. pst/ddata specification for supervisor-mode instructions instruction operand syntax pstddata f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
5-48 mcf5307 users manual processor status, ddata de?ition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
part ii. system integration module (sim) ii-i part ii system integration module (sim) intended audience part ii is intended for users who need to understand the interface between the coldfire core processor complex, described in part i, and internal peripheral devices, described in part iii. it includes a general description of the sim and individual chapters that describe components of the sim, such as the phase-lock loop (pll) timing source, interrupt controller for both on-chip and external peripherals, con guration and operation of chip selects, and the sdram controller. contents part ii contains the following chapters: chapter 6, ?sim overview,? describes the sim programming model, bus arbitration, and system-protection functions for the mcf5307. chapter 7, ?phase-locked loop (pll),? describes con guration and operation of the pll module. it describes in detail the registers and signals that support the pll implementation. chapter 8, ?i2c module,? describes the mcf5307 i2c module, including i2c protocol, clock synchronization, and the registers in the i2c programing model. it also provides extensive programming examples. chapter 9, ?interrupt controller,? describes operation of the interrupt controller portion of the sim. includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. chapter 10, ?chip-select module,? describes the mcf5307 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers. chapter 11, ?synchronous/asynchronous dram controller module,? describes con guration and operation of the synchronous/asynchronous dram controller component of the sim. it begins with a general description and brief glossary, and f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ii-ii mcf5307 users manual includes a description of signals involved in dram operations. the remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. suggested reading the following literature may be helpful with respect to the topics in part ii: the i 2 c bus speci?ation, version 2.1 (january 2000) acronyms and abbreviations table ii-i contains acronyms and abbreviations are used in part ii. table ii-i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion bdm background debug mode codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing edo extended data output (dram) fifo first-in, rst-out gpio i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ipl interrupt priority level jedec joint electron device engineering council lifo last-in, rst-out lru least recently used lsb least-signi cant byte lsb least-signi cant bit mbar memory base address register msb most-signi cant byte msb most-signi cant bit mux multiplex f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
part ii. system integration module (sim) ii-iii nop no operation pclk processor clock pll phase-locked loop por power-on reset rx receive sim system integration module sof start of frame tap test access port ttl transistor-to-transistor logic tx transmit uart universal asynchronous/synchronous receiver transmitter table ii-i. acronyms and abbreviated terms (continued) term meaning f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ii-iv mcf5307 users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-1 chapter 6 sim overview this chapter provides detailed operation information regarding the system integration module (sim). it describes the sim programming model, bus arbitration, and system-protection functions for the mcf5307. 6.1 features the sim, shown in figure 6-1, provides overall control of the bus and serves as the interface between the coldfire core processor complex and the internal peripheral devices. figure 6-1. sim block diagram dram controller external bus interface system integration module (sim) 32-bit address bus 32-bit data bus interrupt controller pll clkin rsti rsto pclk x n cs [7:0] 88 8 8 10 icrs mbar imr csars cscrs csmrs irq [1,3,5,7] 4 dram controller outputs avr ipr irqpar swivr swsr sypcr rsr system control pll control pll base address mpark bus master park dmr0/1 dacr0/1 addr/cntrl mask dram control dcr parallel port pa r software watchdog tw o two uarts dma i 2 c module four channels general- purpose timers v3 coldfire processor complex bclko (to on-chip peripherals) control signals chip select module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-2 mcf5307 users manual features the following is a list of the key sim features: module base address register (mbar) ? base address location of all internal peripherals and sim resources ? address space masking to internal peripherals and sim resources phase-locked loop (pll) clock control register (pllcr) for cpu stop instruction ? control for turning off clocks to core and interrupt levels that turn clocks back on chapter 7, ?phase-locked loop (pll).? interrupt controller ? programmable interrupt level (1?7) for internal peripheral interrupts ? programmable priority level (0?3) within each interrupt level ? four external interrupts; one set to interrupt level 7; three others programmable to two interrupt levels see chapter 9, ?interrupt controller.? chip select module ? eight independent, user-programmable chip-select signals (cs [7:0]) that can interface with sram, prom, eprom, eeprom, flash, and peripherals ? address masking for 64-kbyte to 4-gbyte memory block sizes ? programmable wait states and port sizes ? external master access to chip selects see chapter 10, ?chip-select module.? system protection and reset status ? reset status indicating the cause of last reset ? software watchdog timer with programmable secondary bus monitor see section 6.2.4, ?software watchdog timer.? pin assignment register (par) con gures the parallel port. see section 6.2.9, ?pin assignment register (par).? bus arbitration ? default bus master park register (mpark) controls internal and external bus arbitration and enables display of internal accesses on the external bus for debugging ? supports several arbitration algorithms see section 6.2.10, ?bus arbitration control.? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-3 programming model 6.2 programming model the following sections describe the registers incorporated into the sim. 6.2.1 sim register memory map table 6-1 shows the memory map for the sim registers. the internal registers in the sim are memory-mapped registers offset from the mbar address pointer de ned in mbar[ba]. this supervisor-level register is described in section 6.2.2, ?module base address register (mbar).? because sim registers depend on the base address de ned in mbar[ba], mbar must be programmed before sim registers can be accessed. note: although external masters cannot access the mcf5307?s on-chip memories or mbar, they can access any of the sim memory map and peripheral registers, such as those belonging to the interrupt controller, chip-select module, uarts, timers, dma, and i 2 c. table 6-1. sim registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x000 reset status register (rsr) [p. 6-5] system protection control register (sypcr) [p. 6-8] software watchdog interrupt vector register (swivr) [p. 6-9] software watchdog service register (swsr) [p. 6-9] 0x004 pin assignment register (par) [p. 6-10] interrupt port assignment register (irqpar) [p. 9-7] reserved 0x008 pll control (pllcr) [p. 7-3] reserved 0x00c default bus master park register (mpark) [p. 6-11] reserved 0x010 0x03c reserved interrupt controller registers [p. 9-2] 0x040 interrupt pending register (ipr) [p. 9-6] 0x044 interrupt mask register (imr) [p. 9-6] 0x048 reserved autovector register (avr) [p. 9-5] interrupt control registers (icrs) [p. 9-3] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-4 mcf5307 users manual programming model 6.2.2 module base address register (mbar) the supervisor-level mbar, figure 6-2, speci es the base address and allowable access types for all internal peripherals. it is written with a movec instruction using the cpu address 0xc0f. (see the coldfire family programmers reference manual .) mbar can be read or written through the debug module as a read/write register, as described in chapter 5, ?debug support.? only the debug module can read mbar. the valid bit, mbar[v], is cleared at system reset to prevent incorrect references before mbar is written; other mbar bits are uninitialized at reset. to access internal peripherals, write mbar with the appropriate base address (ba) and set mbar[v] after system reset. all internal peripheral registers occupy a single relocatable memory block along 4-kbyte boundaries. if mbar[v] is set, mbar[ba] is compared to the upper 20 bits of the full 32-bit internal address to determine if an internal peripheral is being accessed. mbar masks speci c address spaces using the address space elds. attempts to access a masked address space generate an external bus access. addresses hitting overlapping memory spaces take the following priority: 1. mbar 2. sram and caches 3. chip select note: the mbar region must be mapped to non-cacheable space. 0x04c software watchdog timer (icr0) [p. 9-3] timer0 (icr1) [p. 9-3] timer1 (icr2) [p. 9-3] i 2 c (icr3) [p. 9-3] 0x050 uart0 (icr4) [p. 9-3] uart1 (icr5) [p. 9-3] dma0 (icr6) [p. 9-3] dma1 (icr7) [p. 9-3] 0x054 dma2 (icr8) [p. 9-3] dma3 (icr9) [p. 9-3] reserved 31 12 11 10 9 8 7 6 5 4 3 2 1 0 field ba wp am c/i sc sd uc ud v reset unde ned 0 r/w w (supervisor only); r/w through debug module (only the debug module can read mbar) address cpu + 0x0c0f figure 6-2. module base address register (mbar) table 6-1. sim registers (continued) mbar offset [31:24] [23:16] [15:8] [7:0] a ttr ib ute m as k bi ts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-5 programming model table 6-2 describes mbar elds. the following example shows how to set the mbar to location 0x1000_0000 using the d0 register. setting mbar[v] validates the mbar location. this example assumes all accesses are valid: move.1 #0x10000001,do movec do,mbar 6.2.3 reset status register (rsr) the reset status register (rsr), figure 6-3, contains two status bits, hrst and swtr. reset control logic sets one of the bits depending on whether the last reset was caused by an external device asserting rsti (hrst = 1) or by the software watchdog timer (swtr = 1). only one rsr bit can be set at any time. if a reset occurs, reset control logic sets only the bit that indicates the cause of reset. table 6-2. mbar field descriptions bits field description 31 12 ba base address. de nes the base address for a 4-kbyte address range. 11 9 reserved, should be cleared. 8 wp write protect. mask bit for write cycles in the mbar-mapped register address range. 0 module address range is read/write. 1 module address range is read only. 7 reserved, should be cleared. 6 am alternate master mask. when am = 0 and an alternate master (external master or dma) accesses mbar-mapped registers, mbar[sc,sd,uc,ud] are ignored in address decoding. these elds mask address space, placing the mbar-mapped register in a speci c address space or spaces. 5 c/i mask cpu space and interrupt acknowledge cycles. 0 activates the corresponding mbar-mapped register 1 regular external bus access 4 sc setting masks supervisor code space in mbar address range 3 sd setting masks supervisor data space in mbar address range 2 uc setting masks user code space in mbar address range 1 ud setting masks user data space in mbar address range 0 v valid. determines whether mbar settings are valid. 0 mbar contents are invalid. 1 mbar contents are valid. 7654 0 field hrst swtr reset 1/0 0 1/0 0_0000 r/w read/write address mbar + 0x000 figure 6-3. reset status register (rsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-6 mcf5307 users manual programming model table 6-3 describes rsr elds. 6.2.4 software watchdog timer the software watchdog timer prevents system lockup should the software become trapped in loops with no controlled exit. the software watchdog timer can be enabled or disabled through sypcr[swe]. if enabled, the watchdog timer requires the periodic execution of a software watchdog servicing sequence. if this periodic servicing action does not occur, the timer times out, resulting in a watchdog timer irq or hardware reset with rst o driven low, as programmed by sypcr[swri]. if the timer times out and the software watchdog transfer acknowledge enable bit (sypcr[swta]) is set, a watchdog timer irq is asserted. note that the software watchdog timer iack cycle cannot be autovectored. if a software watchdog timer iack cycle has not occurred after another timeout, swt t a is asserted in an attempt to terminate the bus cycle and allow the iack cycle to proceed. the setting of sypcr[swtaval] indicates that the watchdog timer t a was asserted. figure 6-4 shows termination of a locked bus. table 6-3. rsr field descriptions bits name description 7 hrst hardware or system reset 1 an external device driving rsti caused the last reset. assertion of reset by an external device causes the core processor to take a reset exception. all registers in internal peripherals and the sim are reset. 6 reserved, should be cleared. 5 swtr software watchdog timer reset 1 the last reset was caused by the software watchdog timer. if sypcr[swri] = 1 and the software watchdog timer times out, a hardware reset occurs. 4 0 reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-7 programming model figure 6-4. mcf5307 embedded system recovery from unterminated access when the watchdog timer times out and sypcr[swri] is programmed for a software reset, an internal reset is asserted and rsr[swtr] is set. to prevent the watchdog timer from interrupting or resetting, the swsr must be serviced by performing the following sequence: 1. write 0x55 to swsr. 2. write 0xaa to the swsr. both writes must occur in order before the timeout, but any number of instructions or swsr accesses can be executed between the two writes. this order allows interrupts and exceptions to occur, if necessary, between the two writes. caution should be exercised when changing sypcr values after the software watchdog timer has been enabled with the setting of sypcr[swe], because it is dif cult to determine the state of the watchdog timer while it is running. the countdown value is constantly compared with the timeout period speci ed by sypcr[swp,swt]. therefore, altering swp and swt improperly causes unpredictable processor behavior. the following steps must be taken to change swp or swt: code enables software watchdog timer interrupt and 1. watchdog timer times out due to unterminated bus 2. watchdog timer interrupt cannot be serviced due to hung bus cycle. wait for another timeout before setting sypcr[swta]. timeout timeout software swta functionality by writing sypcr. sypcr[swtaval] 1 watchdog timer 3. t a held until another bus cycle starts problem: note: the watchdog timer irq should be set to the highest level in the system. 1 swtaval is set if watchdog timer t a is asserted. software watchdog timer irq watchdog timer t a iack cycle code in the watchdog timer interrupt handler polls sypcr[swtaval] to determine if swt t a was needed. if so, execute code to identify bad address. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-8 mcf5307 users manual programming model 1. disable the software watchdog timer by clearing sypcr[swe]. 2. reset the counter by writing 0x55 and then 0xaa to swsr. 3. update sypcr[swt,swp]. 4. reenable the watchdog timer by setting sypcr[swe]. this can be done in step 3. 6.2.5 system protection control register (sypcr) the sypcr, figure 6-5, controls the software watchdog timer, timeout periods, and software watchdog timer transfer acknowledge. the sypcr can be read at any time, but can be written only if a software watchdog timer irq is not pending. at system reset, the software watchdog timer is disabled. table 6-4 describes sypcr elds. 76543210 field swe swri swp swt swta swtaval reset 0000_0000 r/w r/w address mbar + 0x01 figure 6-5. system protection control register (sypcr) table 6-4. sypcr field descriptions bits name description 7 swe software watchdog timer enable 0 software watchdog timer disabled 1 software watchdog timer enabled 6 swri software watchdog reset/interrupt select 0 if a timeout occurs, the watchdog timer generates an interrupt to the core processor at the level programmed into icr0[il]. 1 the software watchdog timer causes soft reset to be asserted for all modules of the part except for the pll (reset mode selects, such as pp_reset_sel or chip-select settings, should not change). 5 swp software watchdog prescaler. this bit interacts with sypcr[swt]. 0 software watchdog timer clock not prescaled. 1 software watchdog timer clock prescaled by 8192. 4 3 swt software watchdog timing delay. swt and swp select the timeout period for the watchdog timer. at system reset, the software watchdog timer is set to the minimum timeout period. swp = 0 00 2 9 /system frequency 01 2 11 /system frequency 10 2 13 /system frequency 11 2 15 /system frequency swp = 1 00 2 22 /system frequency 01 2 24 /system frequency 10 2 26 /system frequency 11 2 28 /system frequency note that if swp and swt are modi ed to select a new software timeout, the software service sequence must be performed (0x55 followed by 0xaa written to the swsr) before the new timeout period takes effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-9 programming model 6.2.6 software watchdog interrupt vector register (swivr) the swivr, shown in figure 6-6, contains the 8-bit interrupt vector (swiv) that the sim returns during an interrupt-acknowledge cycle in response to a software watchdog timer-generated interrupt. swivr is set to the uninitialized vector 0x0f at system reset. note that the software watchdog interrupt cannot be autovectored. 6.2.7 software watchdog service register (swsr) the swsr, shown in figure 6-7, is where the software watchdog timer servicing sequence should be written. to prevent a watchdog timer timeout, the software service sequence must be performed (0x55 followed by 0xaa written to the swsr). both writes must be performed in order before the timeout, but any number of instructions or accesses to the swsr can be executed between the two writes. if the timer has timed out, writing to swsr does not cancel the interrupt (that is, ipr[swt] remains set). the interrupt is cancelled (and swt is cleared) automatically when the iack cycle is run. 2 swta software watchdog transfer acknowledge enable 0 swta transfer acknowledge disabled 1 swta asserts transfer acknowledge enabled. after one timeout period of the unacknowledged assertion of the software watchdog timer interrupt, the software watchdog transfer acknowledge asserts, which allows the watchdog timer to terminate a bus cycle and allow the iack to occur. 1 swtaval software watchdog transfer acknowledge valid 0 swta transfer acknowledge has not occurred. 1 swta transfer acknowledge has occurred. write a 1 to clear this ag bit. 7 0 field swiv reset 0000_1111 r/w supervisor write only address mbar + 0x002 figure 6-6. software watchdog interrupt vector register (swivr) 7 0 field swsr reset undetermined r/w supervisor write only address mbar + 0x003 figure 6-7. software watchdog service register (swsr) table 6-4. sypcr field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-10 mcf5307 users manual programming model 6.2.8 pll clock control for cpu stop instruction the sim contains the pll clock control register, which is described in detail in section 7.2.4, ?pll control register (pllcr).? pllcr[enbstop,pllipl] are signi cant to the operation of the sim, and are described as follows: pllcr[enbstop] must be set for the coldfire cpu stop instruction to be acknowledged. this bit is cleared at reset and must be set for the mcf5307 to enter low-power modes. the cpu stop instruction stops only clocks to the core processor. all internal modules remain clocked and can generate interrupts to restart the coldfire core. for example, the on-chip timer can be used to interrupt the processor after a given timer countdown. pllcr[pllipl] determines the minimum level at which an interrupt (decoded as an interrupt priority level or ipl) must occur to awaken the pll. the pll then turns clocks back on to the core processor and interrupt exception processing takes place. table 6-5 describes pllipl settings to be compared against the interrupt ranges that awaken the core processor from a cpu stop instruction. 6.2.9 pin assignment register (par) the pin assignment register (par), figure 6-8, allows the selection of pin assignments. table 6-5. pllipl settings pllipl description 000 any interrupts can wake core 001 interrupts 2 7 010 interrupts 3 7 011 interrupts 4 7 100 interrupts 5 7 101 interrupts 6 7 110 interrupt 7 only 111 no interrupts can wake core 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field par15 par14 par13 par12 par11 par10 par9 par8 par7 par6 par5 par4 par3 par2 par1 par0 pa r n = 0 pp15 pp14 pp13 pp12 pp11 pp10 pp9 pp8 pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 pa r n = 1 a31 a30 a29 a28 a27 a26 a25 a24 tip dreq0 dreq1 tm2 tm1 tm0 tt1 tt0 reset determined by driving d4/addr_config with a 1 or 0 when rsti negates. the system is con gured as pp[15:0] if d4 is low; otherwise alternate pin functions selected by par = 1 are used. r/w r/w address address mbar + 0x004 figure 6-8. pin assignment register (par) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-11 programming model 6.2.10 bus arbitration control this section describes the bus arbitration register and the four arbitration schemes. 6.2.10.1 default bus master park register (mpark) the mpark, shown in figure 6-9, determines the default bus master arbitration between internal transfers (core and dma module) and between internal and external transfers to internal resources. this arbitration is needed because external masters can access internal registers within the mcf5307 peripherals. figure 6-9. default bus master register (mpark) table 6-6 describes mpark bits. 765432 0 field park iarbctrl earbctrl showdata bcr24bit reset 0000_0000 r/w r/w address mbar + 0x0c table 6-6. mpark field descriptions bits name description 7 6 park park. indicates the arbitration priority of internal transfers among mcf5307 resources. 00 round-robin between dma and coldfire core 01 park on master coldfire core 10 park on master dma module 11 park on current master use of this eld is described in detail in section 6.2.10.1.1, arbitration for internally generated transfers (mpark[park]). 5 iarbctrl internal bus arbitration control. controls external device access to the mcf5307 internal bus. 0 arbitration disabled (single-master system) 1 arbitration enabled. iarbctrl must be set if external masters are using internal resources like the dram controller or chip selects. use of this bit depends on whether the system has single or multiple masters, as follows: in a single-master system, iarbctrl should stay cleared, disabling internal arbitration by external masters. in this scenario, mpark[park] applies only to priority of internal masters over one another. note that the internal dma (master 3) has priority over the coldfire core (master 2), if internal dma bandwidth is at its maximum (bwc = 000). in multiple master systems that expect to use internal resources like the dram controller or chip selects, internal arbitration should be enabled. the external master defaults to the highest priority internal master anytime bg is negated. 4 earbctrl external bus arbitration control. enables internal register memory space to external bus arbitration. internal registers are those accessed at offsets to the mbar. these include the sim, dma, chip selects, timers, uarts, i 2 c, and parallel port registers. these registers do not include the mbar; only the core can access the mbar. 0 arbitration disabled 1 arbitration enabled the use of this eld is described in detail in section 6.2.10.1.2, arbitration between internal and external masters for accessing internal resources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-12 mcf5307 users manual programming model 6.2.10.1.1 arbitration for internally generated transfers (mpark[park]) mpark[park] prioritizes internal transfers, which can be initiated by the core and the on-chip dma module, which contains all four dma channels. priority among the four dma channels in the module is determined by the bwc bits in their respective dma control registers (see chapter 12, ?dma controller module?). the four arbitration schemes for internally generated transfers are described as follows: round-robin scheme (park = 00)?figure 6-10 shows round-robin arbitration between the core and dma module. bus mastership alternates between the core and dma module. figure 6-10. round robin arbitration (park = 00) the dma module presents only the highest-priority dma request, and bus mastership alternates between the core and dma channel as long as both are requesting bus mastership. section 12.5.4.1, ?external request and acknowledge operation,? includes a timing diagram showing a lower-priority dma transfer. when the processor is initialized, the core has rst priority. if dma channels 0 and 1 (both set to bwc = 010) assert an internal bus request during a core-generated bus transfer, dma channel 0 would gain bus mastership next. however, if the core requests the bus during this dma transfer, bus mastership returns to the core rather than being granted to dma channel 1. 3 showdata enable internal register data bus to be driven on external bus. earbctrl must be set for this function to work. section 6.2.10.1.2, arbitration between internal and external masters for accessing internal resources, describes the proper use of showdata. 0 do not drive internal register data bus values to external bus. 1 drive internal register data bus values to external bus. 2 1 reserved, should be cleared. 0 bcr24bit controls the bcr and address mapping for dma. allows the bcr to be used as a 24-bit register. chapter 12, dma controller module, describes the bcrs. 0 dma bcrs function as 16-bit counters. 1 dma bcrs function as 24-bit counters. table 6-6. mpark field descriptions (continued) bits name description core channel 0 channel 1 channel 2 channel 3 dma module internal bus mastership (alternates between core and dma module) 1st 2nd 3rd 4th 5th f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-13 programming model note that the internal dma has higher priority than the core if the internal dma has its bandwidth bwc bits set to 000 (maximum bandwidth). park on master core priority (park = 01)?the core retains bus mastership as long as it needs it. after it negates its internal bus request, the core does not have to rearbitrate for the bus unless the dma module has requested the bus when it is idle. the dma module can be granted bus mastership only when the core is not asserting its bus request. see figure 6-11. figure 6-11. park on master core priority (park = 01) park on master dma priority (park = 10)?the dma module retains bus mastership as long as it needs it. after it negates its internal bus request, the dma module does not have to rearbitrate for the bus unless the core has requested the bus when it is idle. the core can be granted bus mastership only when the dma module is not asserting its bus request. see figure 6-12. figure 6-12. park on dma module priority (park = 10) core dma module core br asserted core br negated dma module br negated dma module br negated/asserted core br negated dma module br asserted core dma module core br asserted dma br negated core br negated dma module br negated dma module br asserted core br negated/asserted f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-14 mcf5307 users manual programming model park on current master priority (park = 11)?the current bus master retains mastership as long as it needs the bus. the other device can become the bus master only when the bus is idle. for example, if the core is bus master out of reset, it retains mastership as long as it needs the bus. it loses mastership only when it negates its bus request signal and the dma asserts its internal bus request signal. at this point the dma module is the bus master, and retains bus mastership as long as it needs the bus. see figure 6-13. figure 6-13. park on current master priority (park = 01) 6.2.10.1.2 arbitration between internal and external masters for accessing internal resources if an external device is programmed to access internal mcf5307 resources (earbctrl = 1), the external device can gain bus mastership only when bg is negated. this means neither the core nor the dma controller can access the external bus until the external device asserts bg . after the external master nishes its bus transfer and asserts bg , the core has priority on the next available bus cycle regardless of the value of park. thus if the core asserts its internal bus request on this rst bus cycle, it executes a bus cycle even if park indicates the dma should have priority. then, after the bus transfer, the park scheme returns to programmed functioning and the dma is given bus mastership. note: in all arbitration modes, if bg is negated, the external master interface has highest priority. in this case, the coldfire core has second-highest priority, until the internal bus grant is asserted. in a single-master system, the setting of earbctrl does not affect arbitration performance. typically, bg is tied low and the mcf5307 always owns the external bus and internal register transfers are already shown on the external bus. in a system where mcf5307 is the only master, this bit may remain cleared. if the system needs external visibility of the data bus values during internal register transfers for system debugging, both earbctrl and showdata must be set. note that when an internal register transfer is driven externally, t a becomes an output, which is asserted (normally an input) to prevent external devices and core dma module core br asserted dma module br negated core br negated dma module br negated dma module br asserted core br negated core br negated dma module br negated dma module br asserted core br asserted core br asserted dma module br asserted f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 6. sim overview 6-15 programming model memories from responding to internal register transfers that go to the external bus. the as signal and all chip-select-related strobe signals are not asserted. do not immediately follow a cycle in which showdata is set with a cycle using fast termination. in multiple-master systems, disabling arbitration with earbctrl allows performance improvement because internal register bus transfer cycles do not interfere with the external bus. having internal transfers go external may affect performance in two ways: ? if the internal device does not control the bus immediately, the core stalls until it wins arbitration of the external bus. ? if the core wins arbitration instantly, it may kick the external master off of the external bus unnecessarily for a transfer that did not need the external bus. for debug, where this performance penalty is not a concern, setting earbctrl and showdata provides external visibility of the internal bus cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6-16 mcf5307 users manual programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 7. phase-locked loop (pll) 7-1 chapter 7 phase-locked loop (pll) this chapter describes con guration and operation of the phase-locked loop (pll) module. it describes in detail the registers and signals that support the pll implementation. 7.1 overview the basic features of the mcf5307 pll implementation are as follows: the pll locks to the clock input (clkin) frequency. it provides a processor clock (pclk) that is twice the input clock frequency and a programmable system bus clock output (bclko) that is 1/2, 1/3, or 1/4 the pclk frequency. a buffered processor status clock (pstclk) is equal to the pclk frequency, as indicated in figure 7-1. this signal is made available for system development. the pll module has the following three modes of operation: reset mode?in reset mode, the core/bus frequency ratio and other con guration information is sampled. at reset, the pll asserts the reset out signal, rst o . normal mode?during normal operations, the divide ratio is programmed at reset and is clock-multiplied to provide a maximum frequency of 90 mhz reduced-power mode?in reduced-power mode, the high-speed processor core clocks are turned off without losing the register contents so that the system can be reenabled by an unmasked interrupt or reset. figure 7-1 shows the frequency relationships of pll module clock signals. z figure 7-1. pll module block diagram pll clkin rsti divide bclko divide[1:0] freq[1:0] rsto pstclk pclk clkin x 4 by 2 divide by 2, 3, or 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-2 mcf5307 users manual pll operation 7.1.1 pll:pclk ratios the speci cations for the clocks in the pll module are summarized in table 0-1. 7.2 pll operation the following sections provide detailed information about the three pll modes. 7.2.1 reset/initialization the pll receives rsti as an input directly from the pin. additionally, signals are multiplexed with d[3:0]/freq[1:0]:divide[1:0] while rsti is asserted. these signals are sampled during reset and registered by the pll on the negation of rsti to provide initialization information. freq[1:0] and divide[1:0] are used by the pll to select the clkin frequency range and set the clkin/pclk ratio, respectively. 7.2.2 normal mode pclk is divided to create the system bus clock, bclko. at reset, the logic level of divide[1:0]/d[1:0] determines the bclko divisor. the bus clock can be 1/2, 1/3, or 1/4 of the pclk frequency. 7.2.3 reduced-power mode the pclk can be turned off in a predictable manner to conserve system power. to allow fast restart of the mcf5307 processor core, the pll continues to operate at the frequency con gured at reset. pclk is disabled using the cpu stop instruction and resumes normal operation on interrupt, as described in section 7.2.4, ?pll control register (pllcr).? table 0-1. pll clock specifications symbol description frequency pll lock time 2.2 ms with clkin running at 45 mhz clkin input clock 16.67 mhz 45 mhz pclk internal processor clock 33.34 mhz 90 mhz (clkin x 2) pstclk processor status clock 33.34 mhz 90 mhz (clkin x 2) bclko output clock 16.67 mhz 45 mhz 11.11 mhz 30 mhz 8.24 mhz 22.5 mhz bclko/pclk ratio 1/2 1/3 1/4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 7. phase-locked loop (pll) 7-3 pll port list 7.2.4 pll control register (pllcr) the pll control register (pllcr), figure 7-2, provides control over the pll. table 7-1 describes pllcr bits. 7.3 pll port list table 7-2 describes pll module inputs. 76543210 field enbstop pllipl reset 0000_0000 r/w r/w address mbar + 0x08 figure 7-2. pll control register (pllcr) table 7-1. pllcr field descriptions bit name description 7 enbstop enable cpu stop instruction. must be set for the coldfire cpu stop instruction to be acknowledged. cleared at reset and must be subsequently set for the processor to enter low-power modes. only clocks to the core are turned off because of the cpu stop instruction. internal modules remain clocked and can generate interrupts to restart the coldfire core. 0 disable cpu stop 1 enable cpu stop; stop instruction turns off clocks to the coldfire core. 6 4 pllipl pll interrupt priority level to wake up from cpu stop. determines the minimum level an interrupt (decoded as an interrupt priority level) must be to waken the pll. the pll then turns clocks back on to the core processor and interrupt exception processing occurs. 000 any interrupts can wake core 001 interrupts 2 7 010 interrupts 3 7 011 interrupts 4 7 100 interrupts 5 7 101 interrupts 6 7 110 interrupt 7 only 111 no interrupts can wake core. any reset, including a watchdog reset, can wake the core. no pll phase lock time is required. 3 0 reserved, should be cleared. table 7-2. pll module input signals signal description clkin input clock to the pll. input frequency must not be changed during operation. changes are recognized only at reset. rsti active-low asynchronous input that, when asserted, indicates pll is to enter reset mode. as long as rsti is asserted, the pll is held in reset and does not begin to lock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-4 mcf5307 users manual timing relationships table 7-3 describes pll module outputs. 7.4 timing relationships the mcf5307 uses clkin and bclko, which is generated by the pll and may be used as the bus timing reference for external devices. the mcf5307 bclko frequency can be 1/2, 1/3, or 1/4 the processor clock. in this document, bus timings are referenced from bclko. furthermore, depending on the user con guration, the bclko-to-processor clock ratio may differ from the clkin-to-processor clock ratio. 7.4.1 pclk, pstclk, and bclko figure 7-3 shows the frequency relationships between pclk, pstclk,clkin, and the three possible versions of bclko. this gure does not show the skew between clkin and pclk, pstclk, and bclko. pstclk is equal to frequency of pclk. similarly, the skew between pclk and bclko is unspeci ed. freq[1:0] input bus indicating the clkin frequency range. freq[1:0] are multiplexed with d[3:2] and are sampled while rsti is asserted. freq[1:0] must be correctly set for proper operation. these signals do not affect clkin frequency but are required to set up the analog pll to handle the input clock frequency. 00 16.6 27.999 mhz 01 28 38.999 mhz 10 39 45 mhz 11 not used divide[1:0] the mcf5307 samples clock ratio encodings on the lower data bits of the bus to determine the clkin-to-processor clock ratio. d[1:0]/divide[1:0] support the divide-ratio combinations. 00 1/4 01 not used 10 1/2 11 1/3 table 7-3. pll module output signals output description bclko this bus clock output provides a divided version of the processor clock frequency, determined by divide[1:0]. pstclk provides a buffered processor status clock at 2x the clkin frequency. pstclk is a delayed version of pclk. see section 7.4.1, pclk, pstclk, and bclko, and figure 7-1. rst o this output provides an external reset for peripheral devices. table 7-2. pll module input signals signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 7. phase-locked loop (pll) 7-5 timing relationships figure 7-3. clkin, pclk, pstclk, and bclko timing 7.4.2 rsti timing figure 7-4 shows pll timing during reset. as shown, rsti must be asserted for at least 80 clkin cycles to give the mcf5307 time to begin its initialization sequence. at this time, the con guration pins should be asserted (d[3:2] for freq[1:0] and d[1:0] for divide[1:0]), meeting the minimum setup and hold times to rsti given in chapter 20, ?electrical speci cations.? on the rising edge of bclko before the rising edge of rsti , the data on d[7:0] is latched and the pll begins ramping to its nal operating frequency. during this ramp and lock time, bclko and pstclk are held low. the pll locks in about 2.2 ms with a 45-mhz clkin, at which time bclkoand pstclk begin normal operation in the speci ed mode. the pll requires 100,000 clkin cycles to guarantee pll lock. to allow for reset of external peripherals requiring a clock source, rst o remains asserted for a number of bclko cycles, as shown in figure 7-4. pclk bclko (/2) bclko (/3) bclko (/4) clkin pstclk note: the clock signals are shown with edges aligned to show frequency relationships only. actual signal edges have some skew between them. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
7-6 mcf5307 users manual pll power supply filter circuit figure 7-4. reset and initialization timing 7.5 pll power supply filter circuit to ensure pll stability, the power supply to the pll power pin should be ltered using a circuit similar to the one in figure 7-5. the circuit should be placed as close as possible to the pll power pin to ensure maximum noise ltering. figure 7-5. pll power supply filter circuit 100k clkin >80 clkin bclko clkin rsti bclko bclko pstclk rsto 30 bclko 20 bclko 15 bclko (1/2 mode) (1/3 mode) (1/4 mode) d[7:0] cycle lock time d[7:0] latched 10 ? 10 f 0.1 f pll power pin vdd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 8. i 2 c module 8-1 chapter 8 i 2 c module this chapter describes the mcf5307 i 2 c module, including i 2 c protocol, clock synchronization, and the registers in the i 2 c programing model. it also provides extensive programming examples. 8.1 overview i 2 c is a two-wire, bidirectional serial bus that provides a simple, ef cient method of data exchange, minimizing the interconnection between devices. this bus is suitable for applications requiring occasional communications over a short distance between many devices. the exible i 2 c allows additional devices to be connected to the bus for expansion and system development. the i 2 c system is a true multiple-master bus including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. this feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. 8.2 interface features the i 2 c module has the following key features: compatibility with i 2 c bus standard support for 3.3-v tolerant devices multiple-master operation software-programmable for one of 64 different serial clock frequencies software-selectable acknowledge bit interrupt-driven, byte-by-byte data transfer arbitration-lost interrupt with automatic mode switching from master to slave calling address identi cation interrupt start and stop signal generation/detection repeated start signal generation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-2 mcf5307 users manual interface features acknowledge bit generation/detection bus-busy detection figure 8-1 is a block diagram of the i 2 c module. figure 8-1. i 2 c module block diagram figure 8-1 shows the relationships of the i 2 c registers, listed below: i 2 c address register (iadr) i 2 c frequency divider register (ifdr) i 2 c control register (i2cr) i 2 c status register (i2sr) i 2 c data i/o register (i2dr) these registers are described in section 8.5, ?programming model.? address compare in/out data shift start, stop, input sync clock control registers and coldfire interface address decode i 2 c address data mux sda scl address irq data and arbitration control register internal bus register (iadr) i 2 c frequency divider register (ifdr) i 2 c data i/o register (i2dr) i 2 c status register (i2sr) i 2 c control register (i2cr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 8. i 2 c module 8-3 i 2 c system con?uration 8.3 i 2 c system con?uration the i 2 c module uses a serial data line (sda) and a serial clock line (scl) for data transfer. for i 2 c compliance, all devices connected to these two signals must have open drain or open collector outputs. (there is no such requirement for inputs.) the logic and function is exercised on both lines with external pull-up resistors. out of reset, the i 2 c default is as slave receiver. thus, when not programmed to be a master or responding to a slave transmit address, the i 2 c module should return to the default slave receiver state. see section 8.6.1, ?initialization sequence,? for exceptions. note: the i 2 c module is designed to be compatible with the philips i 2 c bus protocol. for information on system con guration, protocol, and restrictions, see the i 2 c bus speci?ation, version 2.1 . 8.4 i 2 c protocol normally, a standard communication is composed of the following parts: 1. start signal?when no other device is bus master (both scl and sda lines are at logic high), a device can initiate communication by sending a start signal (see a in figure 8-2). a start signal is de ned as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. figure 8-2. i 2 c standard communication protocol 2. slave address transmission?the master sends the slave address in the rst byte after the start signal (b). after the seven-bit calling address, it sends the r/w bit (c), which tells the slave data transfer direction. each slave must have a unique address. an i 2 c master must not transmit an address that is the same as its slave address; it cannot be master and slave at the same time. 12345678 12345678 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address r/w ack bit data byte no ack bit stop signal lsb msb lsb msb sda scl start signal a b d c e f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-4 mcf5307 users manual i 2 c protocol the slave whose address matches that sent by the master pulls sda low at the ninth clock (d) to return an acknowledge bit. 3. data transfer?when successful slave addressing is achieved, the data transfer can proceed (e) on a byte-by-byte basis in the direction speci ed by the r/w bit sent by the calling master. data can be changed only while scl is low and must be held stable while scl is high, as figure 8-2 shows. scl is pulsed once for each data bit, with the msb being sent rst. the receiving device must acknowledge each byte by pulling sda low at the ninth clock; therefore, a data byte transfer takes nine clock pulses. if it does not acknowledge the master, the slave receiver must leave sda high. the master can then generate a stop signal to abort the data transfer or generate a start signal (repeated start, shown in figure 8-3) to start a new calling sequence. if the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave. the slave releases sda for the master to generate a stop or start signal. 4. stop signal?the master can terminate communication by generating a stop signal to free the bus. a stop signal is de ned as a low-to-high transition of sda while scl is at logical high (f). note that a master can generate a stop even if the slave has made an acknowledgment, at which point the slave must release the bus. instead of signalling a stop, the master can repeat the start signal, followed by a calling command, (a in figure 8-3). a repeated start occurs when a start signal is generated without rst generating a stop signal to end the communication. figure 8-3. repeated start the master uses a repeated start to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 8.4.1 arbitration procedure if multiple devices simultaneously request the bus, the bus clock is determined by a synchronization procedure in which the low period equals the longest clock-low period among the devices and the high period equals the shortest. a data arbitration procedure scl 1234567 8 1 2 5 678 34 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w 99 xx new calling address r/w no stop ack bit stop signal repeated start signal ack bit r/w calling address start sda msb lsb msb lsb signal a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 8. i 2 c module 8-5 i 2 c protocol determines the relative priority of competing devices. a device loses arbitration if it sends logic high while another sends logic low; it immediately switches to slave-receive mode and stops driving sda. in this case, the transition from master to slave mode does not generate a stop condition. meanwhile, hardware sets i2sr[ial] to indicate loss of arbitration. 8.4.2 clock synchronization because wire-and logic is used, a high-to-low transition on scl affects devices connected to the bus. devices start counting their low period when the master drives scl low. when a device clock goes low, it holds scl low until the clock high state is reached. however, the low-to-high change in this device clock may not change the state of scl if another device clock is still in its low period. therefore, the device with the longest low period holds the synchronized clock scl low. devices with shorter low periods enter a high wait state during this time (see figure 8-4). when all devices involved have counted off their low period, the synchronized clock scl is released and pulled high. there is then no difference between device clocks and the state of scl, so all of the devices start counting their high periods. the rst device to complete its high period pulls scl low again. figure 8-4. synchronized clock scl 8.4.3 handshaking the clock synchronization mechanism can be used as a handshake in data transfers. slave devices can hold scl low after completing one byte transfer (9 bits). in such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases scl. 8.4.4 clock stretching slaves can use the clock synchronization mechanism to slow down the transfer bit rate. after the master has driven scl low, the slave can drive scl low for the required period and then release it. if the slave scl low period is longer than the master scl low period, the resulting scl bus signal low period is stretched. internal counter reset scl1 scl2 scl wait start counting high period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-6 mcf5307 users manual programming model 8.5 programming model table 8-1 lists the con guration registers used in the i 2 c interface. note: external masters cannot access the mcf5307?s on-chip memories or mbar, but can access any i 2 c module register. 8.5.1 i 2 c address register (iadr) the iadr holds the address the i 2 c responds to when addressed as a slave. note that it is not the address sent on the bus during the address transfer. table 8-2 describes iadr elds. table 8-1. i 2 c interface memory map mbar offset [31:24] [23:16] [15:8] [7:0] 0x280 i 2 c address register (iadr) [p. 8-6] reserved 0x284 i 2 c frequency divider register (ifdr) [p. 8-7] reserved 0x288 i 2 c control register (i2cr) [p. 8-8] reserved 0x28c i 2 c status register (i2sr) [p. 8-9] reserved 0x290 i 2 c data i/o register (i2dr) [p. 8-10] reserved 76543210 field adr reset 0000_0000 r/w read/write address mbar + 0x280 figure 8-5. i 2 c address register (iadr) table 8-2. i 2 c address register field descriptions bits name description 7 1 adr slave address. contains the speci c slave address to be used by the i 2 c module. slave mode is the default i 2 c mode for an address match on the bus. 0 reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 8. i 2 c module 8-7 programming model 8.5.2 i 2 c frequency divider register (ifdr) the ifdr, figure 8-6, provides a programmable prescaler to con gure the clock for bit-rate selection. table 8-3 describes ifdr[ic]. 76543210 field ic reset 0000_0000 r/w read/write address mbar + 0x284 figure 8-6. i 2 c frequency divider register (ifdr) table 8-3. ifdr field descriptions bits name description 7 6 reserved, should be cleared. 5 0ic i 2 c clock rate. prescales the clock for bit-rate selection. due to potentially slow scl and sda rise and fall times, bus signals are sampled at the prescaler frequency. the serial bit clock frequency is equal to bclk0 divided by the divider shown below. note that ic can be changed anywhere in a program. ic divider ic divider ic divider ic divider 0x00 28 0x10 288 0x20 20 0x30 160 0x01 30 0x11 320 0x21 22 0x31 192 0x02 34 0x12 384 0x22 24 0x32 224 0x03 40 0x13 480 0x23 26 0x33 256 0x04 44 0x14 576 0x24 28 0x34 320 0x05 48 0x15 640 0x25 32 0x35 384 0x06 56 0x16 768 0x26 36 0x36 448 0x07 68 0x17 960 0x27 40 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88 0x19 1280 0x29 56 0x39 768 0x0a 104 0x1a 1536 0x2a 64 0x3a 896 0x0b 128 0x1b 1920 0x2b 72 0x3b 1024 0x0c 144 0x1c 2304 0x2c 80 0x3c 1280 0x0d 160 0x1d 2560 0x2d 96 0x3d 1536 0x0e 192 0x1e 3072 0x2e 112 0x3e 1792 0x0f 240 0x1f 3840 0x2f 128 0x3f 2048 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-8 mcf5307 users manual programming model 8.5.3 i 2 c control register (i2cr) the i2cr is used to enable the i 2 c module and the i 2 c interrupt. it also contains bits that govern operation as a slave or a master. table 8-4 describes i2cr elds. 76543210 field ien iien msta mtx txak rsta reset 0000_0000 r/w read/write address mbar + 0x288 figure 8-7. i 2 c control register (i2cr) table 8-4. i2cr field descriptions bits name description 7 ien i 2 c enable. controls the software reset of the entire i 2 c module. if the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next start condition is detected. master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the current master or the i 2 c module to lose arbitration, after which bus operation returns to normal. 0 the module is disabled, but registers can still be accessed. 1 the i 2 c module is enabled. this bit must be set before any other i2cr bits have any effect. 6 iien i 2 c interrupt enable. 0 i 2 c module interrupts are disabled, but currently pending interrupt condition are not cleared. 1 i 2 c module interrupts are enabled. an i 2 c interrupt occurs if i2sr[iif] is also set. 5 msta master/slave mode select bit. if the master loses arbitration, msta is cleared without generating a stop signal. 0 slave mode. changing msta from 1 to 0 generates a stop and selects slave mode. 1 master mode. changing msta from 0 to 1 signals a start on the bus and selects master mode. 4 mtx transmit/receive mode select bit. selects the direction of master and slave transfers. 0 receive 1 transmit. when a slave is addressed, software should set mtx according to i2sr[srw]. in master mode, mtx should be set according to the type of transfer required. therefore, for address cycles, mtx is always 1. 3 txak transmit acknowledge enable. speci es the value driven onto sda during acknowledge cycles for both master and slave receivers. note that writing txak applies only when the i 2 c bus is a receiver. 0 an acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. 1 no acknowledge signal response is sent (that is, acknowledge bit = 1). 2 rsta repeat start. always read as 0. attempting a repeat start without bus mastership causes loss of arbitration. 0 no repeat start 1 generates a repeated start condition. 1 0 reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 8. i 2 c module 8-9 programming model 8.5.4 i 2 c status register (i2sr) this i2sr contains bits that indicate transaction direction and status. table 8-5 describes i2sr elds. 76543210 field icf iaas ibb ial srw iif rxak reset 1000_0001 r/w r r/w r r/w r address mbar + 0x28c figure 8-8. i 2 cr status register (i2sr) table 8-5. i2sr field descriptions bits name description 7 icf data transferring bit. while one byte of data is transferred, icf is cleared. 0 transfer in progress 1 transfer complete. set by the falling edge of the ninth clock of a byte transfer. 6 iaas i 2 c addressed as a slave bit. the cpu is interrupted if i2cr[iien] is set. next, the cpu must check srw and set its tx/rx mode accordingly. writing to i2cr clears this bit. 0 not addressed. 1 addressed as a slave. set when its own address (iadr) matches the calling address. 5 ibb i 2 c bus busy bit. indicates the status of the bus. 0 bus is idle. if a stop signal is detected, ibb is cleared. 1 bus is busy. when start is detected, ibb is set. 4 ial arbitration lost. set by hardware in the following circumstances. (ial must be cleared by software by writing zero to it.) sda sampled low when the master drives high during an address or data-transmit cycle. sda sampled low when the master drives high during the acknowledge bit of a data-receive cycle. a start cycle is attempted when the bus is busy. a repeated start cycle is requested in slave mode. a stop condition is detected when the master did not request it. 3 reserved, should be cleared. 2 srw slave read/write. when iaas is set, srw indicates the value of the r/w command bit of the calling address sent from the master. srw is valid only when a complete transfer has occurred, no other transfers have been initiated, and the i 2 c module is a slave and has an address match. 0 slave receive, master writing to slave. 1 slave transmit, master reading from slave. 1 iif i 2 c interrupt. must be cleared by software by writing a zero to it in the interrupt routine. 0 no i 2 c interrupt pending 1 an interrupt is pending, which causes a processor interrupt request (if iien = 1). set when one of the following occurs: complete one byte transfer (set at the falling edge of the ninth clock) reception of a calling address that matches its own speci c address in slave-receive mode arbitration lost 0 rxak received acknowledge. the value of sda during the acknowledge bit of a bus cycle. 0 an acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 no acknowledge signal was detected at the ninth clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-10 mcf5307 users manual i 2 c programming examples 8.5.5 i 2 c data i/o register (i2dr) in master-receive mode, reading the i2dr, figure 8-9, allows a read to occur and initiates next byte data receiving. in slave mode, the same function is available after it is addressed. 8.6 i 2 c programming examples the following examples show programming for initialization, signalling start, post-transfer software response, signalling stop, and generating a repeated start. 8.6.1 initialization sequence before the interface can transfer serial data, registers must be initialized, as follows: 1. set ifdr[ic] to obtain scl frequency from the system bus clock. see section 8.5.2, ?i2c frequency divider register (ifdr).? 2. update the iadr to de ne its slave address. 3. set i2cr[ien] to enable the i 2 c bus interface system. 4. modify the i2cr to select master/slave mode, transmit/receive mode, and interrupt-enable or not. note: if ibsr[ibb] when the i 2 c bus module is enabled, execute the following code sequence before proceeding with normal initialization code. this issues a stop command to the slave device, placing it in idle state as if it were just power-cycled on. i2cr = 0x0 i2cr = 0xa dummy read of i2dr ibsr = 0x0 i2cr = 0x0 8.6.2 generation of start after completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. on a multiple-master bus system, ibsr[ibb] must be tested to determine whether the serial bus is free. if the bus is free (ibb = 0), the start signal 76543210 field d reset 0000_0000 r/w read/write address mbar + 0x290 figure 8-9. i 2 c data i/o register (i2dr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 8. i 2 c module 8-11 i 2 c programming examples and the rst byte (the slave address) can be sent. the data written to the data register comprises the address of the desired slave and the lsb indicates the transfer direction. the free time between a stop and the next start condition is built into the hardware that generates the start cycle. depending on the relative frequencies of the system clock and the scl period, it may be necessary to wait until the i 2 c is busy after writing the calling address to the i2dr before proceeding with the following instructions. the following example signals start and transmits the rst byte of data (slave address): chflag move.b i2sr,-(a0);check i2sr[mbb] btst.b #5, (a0)+ bne.s chflag;if i2sr[mbb] = 1, wait until it is clear txstart move.b i2cr,-(a0);set transmit mode bset.b #4,(a0) move.b (a0)+, i2cr move.b i2cr, -(a0);set master mode bset.b #5, (a0);generate start condition move.b (a0)+, i2cr move.b calling,-(a0);transmit the calling address, d0=r/w move.b (a0)+, i2dr ifree move.b i2sr,-(a0);check i2sr[mbb] ;if it is clear, wait until it is set. btst.b #5, (a0)+; beq.s ifree; 8.6.3 post-transfer software response sending or receiving a byte sets the i2sr[icf], which indicates one byte communication is nished. i2sr[iif] is also set. an interrupt is generated if the interrupt function is enabled during initialization by setting i2cr[iien]. software must rst clear iif in the interrupt routine. icf is cleared either by reading from i2dr in receive mode or by writing to i2dr in transmit mode. software can service the i 2 c i/o in the main program by monitoring iif if the interrupt function is disabled. polling should monitor iif rather than icf because that operation is different when arbitration is lost. when an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent. if master receive mode is required (i2dr[r/w], i2cr[mtx] should be toggled. during slave-mode address cycles (i2sr[iaas] = 1), i2sr[srw] is read to determine the direction of the next transfer. mtx is programmed accordingly. for slave-mode data cycles (iaas = 0), srw is invalid. mtx should be read to determine the current transfer direction. the following is an example of a software response by a master transmitter in the interrupt routine (see figure 8-10). i2sr lea.l i2sr,-(a7);load effective address bclr.b #1,(a7)+;clear the iif flag move.b i2cr,-(a7);push the address on stack, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-12 mcf5307 users manual i 2 c programming examples btst.b #5,(a7)+;check the msta flag beq.s slave;branch if slave mode move.b i2cr,-(a7);push the address on stack btst.b #4,(a7)+;check the mode flag beq.s receive;branch if in receive mode move.b i2sr,-(a7);push the address on stack, btst.b #0,(a7)+;check ack from receiver bne.b end;if no ack, end of transmission transmitmove.b databuf,-(a7);stack data byte move.b (a7)+, i2dr;transmit next byte of data 8.6.4 generation of stop a data transfer ends when the master signals a stop, which can occur after all data is sent, as in the following example. mastx move.b i2sr, -(a7);if no ack, branch to end btst.b #0,(a7)+ bne.b end move.b txcnt,d0;get value from the transmitting counter beq.s end;if no more data, branch to end move.b databuf,-(a7);transmit next byte of data move.b (a7)+,i2dr move.b txcnt,d0;decrease the txcnt subq.l #1,d0 move.b d0,txcnt bra.s emastx;exit end lea.l i2cr,-(a7);generate a stop condition bclr.b #5,(a7)+ emastx rte;return from interrupt for a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. this is done by setting i2cr[txak] before reading the next-to-last byte. before the last byte is read, a stop signal must be generated, as in the following example. masr move.b rxcnt,d0;decrease rxcnt subq.l #1,d0 move.b d0,rxcnt beq.s enmasr;last byte to be read move.b rxcnt,d1;check second-to-last byte to be read extb.l d1 subi.l #1,d1; bne.s nxmar;not last one or second last lamar bset.b #3,i2cr;disable ack bra nxmar enmasr bclr.b #5,i2cr;last one, generate stop signal nxmar move.b i2dr,rxbuf;read data and store rte 8.6.5 generation of repeated start after the data transfer, if the master still wants the bus, it can signal another start followed by another slave address without signalling a stop, as in the following example. restart move.b i2cr,-(a7);repeat start (restart) bset.b #2, (a7) move.b (a7)+, i2cr move.b calling,-(a7);transmit the calling address, d0=r/w- move.b calling,-(a7); move.b (a7)+, i2dr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 8. i 2 c module 8-13 i 2 c programming examples 8.6.6 slave mode in the slave interrupt service routine, the module addressed as slave bit (iaas) should be tested to check if a calling of its own address has just been received. if iaas is set, software should set the transmit/receive mode select bit (i2cr[mtx]) according to the i2sr[srw]. writing to the i2cr clears the iaas automatically. the only time iaas is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers will have iaas cleared. a data transfer can now be initiated by writing information to i2dr for slave transmits, or read from i2dr in slave-receive mode. a dummy read of i2dr in slave/receive mode releases scl, allowing the master to send data. in the slave transmitter routine, i2sr[rxak] must be tested before sending the next byte of data. setting rxak means an end-of-data signal from the master receiver, after which software must switch it from transmitter to receiver mode. reading i2dr then releases scl so that the master can generate a stop signal. 8.6.7 arbitration lost if several devices try to engage the bus at the same time, one becomes master. hardware immediately switches devices that lose arbitration to slave receive mode. data output to sda stops, but scl is still generated until the end of the byte during which arbitration is lost. an interrupt occurs at the falling edge of the ninth clock of this transfer with i2sr[ial] = 1 and i2cr[msta] = 0. if a device that is not a master tries to transmit or do a start, hardware inhibits the transmission, clears msta without signalling a stop, generates an interrupt to the cpu, and sets ial to indicate a failed attempt to engage the bus. when considering these cases, the slave service routine should rst test ial and software should clear it if it is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8-14 mcf5307 users manual i 2 c programming examples figure 8-10. flow-chart of typical i 2 c interrupt routine clear master mode? tx/rx ? last byte transmitted ? rxak= 0 ? end of addr cycle (master rx) ? write next byte to i2dr switch to rx mode dummy read from i2dr generate stop signal read data from i2dr and store set txak =1 generate stop signal 2nd last byte to be last byte to be ? arbitration lost? clear ial iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to i2dr set rx mode dummy read from i2dr ack from receiver ? tx next byte read data from i2dr and store switch to rx mode dummy read from i2dr rte yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iif address cycle data cycle read read? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 9. interrupt controller 9-1 chapter 9 interrupt controller this chapter describes the operation of the interrupt controller portion of the system integration module (sim). it includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. 9.1 overview the sim provides a centralized interrupt controller for all mcf5307 interrupt sources, which consist of the following: external interrupts software watchdog timer timer modules i 2 c module uart modules dma module figure 9-1 is a block diagram of the interrupt controller. figure 9-1. interrupt controller block diagram interrupt controller 12 icrs imr irq [1,3,5,7] 4 avr ipr irqpar software watchdog tw o two uarts dma i 2 c module four channels general- purpose timers system integration module (sim) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
9-2 mcf5307 users manual interrupt controller registers the sim provides the following registers for managing interrupts: each potential interrupt source is assigned one of the 10 interrupt control registers (icr0?icr9), which are used to prioritize the interrupt sources. the interrupt mask register (imr) provides bits for masking individual interrupt sources. the interrupt pending register (ipr) provides bits for indicating when an interrupt request is being made (regardless of whether it is masked in the imr). the autovector register (avec) controls whether the sim supplies an autovector or executes an external interrupt acknowledge cycle for each irq. the interrupt port assignment register (irqpar) provides the level assignment of the primary external interrupt pins?irq5, irq3, and irq1. 9.2 interrupt controller registers the interrupt controller register portion of the sim memory map is shown in table 9-2. each internal interrupt source has its own interrupt control register (icr0?icr9), shown in table 9-2 and described in section 9.2.1, ?interrupt control registers (icr0?icr9).? table 9-1. interrupt controller registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x040 interrupt pending register (ipr) [p. 9-6] 0x044 interrupt mask register (imr) [p. 9-6] 0x048 reserved autovector register (avr) [p. 9-5] interrupt control registers (icrs) [p. 9-3] 0x04c software watchdog timer (icr0) [p. 9-3] timer0 (icr1) [p. 9-3] timer1 (icr2) [p. 9-3] i 2 c (icr3) [p. 9-3] 0x050 uart0 (icr4) [p. 9-3] uart1 (icr5) [p. 9-3] dma0 (icr6) [p. 9-3] dma1 (icr7) [p. 9-3] 0x054 dma2 (icr8) [p. 9-3] dma3 (icr9) [p. 9-3] reserved table 9-2. interrupt control registers mbar offset register name 0x04c icr0 software watchdog timer 0x04d icr1 timer0 0x04e icr2 timer1 0x04f icr3 i 2 c 0x050 icr4 uart0 0x051 icr5 uart1 0x052 icr6 dma0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 9. interrupt controller 9-3 interrupt controller registers internal interrupts are programmed to a level and priority. each internal interrupt has a unique icr. each of the 7 interrupt levels has 5 priorities, for a total of 35 possible priority levels, encompassing internal and external interrupts. the four external interrupt pins offer seven possible settings at a xed interrupt level and priority. the irqpar determines these settings for external interrupt request levels. external interrupts can be programmed to supply an autovector or execute an external interrupt acknowledge cycle. this is described in section 9.2.2, ?autovector register (avr).? 9.2.1 interrupt control registers (icr0?cr9) the interrupt control registers (icr0?icr9) provide bits for de ning the interrupt level and priority for the interrupt source assigned to the icr, shown in table 9-2. table 9-3 describes icr elds. 0x053 icr7 dma1 0x054 icr8 dma2 0x055 icr9 dma3 76543210 field avec il ip reset 0 0_00 00 r/w r/w address mbar + 0x04c (icr0); 0x04d (icr1); 0x04e (icr2); 0x04f (icr3); 0x050 (icr4); 0x051 (icr5); 0x052 (icr6); 0x053 (icr7); 0x054 (icr8); 0x055 (icr9) figure 9-2. interrupt control registers (icr0?cr9) table 9-3. icr n field descriptions bits field description 7 avec autovector enable. determines whether the interrupt-acknowledge cycle input (for the internal interrupt level indicated in il for each interrupt) requires an autovector response. 0 interrupting source returns vector during interrupt-acknowledge cycle. 1 sim generates autovector during interrupt acknowledge cycle. 6 5 reserved, should be cleared. 4 2 il interrupt level. indicates the interrupt level assigned to each interrupt input. see table 9-4. 1 0 ip interrupt priority. indicates the interrupt priority for internal modules within the interrupt-level assignment. see table 9-4. 00 lowest 01 low 10 high 11 highest table 9-2. interrupt control registers (continued) mbar offset register name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
9-4 mcf5307 users manual interrupt controller registers note: assigning the same interrupt level and priority to multiple icrs causes unpredictable system behavior. table 9-4 shows possible priority schemes for internal and external sources of the mcf5307. the internal module interrupt source in this table can be any internal interrupt source programmed to the given level and priority. this table shows how external interrupts are prioritized with respect to internal interrupt sources within the same level. for example, uart0 and uart1 sources are programmed to il = 110; in this case, uart0 is given lower priority than uart1, so icr4[ip] = 01 and the icr5[ip] = 10. irq3 is programmed to level 6. if all three assert an interrupt request at the same time, they are serviced in the following order: 1. icr5[il] = 110 and icr5[ip] = 10, so uart1 is serviced rst (priority 7 in table 9-4). 2. external interrupt irq3, set to level 6, is serviced next (priority 8). 3. icr4[il] = 110 and icr5[ip] = 01, so uart0 is serviced last (priority 9). table 9-4. interrupt priority scheme priority interrupt level icr interrupt source irqpar[irqpar] il ip 1 7 111 11 internal module xxx 2 111 10 xxx 3 xxx xx external interrupt pin irq7 xxx 4 111 01 internal module xxx 5 111 00 xxx 6 6 110 11 internal module xxx 7 110 10 xxx 8 xxx xx external interrupt pin irq3 (programmed as irq6) x1x 9 110 01 internal module xxx 10 110 00 xxx 11 5 101 11 internal module xxx 12 101 10 xxx 13 xxx xx external interrupt pin irq5 0xx 14 101 01 internal module xxx 15 101 00 xxx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 9. interrupt controller 9-5 interrupt controller registers 9.2.2 autovector register (avr) the autovector register (avr), shown in figure 9-3, enables external interrupt sources to be autovectored, using the vector offset de ned in table 2-19 in section 2.8, ?exception processing overview.? note that the autovector enable for internal interrupt sources applies for respective icrs. 16 4 100 11 internal module xxx 17 100 10 xxx 18 xxx xx external interrupt pin irq5 (programmed as irq4) 1xx 19 100 01 internal module xxx 20 100 00 xxx 21 3 011 11 internal module xxx 22 011 10 xxx 23 xxx xx external interrupt pin irq3 x0x 24 011 01 internal module xxx 25 011 00 xxx 26 2 010 11 internal module xxx 27 010 10 xxx 28 xxx xx external interrupt pin irq1 (programmed as irq2) xx1 29 010 01 internal module xxx 30 010 00 xxx 31 1 001 11 internal module xxx 32 001 10 xxx 33 xxx xx external interrupt pin irq1 xx0 34 001 01 internal module xxx 35 001 00 xxx 76543210 field avec blk reset 0000_0000 r/w r/w address mbar + 0x04b figure 9-3. autovector register (avr) table 9-4. interrupt priority scheme (continued) priority interrupt level icr interrupt source irqpar[irqpar] il ip f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
9-6 mcf5307 users manual interrupt controller registers table 9-5 describes avr elds. . table 9-6 shows the correlation between avr[avec] and the external interrupts. note that an avec n bit is valid only when the corresponding external interrupt request level is enabled in the irqpar. 9.2.3 interrupt pending and mask registers (ipr and imr) the interrupt pending register (ipr), figure 9-4, makes visible the interrupt sources that have an interrupt pending. the interrupt mask register (imr), also shown in figure 9-4, is used to mask the internal and external interrupt sources. note: to mask interrupt sources, rst set the core?s status register interrupt mask level to that of the source being masked in the imr. then, the imr bit can be masked. an interrupt is masked by setting, and enabled by clearing, the corresponding imr bit. when a masked interrupt occurs, the corresponding ipr bit is still set, but no interrupt request is passed to the core. table 9-5. avr field descriptions bit name description 7 1 avec autovector control. determines whether the external interrupt at that level is autovectored. 0 interrupting source returns vector during interrupt-acknowledge cycle. 1 sim generates autovector during interrupt-acknowledge cycle. 0 blk block address strobe (as ) for external avec access. available for users who use as as a global chip select for peripherals and do not want to enable them during an avec cycle. 0 do not block address strobe. 1 block address strobe from asserting. table 9-6. autovector register bit assignments autovector interrupt source autovector register bit location vector offset external interrupt request 1 avec1 0x64 external interrupt request 2 avec2 0x68 external interrupt request 3 avec3 0x6c external interrupt request 4 avec4 0x70 external interrupt request 5 avec5 0x74 external interrupt request 6 avec6 0x78 external interrupt request 7 avec7 0x7c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 9. interrupt controller 9-7 interrupt controller registers table 9-7 describes ipr and imr elds. 9.2.4 interrupt port assignment register (irqpar) the interrupt port assignment register (irqpar), shown in figure 9-5, provides the level assignment of the primary external interrupt pins?irq5, irq3, and irq1. the setting of irqpar2?irqpar0 determines the interrupt level of these external interrupt pins. table 9-8 describes irqpar elds. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field dma3 dma2 reset 1 1 r/w read-only (ipr); r/w (imr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field dma1 dma0 uart1 uart0 i2c timer2 timer1 swt eint7 eint6 eint5 eint4 eint3 eint2 eint1 reset 1111 1111 1111 1 1 1 r/w read-only (ipr); r/w (imr) addr mbar + 0x040 (ipr); + 0x044 (imr) figure 9-4. interrupt pending register (ipr) and interrupt mask register (imr) table 9-7. ipr and imr field descriptions bits name description 31 18 reserved, should be cleared. 17 1 see figure 9-4 interrupt pending/mask. each bit corresponds to an interrupt source de ned by the icr. the corresponding imr bit determines whether an interrupt condition can generate an interrupt. at every clock, the ipr samples the signal generated by the interrupting source. the corresponding ipr bit re ects the state of the interrupt signal even if the corresponding imr bit is set. 0 the corresponding interrupt source is not masked (imr) and has no interrupt pending (ipr). 1 the corresponding interrupt source is masked (imr) and has an interrupt pending (ipr) 76543210 field irqpar2 irqpar1 irqpar0 reset 0000_0000 r/w r/w address mbar + 0x06 figure 9-5. interrupt port assignment register (irqpar) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
9-8 mcf5307 users manual interrupt controller registers table 9-8. irqpar field descriptions bits name description 7 5 irqpar n con gures the irq pin assignments and priorities irqpar n external pin irqpar n = 0 irqpar n = 1 irqpar2 irq5 level 5 level 4 irqpar1 irq3 level 3 level 6 irqpar0 irq1 level 1 level 2 4 0 reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 10. chip-select module 10-1 chapter 10 chip-select module this chapter describes the mcf5307 chip-select module, including the operation and programming model of the chip-select registers, which include the chip-select address, mask, and control registers. 10.1 overview the following list summarizes the key chip-select features: eight independent, user-programmable chip-select signals (cs [7:0]) that can interface with sram, prom, eprom, eeprom, flash, and peripherals address masking for 64-kbyte to 4-gbyte memory block sizes programmable wait states and port sizes external master access to chip selects 10.2 chip-select module signals table 10-1 lists signals used by the chip-select module. table 10-2 shows the interaction of the byte enable/byte-write enables with related signals. table 10-1. chip-select module signals signal description chip selects (cs [7:0]) each cs n can be independently programmed for an address location as well as for masking, port size, read/write burst-capability, wait-state generation, and internal/external termination. only cs 0 is initialized at reset when it acts as a global chip select that allows boot rom to be at any de ned address space. port size and termination (internal versus external) and byte enables for cs 0 are con gured by the logic levels of d[7:5] when rsti negates. output enable (oe ) interfaces to memory or to peripheral devices and enables a read transfer. it is asserted and negated on the falling edge of the clock. oe is asserted only when one of the chip selects matches for the current address decode. byte enables/ byte write enables (be [3:0]/ bwe [3:0]) these multiplexed signals are individually programmed through the byte enable mode bit, cscr n [bem], described in section 10.4.1.3, chip-select control registers (cscr0 cscr7). these generated signals provide byte data select signals, which are decoded from the transfer size, a1, and a0 signals in addition to the programmed port size and burstability of the memory accessed, as table 10-2 shows. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10-2 mcf5307 users manual chip-select operation 10.3 chip-select operation each chip select has a dedicated set of the following registers for con guration and control. chip-select address registers (csar n ) control the base address space of the chip select. see section 10.4.1.1, ?chip-select address registers (csar0?csar7).? table 10-2. byte enables/byte write enable signal settings transfer size port size a1 a0 be0 /bwe0 be1 /bwe1 be2 /bwe2 be3 /bwe3 d[31:24] d[23:16] d[15:8] d[7:0] byte 8-bit 0 0 0111 010111 100111 110111 16-bit 0 0 0 1 1 1 011011 100111 111011 32-bit 0 0 0 1 1 1 011011 101101 111110 word 8-bit 0 0 0 1 1 1 010111 100111 110111 16-bit 0 0 0 0 1 1 100011 32-bit 0 0 0 0 1 1 101100 longword 8-bit 0 0 0111 010111 100111 110111 16-bit 0 0 0 0 1 1 100011 32-bit 0 0 0 0 0 0 line 8-bit 0 0 0111 010111 100111 110111 16-bit 0 0 0 0 1 1 100011 32-bit 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 10. chip-select module 10-3 chip-select operation chip-select mask registers (csmr n ) provide 16-bit address masking and access control. see section 10.4.1.2, ?chip-select mask registers (csmr0?csmr7).? chip-select control registers (cscr n ) provide port size and burst capability indication, wait-state generation, and automatic acknowledge generation features. see section 10.4.1.3, ?chip-select control registers (cscr0?cscr7).? each cs n can assert during speci c cpu space accesses such as interrupt-acknowledge cycles and each can be accessed by an external master. cs0 is a global chip select after reset and provides relocatable boot rom capability. 10.3.1 general chip-select operation when a bus cycle is initiated, the mcf5307 rst compares its address with the base address and mask con gurations programmed for chip selects 0?7 (con gured in cscr0?cscr7) and dram block 0 and 1 address and control registers (con gured in dacr0 and dacr1). if the driven address matches a programmed chip select or dram block, the appropriate chip select is asserted or the dram block is selected using the speci cations programmed in the respective con guration register. otherwise, the following occurs: if the address and attributes do not match in cscr or dacr, the mcf5307 runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. should an address and attribute match in multiple cscrs, the matching chip-select signals are driven; however, the mcf5307 runs an external burst-inhibited bus cycle with external termination on a 32-bit port. should an address and attribute match both dacrs or a dacr and a cscr, the operation is unde ned. table 10-3 shows the type of access as a function of match in the cscrs and dacrs. table 10-3. accesses by matches in cscrs and dacrs number of cscr matches number of dacr matches type of access 0 0 external 10 de ned by cscr multiple 0 external, burst-inhibited, 32-bit 01 de ned by dacrs 1 1 unde ned multiple 1 unde ned 0 multiple unde ned 1 multiple unde ned multiple multiple unde ned f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10-4 mcf5307 users manual chip-select operation 10.3.1.1 8-, 16-, and 32-bit port sizing static bus sizing is programmable through the port size bits, cscr[ps]. see section 10.4.1.3, ?chip-select control registers (cscr0?cscr7).? figure 10-1 shows the correspondence between data byte lanes and the external chip-select memory. note that all lanes are driven, although unused lines are unde ned. figure 10-1. connections for external memory port sizes 10.3.1.2 global chip-select operation cs0 , the global (boot) chip select, allows address decoding for boot rom before system initialization. its operation differs from other external chip-select outputs after system reset. after system reset, cs0 is asserted for every external access. no other chip-select can be used until the valid bit, csmr0[v], is set, at which point cs0 functions as con gured and cs [7:1] can be used. at reset, the port size and automatic acknowledge functions of the global chip-select are determined by the logic levels of the inputs on d[7:5]. table 10-4 and table 10-5list the various reset encodings for the con guration signals multiplexed with d[7:5]. provided the required address range is in the chip-select address register (csar0), cs0 can table 10-4. d7/aa, automatic acknowledge of boot cs0 d7/aa boot cs0 aa con?uration at reset 0 disabled 1 enable with 15 wait states table 10-5. d[6:5]/ps[1:0], port size of boot cs0 d[6:5]/ps[1:0] boot cs0 port size at reset 00 32-bit port 01 8-bit port 1x 16-bit port byte 0 8-bit port 16-bit port 32-bit port byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 d[31:24] d[23:16] d[15:8] d[7:0] external memory memory memory data bus be0 be1 be2 be3 driven, undefined driven, undefined f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 10. chip-select module 10-5 chip-select registers be programmed to continue decoding for a range of addresses after the csmr0[v] is set, after which the global chip-select can be restored only by a system reset. 10.4 chip-select registers table 10-6table 10-6 is the chip-select register memory map. reading reserved locations returns zeros. table 10-6. chip-select registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x080 chip-select address register bank 0 (csar0) [p. 10-6] reserved 1 0x084 chip-select mask register bank 0 (csmr0) [p. 10-6] 0x088 reserved 1 chip-select control register bank 0 (cscr0) [p. 10-8] 0x08c chip-select address register bank 1 (csar1) [p. 10-6] reserved 1 0x090 chip-select mask register bank 1 (csmr1) [p. 10-6] 0x094 reserved 1 chip-select control register bank 1 (cscr1) [p. 10-8] 0x098 chip-select address register bank 2 (csar2) [p. 10-6] reserved 1 0x09c chip-select mask register bank 2 (csmr2) [p. 10-6] 0x0a0 reserved 1 chip-select control register bank 2 (cscr2) [p. 10-8] 0x0a4 chip-select address register bank 3 (csar3) [p. 10-6] reserved 1 0x0a8 chip-select mask register bank 3 (csmr3) [p. 10-6] 0x0ac reserved 1 chip-select control register bank 3 (cscr3) [p. 10-8] 0x0b0 chip-select address register bank 4 (csar4) [p. 10-6] reserved 1 0x0b4 chip-select mask register bank 4 (csmr4) [p. 10-6] 0x0b8 reserved 1 chip-select control register bank 4 (cscr4) [p. 10-8] 0x0bc chip-select address register bank 5 (csar5) [p. 10-6] reserved 1 0x0c0 chip-select mask register bank 5 (csmr5) [p. 10-6] 0x0c4 reserved chip-select control register bank 5 (cscr5) [p. 10-8] 0x0c8 chip-select address register bank 6 (csar6) [p. 10-6] reserved 1 0x0cc chip-select mask register bank 6 (csmr6) [p. 10-6] 0x0d0 reserved 1 chip-select control register bank 6 (cscr6) [p. 10-8] 0x0d4 chip-select address register bank 7 (csar7) [p. 10-6] reserved 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10-6 mcf5307 users manual chip-select registers note: external masters cannot access mcf5307 on-chip memories or mbar, but can access any of the chip-select module registers. 10.4.1 chip-select module registers the chip-select module is programmed through the chip select address registers (csar0?csar7), chip select mask registers (csmr0?csmr7), and the chip select control registers (cscr0?cscr7). 10.4.1.1 chip-select address registers (csar0?sar7) chip select address registers, figure 10-2, specify the chip select base addresses. table 10-7 describes csar[ba]. 10.4.1.2 chip-select mask registers (csmr0?smr7) the chip select mask registers, figure 10-3, are used to specify the address mask and allowable access types for the respective chip selects. 0x0d8 chip-select mask register bank 7 (csmr7) [p. 10-6] 0x0dc reserved 1 chip-select control register bank 7 (cscr7) [p. 10-8] 1 addresses not assigned to a register and undefined register bits are reserved for expansion. write accesses to these reserved address spaces and reserved register bits have no effect. 15 0 field ba reset uninitialized r/w r/w addr 0x080 (csar0); 0x08c (csar1); 0x098 (csar2); 0x0a4 (csar3); 0x0b0 (csar4); 0x0bc (csar5); 0x0c8 (csar6); 0x0d4 (csar7) figure 10-2. chip select address registers (csar0?sar7) table 10-7. csar n field description bits name description 15 0 ba base address. de nes the base address for memory dedicated to chip select cs [7:0]. ba is compared to bits 31 16 on the internal address bus to determine if chip-select memory is being accessed. table 10-6. chip-select registers (continued) mbar offset [31:24] [23:16] [15:8] [7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 10. chip-select module 10-7 chip-select registers . table 10-8 describes csmr elds. 31 1615 9876543210 field bam wp am c/i sc sd uc ud v reset unitialized 0 r/w r/w addr 0x084 (csmr0); 0x090 (csmr1); 0x09c (csmr2); 0x0a8 (csmr3); 0x0b4 (csmr4); 0x0c0 (csmr5); 0x0cc (csmr6); 0x0d8 (csmr7) figure 10-3. chip select mask registers (csmr n ) table 10-8. csmr n field descriptions bits name description 31 16 bam base address mask. de nes the chip select block by masking address bits. setting a bam bit causes the corresponding csar bit to be ignored in the decode. 0 corresponding address bit is used in chip-select decode. 1 corresponding address bit is a don t care in chip-select decode. the block size for cs [7:0] is 2 n ; n = (number of bits set in respective csmr[bam]) + 16. so, if csar0 = 0x0000 and csmr0[bam] = 0x0008, cs0 would address two discontinuous 64-kbyte memory blocks: one from 0x0000 0xffff and one from 0x8_0000 0x8_ffff. likewise, for cs0 to access 32 mbytes of address space starting at location 0x0, cs1 must begin at the next byte after cs0 for a 16-mbyte address space. then csar0 = 0x0000, csmr0[bam] = 0x01ff, csar1 = 0x0200, and csmr1[bam] = 0x00ff. 8 wp write protect. controls write accesses to the address range in the corresponding csar. attempting to write to the range of addresses for which csar n [wp] = 1 results in the appropriate chip select not being selected. no exception occurs. 0 both read and write accesses are allowed. 1 only read accesses are allowed. 7 reserved, should be cleared. 6 am alternate master. when am = 0 during an external master or dma access, sc, sd, uc, and ud are don t cares in the chip-select decode. 5 1 c/i, sc, sd, uc, ud address space mask bits. these bits determine whether the speci ed accesses can occur to the address space de ned by the bam for this chip select. c/i cpu space and interrupt acknowledge cycle mask sc supervisor code address space mask sd supervisor data address space mask uc user code address space mask ud user data address space mask 0 the address space assigned to this chip select. is available to the speci ed access type. 1 the address space assigned to this chip select. is not available (masked) to the speci ed access type. if this address space is accessed, chip select is not activated and a regular external bus cycle occurs. note that if if am = 0, sc, sd, uc, and ud are ignored in the chip select decode on external master or dma access. 0 v valid bit. indicates whether the corresponding csar, csmr, and cscr contents are valid. programmed chip selects do not assert until v is set (except for cs0 , which acts as the global chip select). reset clears each csmr n [v]. 0 chip select invalid 1 chip select valid f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10-8 mcf5307 users manual chip-select registers 10.4.1.3 chip-select control registers (cscr0?scr7) each chip-select control register, figure 10-4, controls the auto acknowledge, external master support, port size, burst capability, and activation of each chip select. note that to support the global chip select, cs0 , the cscr0 reset values differ from the other cscrs. cs0 allows address decoding for boot rom before system initialization. figure 10-4. chip-select control registers (cscr0?scr7) table 10-9 describes cscr n elds. 151413 1098765 4 3 2 0 field ws aa ps1 ps0 bem bstr bstw reset: cscr0 11_11 d7 d6 d5 reset: other cscrs unitialized r/w r/w address 0x08a (cscr0); 0x096 (cscr1); 0x0a2 (cscr2); 0x0ae (cscr3); 0x0ba (cscr4); 0x0c6 (cscr5); 0x0d2 (cscr6); 0x0de (cscr7) table 10-9. cscr n field descriptions bits name description 15 14 reserved, should be cleared. 13 10 ws wait states. the number of wait states inserted before an internal transfer acknowledge is generated (ws = 0 inserts zero wait states, ws = 0xf inserts 15 wait states). if aa = 0, t a must be asserted by the external system regardless of the number of wait states generated. in that case, the external transfer acknowledge ends the cycle. an external t a supersedes the generation of an internal t a . 9 reserved, should be cleared. 8 aa auto-acknowledge enable. determines the assertion of the internal transfer acknowledge for accesses speci ed by the chip-select address. 0 no internal t a is asserted. cycle is terminated externally. 1 internal t a is asserted as speci ed by ws. note that if aa = 1 for a corresponding cs n and the external system asserts an external t a before the wait-state countdown asserts the internal t a , the cycle is terminated. burst cycles increment the address bus between each internal termination. 7 6 ps port size. speci es the width of the data associated with each chip select. it determines where data is driven during write cycles and where data is sampled during read cycles. see section 10.3.1.1, 8-, 16-, and 32-bit port sizing. 00 32-bit port size. valid data sampled and driven on d[31:0] 01 8-bit port size. valid data sampled and driven on d[31:24] 1x 16-bit port size. valid data sampled and driven on d[31:16] 5 bem byte enable mode. speci es the byte enable operation. certain srams have byte enables that must be asserted during reads as well as writes. bem can be set in the relevant cscr to provide the appropriate mode of byte enable in support of these srams. 0 neither be nor bwe is asserted for read. bwe is generated for data write only. 1be is asserted for read; bwe is asserted for write. 4 bstr burst read enable. speci es whether burst reads are used for memory associated with each cs n . 0 data exceeding the speci ed port size is broken into individual, port-sized non-burst reads. for example, a longword read from an 8-bit port is broken into four 8-bit reads. 1 enables data burst reads larger than the speci ed port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 10. chip-select module 10-9 chip-select registers 10.4.1.4 code example the code below provides an example of how to initialize the chip-selects. only chip selects 0, 1, 2, and 3 are programmed here; chip selects 4, 5, 6, and 7 are left invalid. mbarx de nes the base of the module address space. csar0 equ mbarx+0x080 ;chip select 0 address register csmr0 equ mbarx+0x084 ;chip select 0 mask register cscr0 equ mbarx+0x08a ;chip select 0 control register csar1 equ mbarx+0x08c ;chip select 1 address register csmr1 equ mbarx+0x090 ;chip select 1 mask register cscr1 equ mbarx+0x096 ;chip select 1 control register csar2 equ mbarx+0x098 ;chip select 2 address register csmr2 equ mbarx+0x09c ;chip select 2 mask register cscr2 equ mbarx+0x0a2 ;chip select 2 control register csar3 equ mbarx+0x0a4 ;chip select 3 address register csmr3 equ mbarx+0x0a8 ;chip select 3 mask register cscr3 equ mbarx+0x0ae ;chip select 3 control register csar4 equ mbarx+0x0b0 ;chip select 4 address register csar4 equ mbarx+0x0b4 ;chip select 4 mask register csmr4 equ mbarx+0x0ba ;chip select 4 control register csar5 equ mbarx+0x0bc ;chip select 5 address register csmr5 equ mbarx+0x0c0 ;chip select 5 mask register cscr5 equ mbarx+0x0c6 ;chip select 5 control register csar6 equ mbarx+0x0c8 ;chip select 6 address register csmr6 equ mbarx+0x0cc ;chip select 6 mask register cscr6 equ mbarx+0x0d2 ;chip select 6 control register csar7 equ mbarx+0x0d4 ;chip select 7 address register csmr7 equ mbarx+0x0d8 ;chip select 7 mask register cscr7 equ mbarx+0x0de ;chip select 7 control register ; all other chip selects should be programmed and made valid before global ; chip select is de-activated by validating cs0 ; program chip select 3 registers move.w #0x0040,d0 ;csar3 base address 0x00400000 move.w d0,csar3 move.w #0x00a0,d0 ;cscr3 = no wait states, aa=0, ps=16-bit, bem=1, move.w d0,cscr3 ;bstr=0, bstw=0 move.l #0x001f016b,d0 ;address range from 0x00400000 to 0x005fffff move.l d0,csmr3 ;wp,em,c/i,sd,ud,v=1; sc,uc=0 ; program chip select 2 registers move.w #0x0020,d0 ;csar2 base address 0x00200000 (to 0x003fffff) 3 bstw burst write enable. speci es whether burst writes are used for memory associated with each cs n . 0 break data larger than the speci ed port size into individual port-sized, non-burst writes. for example, a longword write to an 8-bit port takes four byte writes. 1 enables burst write of data larger than the speci ed port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports. 2 0 reserved, should be cleared. table 10-9. cscr n field descriptions bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10-10 mcf5307 users manual chip-select registers move.w d0,csar2 move.w #0x0538,d0 ;cscr2 = 1 wait state, aa=1, ps=32-bit, bem=1, move.w d0,cscr2 ;bstr=1, bstw=1 move.l #0x001f0001,d0 ;address range from 0x00200000 to 0x003fffff move.l d0,csmr2 ;wp,em,c/i,sc,sd,uc,ud=0; v=1 ; program chip select 1 registers move.w #0x0000,d0 ;csar1 base addresses 0x00000000 (to 0x001fffff) move.w d0,csar1 ;and 0x80000000 (to 0x801fffff) move.w #0x09b0,d0 ;cscr1 = 2 wait states, aa=1, ps=16-bit, bem=1, move.w d0,cscr1 ;bstr=1, bstw=0 move.l #0x801f0001,d0 ;address range from 0x00000000 to 0x001fffff and move.l d0,csmr1 ;0x80000000 to 0x801fffff ;wp, em, c/i, sc, sd, uc, ud=0, v=1 ; program chip select 0 registers move.w #0x0080,d0 ;csar0 base address 0x00800000 (to 0x009fffff) move.w d0,csar0 move.w #0x0d80,d0 ;cscr0 = three wait states, aa=1, ps=16-bit, bem=0, move.w d0,cscr0 ;bstr=0, bstw=0 ; program chip select 0 mask register (validate chip selects) move.l #0x001f0001,d0 ;address range from 0x00800000 to 0x009fffff move.l d0,csmr0 ;wp,em,c/i,sc,sd,uc,ud=0; v=1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-1 chapter 11 synchronous/asynchronous dram controller module this chapter describes con guration and operation of the synchronous/asynchronous dram controller component of the system integration module (sim). it begins with a general description and brief glossary, and includes a description of signals involved in dram operations. the remainder of the chapter consists of the two following parts: section 11.3, ?asynchronous operation,? describes the programming model and signal timing for the four basic asynchronous modes. ? non-page mode ? burst page mode ? continuous page mode ? extended data-out mode section 11.4, ?synchronous operation,? describes the programming model and signal timing, as well as the command set required for synchronous operations. this section also includes extensive examples the designer can follow to better understand how to con gure the dram controller for synchronous operations. 11.1 overview the dram controller module provides glueless integration of dram with the coldfire product. the key features of the dram controller include the following: support for two independent blocks of dram interface to standard synchronous/asynchronous dynamic random access memory (adram/sdram) components programmable sras , scas , and refresh timing support for page mode support for 8-, 16-, and 32-bit wide dram blocks support for synchronous and asynchronous drams, including edo dram, sdram, and fast page mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-2 mcf5307 users manual overview 11.1.1 de?itions the following terminology is used in this chapter: a/sdram block?any group of dram memories selected by one of the mcf5307 ras [1:0] signals. thus, the mcf5307 can support two independent memory blocks. the base address of each block is programmed in the dram address and control registers (dacr0 and dacr1). sdram?rams that operate like asynchronous drams but with a synchronous clock, a pipelined, multiple-bank architecture, and faster speed. sdram bank?an internal partition in an sdram device. for example, a 64-mbit sdram component might be con gured as four 512k x 32 banks. banks are selected through the sdram component?s bank select lines. 11.1.2 block diagram and major components the basic components of the dram controller are shown in figure 11-1. figure 11-1. asynchronous/synchronous dram controller block diagram the dram controller?s major components, shown in figure 11-1, are described as follows: dram address and control registers (dacr0 and dacr1)?the dram controller consists of two con guration register units, one for each supported memory block. dacr0 is accessed at mbar + 0x0108; dacr1 is accessed at 0x010. the register information is passed on to the hit logic. memory block 0 hit logic dram address/control register 0 (dacr0) a[31:0] internal address control logic and ras [1:0] cas [3:0] dramw dram controller module refresh counter scas sras scke state machine multiplexing page hit logic dram control register (dcr) bus memory block 1 hit logic dram address/control register 1 (dacr1) these signals a[31:0] are used for sdram only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-3 dram controller operation control logic and state machine?generates all dram signals, taking bus cycle characteristic data from the block logic, along with hit information to generate dram accesses. handles refresh requests from the refresh counter. ? dram control register (dcr)?contains data to control refresh operation of the dram controller. both memory blocks are refreshed concurrently as controlled by dcr[rc]. ? refresh counter?determines when refresh should occur, determined by the value of dcr[rc]. it generates a refresh request to the control block. hit logic?compares address and attribute signals of a current dram bus cycle to both dacrs to determine if a dram block is being accessed. hits are passed to the control logic along with characteristics of the bus cycle to be generated. page hit logic?determines if the next dram access is in the same dram page as the previous one. this information is passed on to the control logic. address multiplexing?multiplexes addresses to allow column and row addresses to share pins. this allows glueless interface to drams. 11.2 dram controller operation the dram controller mode is programmed through dcr[so]. asynchronous mode (so = 0) includes support for page mode and edo drams. synchronous mode is designed to work with industry-standard sdrams. these modes act very differently from one another, especially regarding the use of dram registers and pins. memory blocks cannot operate in different modes; both are either synchronous or asynchronous. 11.2.1 dram controller registers the dram controller registers memory map, table 11-1, is the same regardless of whether asynchronous or synchronous dram is used, although bit con gurations may vary. note: external masters cannot access mcf5307 on-chip memories or mbar, but they can access dram controller registers. table 11-1. dram controller registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x100 dram control register (dcr) [p. 11-4] reserved 0x104 reserved 0x108 dram address and control register 0 (dacr0) [p. 11-5] 0x10c dram mask register block 0 (dmr0) [p. 11-7] 0x110 dram address and control register 1 (dacr1) [p. 11-5] 0x114 dram mask register block 1 (dmr1) [p. 11-7] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-4 mcf5307 users manual asynchronous operation 11.3 asynchronous operation the dram controller supports asynchronous drams for cost-effective systems. typical access times for the dram controller interfacing to adram are 4-3-3-3. the dram controller supports the following four asynchronous modes: non-page mode burst page mode continuous page mode extended data-out mode in asynchronous mode, ras and cas always transition at the falling clock edge. as summarized previously, operation and timing of each adram block is controlled by separate registers, but refresh is the same for both. all adram accesses should be terminated by the dram controller. there is no priority encoding between memory blocks, so programming blocks to overlap with other blocks or with other internal resources causes unde ned behavior. 11.3.1 dram controller signals in asynchronous mode table 11-2 summarizes dram signals used in asynchronous mode. 11.3.2 asynchronous register set the following register con gurations apply when dcr[so] is 0, indicating the dram controller is interfacing to asynchronous drams. 11.3.2.1 dram control register (dcr) in asynchronous mode the dcr provides programmable options for the refresh logic as well as the control bit to determine if the module is operating with synchronous or asynchronous drams. the dcr is shown in figure 11-2. table 11-2. sdram signal summary signal description ras [1:0] row address strobes. interface to ras inputs on industry-standard adrams. when sdrams are used, these signals interface to the chip-select lines within an sdram s memory block. thus, there is one ras line for each of the two blocks. cas [3:0] column address strobes. interface to cas inputs on industry-standard drams. these provide cas for a given adram block. when sdrams are used, cas [3:0] control the byte enables (dqm x ) for standard sdrams. cas [3:0] strobes data in least-to-most signi cant byte order (cas0 is msb). dramw dram read/write. asserted when a dram write cycle is underway. negated for read bus cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-5 asynchronous operation table 11-3 describes dcr elds. 11.3.2.2 dram address and control registers (dacr0/dacr1) dacr0 and dacr1, figure 11-3, contain the base address compare value and the control bits for memory blocks 0 and 1. address and timing are also controlled by these registers. memory areas de ned for each block should not overlap; operation is unde ned for accesses in overlapping regions. 15 14 13 12 11 10 9 8 0 field so nam rra rrp rc reset 0 uninitialized r/w r/w address mbar + 0x100 figure 11-2. dram control register (dcr) (asynchronous mode) table 11-3. dcr field descriptions (asynchronous mode) bits name description 15 so synchronous operation. selects synchronous or asynchronous mode. a dram controller in synchronous mode can be switched to adram mode only by resetting the mcf5307. 0 asynchronous drams. default at reset. 1 synchronous drams 14 reserved, should be cleared. 13 nam no address multiplexing. some implementations require external multiplexing. for example, when linear addressing is required, the dram should not multiplex addresses on dram accesses. 0 the dram controller multiplexes the external address bus to provide column addresses. 1 the dram controller does not multiplex the external address bus to provide column addresses. 12 11 rra refresh ras asserted. determines how long ras is asserted during a refresh operation. 00 2 clocks 01 3 clocks 10 4 clocks 11 5 clocks 10 9 rrp refresh ras precharge. controls how many clocks ras is precharged after a refresh operation before accesses are allowed to dram. 00 1 clock 01 2 clocks 10 3 clocks 11 4 clocks 8 0 rc refresh count. controls refresh frequency. the number of bus clocks between refresh cycles is (rc + 1) * 16. refresh can range from 16 8192 bus clocks to accommodate both standard and low-power drams with bus clock operation from less than 2 mhz to greater than 50 mhz. the following example calculates rc for an auto-refresh period for 4096 rows to receive 64 ms of refresh every 15.625 s for each row (625 bus clocks at 40 mhz). # of bus clocks = 625 = (rc eld + 1) * 16 rc = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, rc = 0x26. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-6 mcf5307 users manual asynchronous operation table 11-4 describes dacr n elds. 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field ba re cas rp rncn rcd edo ps pm reset unitialized 0 unitialized r/w r/w addr mbar + 0x10c (dacr0); 0x110 (dacr1) figure 11-3. dram address and control registers (dacr0/dacr1) table 11-4. dacr0/dacr1 field description bits name description 31 18 ba base address. used with dmr[bam] to determine the address range in which the associated dram block is located. each ba bit is compared with the corresponding address of the bus cycle in progress. if each bit matches, or if bits that do not match are masked in the bam, the address selects the associated dram block. 17 16 reserved, should be cleared. 15 re refresh enable. determines whether the dram controller generates a refresh to the associated dram block. dram contents are not preserved during hard reset or software watchdog reset. 0 do not refresh associated dram block. (default at reset) 1 refresh associated dram block. 14 reserved, should be cleared. 13 12 cas cas timing. determines how long cas is asserted during a dram access. 00 1 clock cycle 01 2 clock cycles 10 3 clock cycles 11 4 clock cycles 11 10 rp ras precharge timing. determines how long ras is precharged between accesses. note that rp is different from dcr[rrp]. 00 1 clock cycle 01 2 clock cycles 10 3 clock cycles 11 4 clock cycles 9 rncn ras -negate-to-cas -negate. controls whether ras and cas negate concurrently or one clock apart. rncn is ignored if cas is asserted for only one clock and both ras and cas are negated. rncn is used only for non-page-mode accesses and single accesses in page mode. 0 ras negates concurrently with cas . 1 ras negates one clock before cas . 8 rcd ras -to-cas delay. determines the number of system clocks between assertions of ras and cas . 0 1 clock cycle 1 2 clock cycles 7 reserved, should be cleared. 6 edo extended data out. determines whether the dram block operates in a mode to take advantage of industry-standard edo drams. do not use edo mode with non-edo dram. 0 edo operation disabled. 1 edo operation enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-7 asynchronous operation 11.3.2.3 dram controller mask registers (dmr0/dmr1) the dram controller mask registers (dmr0 and dmr1), shown in figure 11-4, include mask bits for the base address and for address attributes. table 11-5 describes dmr n elds. 5 4 ps port size. determines the port size of the associated dram block. for example, if two 16-bit wide dram components form one dram block, the port size is 32 bits. programming ps allows the dram controller to execute dynamic bus sizing for associated accesses. 00 32-bit port 01 8-bit port 1x 16-bit port 3 2 pm page mode. con gures page-mode operation for the memory block. 00 no page mode 01 burst page mode (page mode for bursts only) 10 reserved 11 continuous page mode 1 0 reserved, should be cleared. 31 1817 9876543210 field bam wp c/i am sc sd uc ud v reset uninitialized 0 r/w r/w addr mbar + 0x10c (dmr0), 0x114 (dmr1) figure 11-4. dram controller mask registers (dmr0 and dmr1) table 11-5. dmr0/dmr1 field descriptions bits name description 31 18 bam base address mask. masks the associated dacr n [ba]. lets the dram controller connect to various dram sizes. mask bits need not be contiguous (see section 11.5, sdram example. ) 0 the associated address bit is used in decoding the dram hit to a memory block. 1 the associated address bit is not used in the dram hit decode. 17 9 reserved, should be cleared. 8 wp write protect. determines whether the associated block of dram is write protected. 0 allow write accesses 1 ignore write accesses. the dram controller ignores write accesses to the memory block and an address exception occurs. write accesses to a write-protected dram region are compared in the chip select module for a hit. if no hit occurs, an external bus cycle is generated. if this external bus cycle is not acknowledged, an access exception occurs. 7 reserved, should be cleared. table 11-4. dacr0/dacr1 field description (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-8 mcf5307 users manual asynchronous operation 11.3.3 general asynchronous operation guidelines the dram controller provides control for ras , cas , and dramw signals, as well as address multiplexing and bus cycle termination. whether the mode is synchronous or asynchronous determines signal control and termination. to reduce complexity, multiplexing is the same for both modes. table 11-6 shows the scheme for dram con gurations. this scheme works for symmetric con gurations (in which the number of rows equals the number of columns) as well as asymmetric con gurations (in which the number of rows and columns are different). 6 1am x address modi er masks. determine which accesses can occur in a given dram block. 0 allow access type to hit in dram 1 do not allow access type to hit in dram bit associated access type access de?ition c/i cpu space/interrupt acknowledge movec instruction or interrupt acknowledge cycle am alternate master external or dma master sc supervisor code any supervisor-only instruction access sd supervisor data any data fetched during the instruction access uc user code any user instruction ud user data any user data 0 v valid. cleared at reset to ensure that the dram block is not erroneously decoded. 0 do not decode dram accesses. 1 registers controlling the dram block are initialized; dram accesses can be decoded. table 11-6. generic address multiplexing scheme address pin row address column address notes relating to port sizes 17 17 0 8-bit port only 16 16 1 8- and 16-bit ports only 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 99 8 17 17 16 32-bit port only 18 18 17 16-bit port only or 32-bit port with only 8 column address lines 19 19 18 16-bit port only when at least 9 column address lines are used table 11-5. dmr0/dmr1 field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-9 asynchronous operation note the following: each mcf5307 address bit drives both a row address and a column address bit. as the user upgrades adram, corresponding mcf5307 address bits must be connected. this multiplexing scheme allows various memory widths to be connected to the address bus. some differences exist for each of the three possible port sizes. note that only 8-bit ports use an a0 address from the mcf5307. because 16- and 32-bit ports issue either words or longwords when accessed, they do not use the mcf5307 a0 signal. likewise, the con guration for 32-bit ports uses neither a0 or a1. this presents a slight problem because dram address signal a0 is issued on physical pin a17 of the mcf5307 along with the adram address signal a17. although a0 is not used for larger ports, a17 is still needed. the mcf5307 dram controller provides for this by changing the column address that appears on physical pin a17 of the processor whenever an 8-bit port is not selected. this is determined by the dacr n [ps] settings. for 8-bit ports, mcf5307 physical pin a17 drives logical address a0 during the cas cycle. when 16- or 32-bit port sizes are programmed, the cas cycle pin a17 drives logical address a16, as indicated in the generic connection scheme. if a 32-bit port is used with only eight column address lines, a18 must drive dram address bit a18. otherwise, in 32-bit port con gurations, the mcf5307 physical address line is not connected with more than eight column address lines. all adram blocks have a xed page size of 512 bytes for page-mode operation. the addresses are connected differently for various width combinations. table 11-7, table 11-8, and table 11-9 show how 8-, 16-, and 32-bit symmetrical adram memories are connected to the address bus. the memory sizes show what dram size is accessed if the corresponding bits are connected to the memory. in each case, there is a base memory size. this limitation exists to allow simple page-mode multiplexing. notice also that mcf5307 pin 17 is treated differently in byte-wide operations. in byte-wide operations, address bits 16 and 17 are driven on mcf5307 physical address pins 16 and 17, rather than the two bits being driven solely on a17, as they are for 32-wide memories. 20 20 19 21 21 20 22 22 21 23 23 22 24 24 23 25 25 24 table 11-6. generic address multiplexing scheme (continued) address pin row address column address notes relating to port sizes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-10 mcf5307 users manual asynchronous operation note that in table 11-8, mcf5307 pin a19 is not connected because dram address bit 18 is already provided on mcf5307 pin a18; thus, the next mcf5307 pin used should be a20. table 11-7. dram addressing for byte-wide memories mcf5307 address pin mcf5307 address bit driven for ras mcf5307 address bit driven when cas is asserted memory size 17 17 0 base memory size of 256 kbytes 16 16 1 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 99 8 19 19 18 1 mbyte 21 21 20 4 mbytes 23 23 22 16 mbytes 25 25 24 64 mbytes table 11-8. dram addressing for 16-bit wide memories mcf5307 address pin mcf5307 address bit driven for ras mcf5307 address bit driven when cas is asserted memory size 16 16 1 base memory size of 128 kbytes 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 99 8 18 18 17 512 kbytes 20 20 19 2 mbytes 22 22 21 8 mbytes 24 24 23 32 mbytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-11 asynchronous operation 11.3.3.1 non-page-mode operation in non-page mode, the simplest mode, the dram controller provides termination and runs a separate bus cycle for each data transfer. figure 11-5 shows a non-page-mode access in which a dram read is followed by a write. addresses for a new bus cycle are driven at the rising clock edge. for a dram block hit, the associated ras is driven at the next falling edge. here dacr n [rcd] = 0, so the address is multiplexed at the next rising edge to provide the column address. the required cas signals are then driven at the next falling edge and remain asserted for the period programmed in dacr n [cas]. here, dacr n [rncn] = 1, so it is precharged one clock before cas is negated. on a read, data is sampled on the last rising edge of the clock that cas is valid. figure 11-5. basic non-page-mode operation rcd = 0, rncn = 1 (4-4-4-4) table 11-9. dram addressing for 32-bit wide memories mcf5307 address pin mcf5307 address bit driven for ras mcf5307 address bit driven when cas is asserted memory size 15 15 2 base memory size of 64 kbytes 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 99 8 17 17 16 256 kbytes 19 19 18 1 mbyte 21 21 20 4 mbytes 23 23 22 16 mbytes 25 25 24 64 mbytes a[31:0] ras [1] or [0] cas [3:0] dramw d[31:0] dacr n [rcd] = 0 dacr n [rncn] = 1 dacr n [cas] = 01] row column bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-12 mcf5307 users manual asynchronous operation figure 11-6 shows a variation of the basic cycle. in this case, rcd is 1, so there are two clocks between ras and cas . note that the address is multiplexed on the rising clock immediately before cas is asserted. because rncn = 0, ras and cas are negated together. the next bus cycle is initiated, but because dacr n [rp] requires ras to be precharged for two clocks, ras is delayed for a clock in the bus cycle. note that this does not delay the address signals, only ras . figure 11-6. basic non-page-mode operation rcd = 1, rncn = 0 (5-5-5-5) 11.3.3.2 burst page-mode operation burst page-mode operation (dacrn[pm] = 01) optimizes memory accesses in page mode by allowing a row address to remain registered in the dram while accessing data in different columns. this eliminates the setup and hold times associated with the need to precharge and assert ras. therefore, only the rst bus cycle in the page takes the full access time; subsequent accesses are streamlined. single accesses look the same as non-page-mode accesses. burst page-mode accesses of any size?byte, word, longword, or line?are assumed to reside in the same page. in this mode, the dram controller generates a burst transfer only when the operand is larger than the dram block port size (such as, a line transfer to a 32-bit port or a longword transfer to an 8-bit port). the primary cycle asserts ras and cas ; subsequent cycles assert only cas . at the end of the access, ras is precharged. the dram controller increments addresses between cycles. figure 11-7 shows a read access in burst page mode. four accesses take place, which could be a 32-bit access to an 8-bit port or a line access to a 32-bit port. other burst page-mode operations may be from 2 to 16 accesses long, depending on the access and port sizes. in those cases, timing is similar with more or fewer accesses. a[31:0] ras [1] or [0] cas [3:0] dramw d[31:0] rcd = 1 rncn = 0 cas = 01 rp = 01 row column bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-13 asynchronous operation figure 11-7. burst page-mode read operation (4-3-3-3) figure 11-8 shows the write operation with the same con guration. figure 11-8. burst page-mode write operation (4-3-3-3) 11.3.3.3 continuous page mode continuous page mode (dacrn[pm] = 11) is a type of page mode that balances performance, complexity, and size. in typical page-mode implementations, sequential addresses are checked for multiple hits in a dram block. on a hit, ras remains asserted and cas is asserted with the new column address. on a miss, ras must be precharged again before the bus cycle begins. continuous page mode supports page-mode operation without requiring an address holding register per memory block and eliminates the delay for a miss-to-precharge ras for the upcoming bus cycle. because the internal mcf5307 address bus is pipelined, addresses for a[31:0] ras [1] or [0] cas [3:0] dramw d[31:0] rcd = 0 cas = 01 row column column column column bclko a[31:0] ras [1] or [0] cas [3:0] dramw d[31:0] rcd = 0 cas = 01 row column column column column bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-14 mcf5307 users manual asynchronous operation the next bus cycle are often available before the current cycle completes. the two addresses are compared at the end of the cycle to determine if the next address hits the same page. if so, ras remains asserted. if not, or if no access is pending, ras is precharged before the next bus cycle is active on the external bus. as a result, a page miss suffers no penalty. single accesses not followed by a hit in the page look like non-page-mode accesses. figure 11-9 shows a write cycle followed by a read cycle in continuous page mode. the read hits in the same page as the write so ras is not negated before the second cycle. note that the row address does not appear on the pins for a bus cycle that hits in the page. column addresses are immediately multiplexed onto the pins. the third bus cycle is a page miss, so ras is precharged before the end of the bus cycle and no extra precharge delay is incurred. figure 11-9. continuous page-mode operation if a write cycle hits in the page, cas must be delayed by one clock to allow data to become valid, as shown in figure 11-10. a[31:0] ras [1] or [0] cas [3:0] dramw d[31:0] rcd=0 rncn=1 cas=01 bus cycle 1 bus cycle 2 bus cycle 3 page hit page miss row column column row column bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-15 asynchronous operation figure 11-10. write hit in continuous page mode 11.3.3.4 extended data out (edo) operation edo is a variation of page mode that allows the dram to continue driving data out of the device while cas is precharging. to support edo drams, the dram controller delays internal termination of the cycle by one clock so data can continue to be captured as cas is being precharged. for data to be driven by the drams, ras is held after cas is negated. edo operation does not affect write operations. edo drams can be used in continuous page or burst page modes. single accesses not followed by a hit in the page look like non-page-mode accesses. figure 11-11 shows four consecutive edo accesses. note that data is sampled after cas is negated and that on the last page access, cas is held until after data is sampled to assure that the data is driven. this allows ras to be precharged before the end of the cycle. figure 11-11. edo read operation (3-2-2-2) a[31:0] ras [1] or [0] cas [3:0] dramw d[31:0] rcd = 0 cas = 01 bus cycle 1 bus cycle 2 page hit page miss row column column bclko a[31:0] ras [1] or [0] cas [3:0] dramw d[31:0] rcd = 0 cas = 00 bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-16 mcf5307 users manual synchronous operation 11.3.3.5 refresh operation the dram controller supports cas -before-ras refresh operations that are not synchronized to bus activity. a special dramw pin is provided so refresh can occur regardless of the state of the processor bus. when the refresh counter rolls over, it sets an internal ag to indicate that a refresh is pending. if that happens during a continuous page-mode access, the page is closed (ras precharged) when the data transfer completes to allow the refresh to occur. the ag is cleared when the refresh cycle is run. both memory blocks are simultaneously refreshed as determined by the dcr. dram accesses are delayed during refresh. only an active bus access to a dram block can delay refresh. figure 11-12 shows a bus cycle delayed by a refresh operation. notice that dramw is forced high during refresh. the row address is held until the pending dram access. figure 11-12. dram access delayed by refresh 11.4 synchronous operation by running synchronously with the system clock instead of responding to asynchronous control signals, sdram can (after an initial latency period) be accessed on every clock; 5-1-1-1 is a typical mcf5307 burst rate to sdram. note that because the mcf5307 cannot have more than one page open at a time, it does not support interleaving. sdram controllers are more sophisticated than asynchronous dram controllers. not only must they manage addresses and data, but they must send special commands for such functions as precharge, read, write, burst, auto-refresh, and various combinations of these functions. table 11-10 lists common sdram commands. a[31:0] ras [1] or [0] cas [3:0] dramw rra = 01 rrp = 01 bclko refresh access f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-17 synchronous operation sdrams operate differently than asynchronous drams, particularly in the use of data pipelines and commands to initiate special actions. commands are issued to memory using speci c encodings on address and control pins. soon after system reset, a command must be sent to the sdram mode register to con gure sdram operating parameters. note that, after synchronous operation is selected by setting dcr[so], dram controller registers re ect the synchronous operation and there is no way to return to asynchronous operation without resetting the processor. 11.4.1 dram controller signals in synchronous mode table 11-11 shows the behavior of dram signals in synchronous mode. table 11-10. sdram commands command de?ition actv activate. executed before read or write executes; sdram registers and decodes row address. mrs mode register set. nop no-op. does not affect sdram state machine; dram controller control signals negated; ras asserted. pall precharge all. precharges all internal banks of an sdram component; executed before new page is opened. read read access. sdram registers column address and decodes that a read access is occurring. ref refresh. refreshes internal bank rows of an sdram component. self self refresh. refreshes internal bank rows of an sdram component when it is in low-power mode. selfx exit self refresh. this command is sent to the dram controller when dcr[is] is cleared. write write access. sdram registers column address and decodes that a write access is occurring. table 11-11. synchronous dram signal connections signal description sras synchronous row address strobe. indicates a valid sdram row address is present and can be latched by the sdram. sras should be connected to the corresponding sdram sras . do not confuse sras with the dram controller s ras [1:0], which should not be interfaced to the sdram sras signals. scas synchronous column address strobe. indicates a valid column address is present and can be latched by the sdram. scas should be connected to the corresponding signal labeled scas on the sdram. do not confuse scas with the dram controller s cas [3:0] signals. dramw dram read/write. asserted for write operations and negated for read operations. ras [1:0] row address strobe. select each memory block of sdrams connected to the mcf5307 . one ras signal selects one sdram block and connects to the corresponding cs signals. scke synchronous dram clock enable. connected directly to the cke (clock enable) signal of sdrams. enables and disables the clock internal to sdram. when cke is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. scke functionality is controlled by dcr[coc]. for designs using external multiplexing, setting coc allows scke to provide command-bit functionality. cas [3:0] column address strobe. for synchronous operation, cas [3:0] function as byte enables to the sdrams. they connect to the dqm signals (or mask quali ers) of the sdrams. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-18 mcf5307 users manual synchronous operation figure 11-13 shows a typical signal con guration for synchronous mode. figure 11-13. mcf5307 sdram interface 11.4.2 using edge select (edgesel) edgesel can ease system-level timings (note that the optional buffer in figure 11-13 is for memories that need extra delay). the clock at the input to the sdram is monitored and data is held until the next edge of the bus clock, adding required output hold time to the address, data, and control signals. to generate sdram interface timing, address, data, and control signals are clocked through a two-stage shift register. the rst stage is clocked on the rising edge of bclko; the second is clocked on the falling edge. this makes the signal available for up to an additional half bus clock cycle, of which only a small amount is needed for proper timing. using the connection shown in figure 11-13 ensures that data remains held for a longer time after the rising edge of the sdram clock input. this helps to match the mcf5307 output timing with the sdram clock. figure 11-14 shows the output wave forms for the interface signals changing on the rising edge (a) and falling edge (b) of bclko as determined by whether edgesel is tied high or low. it also shows timing (c) with edgesel tied to buffered bclko. bclko bus clock output. connects to the clk input of sdrams. edgesel synchronous edge select. provides additional output hold time for signals that interface to external sdrams. edgesel supports the three following modes for sdram interface signals: tied high. signals change on the rising edge of bclko. tied low. signals change on the falling edge of bclko. tied to buffered bclko. signals change on the rising edge of the buffered clock. edgesel can provide additional output hold time for sdram interface signals, however the sdram clock and bclko frequencies must be the same. see section 11.4.2, using edge select (edgesel). table 11-11. synchronous dram signal connections (continued) signal description edgesel a[31:0] cas dramw scas sras scke cke cas ras dqm we address data clk mcf5307 bclko d[31:0] sdram 1 trace length from buffer to clk must equal length from buffer to edgesel. 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-19 synchronous operation figure 11-14. using edgesel to change signal timing 11.4.3 synchronous register set the memory map in table 11-1 is the same for both synchronous and asynchronous operation. however, some bits are different, as noted in the following sections. 11.4.3.1 dram control register (dcr) in synchronous mode the dram control register (dcr), figure 11-15, controls refresh logic. table 11-12 describes dcr elds. 1514131211109876543210 field so nam coc is rtim rc reset 0 uninitialized r/w r/w addr mbar + 0x100 figure 11-15. dram control register (dcr) (synchronous mode) table 11-12. dcr field descriptions (synchronous mode) bits name description 15 so synchronous operation. selects synchronous or asynchronous mode. when in synchronous mode, the dram controller can be switched to adram mode only by resetting the mcf5307. 0 asynchronous drams. default at reset. 1 synchronous drams 14 reserved, should be cleared. 13 nam no address multiplexing. some implementations require external multiplexing. for example, when linear addressing is required, the dram should not multiplex addresses on dram accesses. 0 the dram controller multiplexes the external address bus to provide column addresses. 1 the dram controller does not multiplex the external address bus to provide column addresses. valid valid valid valid bclko address/ valid valid valid buffered valid valid valid valid a: address and data timing with edgesel tied high b: address and data timing with edgesel tied low data address/ data c: address and data timing with edgesel tied to buffered clock address/ data bclko buffer delay bclko bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-20 mcf5307 users manual synchronous operation 11.4.3.2 dram address and control registers (dacr0/dacr1) in synchronous mode the dram address and control registers (dacr0 and dacr1), shown in figure 11-16, contain the base address compare value and the control bits for both memory blocks 0 and 1 of the dram controller. address and timing are also controlled by bits in dacr n . 12 coc command on sdram clock enable (scke). implementations that use external multiplexing (nam = 1) must support command information to be multiplexed onto the sdram address bus. 0 scke functions as a clock enable; self-refresh is initiated by the dram controller through dcr[is]. 1 scke drives command information. because scke is not a clock enable, self-refresh cannot be used (setting dcr[is]). thus, external logic must be used if this functionality is desired. external multiplexing is also responsible for putting the command information on the proper address bit. 11 is initiate self-refresh command. 0 take no action or issue a selfx command to exit self refresh. 1 if dcr[coc] = 0, the dram controller sends a self command to both sdram blocks to put them in low-power, self-refresh state where they remain until is is cleared, at which point the controller sends a selfx command for the sdrams to exit self-refresh. the refresh counter is suspended while the sdrams are in self-refresh; the sdram controls the refresh period. 10 9 rtim refresh timing. determines the timing operation of auto-refresh in the dram controller. speci cally, it determines the number of clocks inserted between a ref command and the next possible actv command. this same timing is used for both memory blocks controlled by the dram controller. this corresponds to t rc in the sdram speci cations. 00 3 clocks 01 6 clocks 1x 9 clocks 8 0 rc refresh count. controls refresh frequency. the number of bus clocks between refresh cycles is (rc + 1) * 16. refresh can range from 16 8192 bus clocks to accommodate both standard and low-power drams with bus clock operation from less than 2 mhz to greater than 50 mhz. the following example calculates rc for an auto-refresh period for 4096 rows to receive 64 ms of refresh every 15.625 s for each row (625 bus clocks at 40 mhz). this operation is the same as in asynchronous mode. # of bus clocks = 625 = (rc eld + 1) * 16 rc = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, rc = 0x26. 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field ba re casl cbm imrs ps ip pm reset uninitialized 0 uninitialized 0 uninitialized r/w r/w addr mbar+0x108 (dacr0); 0x110(dacr1) figure 11-16. dacr0 and dacr1 registers (synchronous mode) table 11-12. dcr field descriptions (synchronous mode) (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-21 synchronous operation table 11-13 describes dacr n elds. table 11-13. dacr0/dacr1 field descriptions (synchronous mode) bit name description 31 18 ba base address register. with dcmr[bam], determines the address range in which the associated dram block is located. each ba bit is compared with the corresponding address of the current bus cycle. if all unmasked bits match, the address hits in the associated dram block. ba functions the same as in asynchronous operation. 17 16 reserved, should be cleared. 15 re refresh enable. determines when the dram controller generates a refresh cycle to the dram block. 0 do not refresh associated dram block 1 refresh associated dram block 14 reserved, should be cleared. 13 12 casl cas latency. affects the following sdram timing speci cations. timing nomenclature varies with manufacturers. refer to the sdram speci cation for the appropriate timing nomenclature: parameter number of bus clocks casl= 00 casl = 01 casl= 10 casl= 11 t rcd sras assertion to scas assertion 1 2 3 3 t casl scas assertion to data out 1 2 3 3 t ras actv command to precharge command 2 4 6 6 t rp precharge command to actv command 1 2 3 3 t rwl , t rdl last data input to precharge command 1111 t ep last data out to precharge command) 1 1 1 1 11 reserved, should be cleared. 10 8 cbm command and bank mux [2:0]. because different sdram con gurations cause the command and bank select lines to correspond to different addresses, these resources are programmable. cbm determines the addresses onto which these functions are multiplexed. cbm command bit bank select bits 000 17 18 and up 001 18 19 and up 010 19 20 and up 011 20 21 and up 100 21 22 and up 101 22 23 and up 110 23 24 and up 111 24 25 and up this encoding and the address multiplexing scheme handle common sdram organizations. bank select bits include a base bit and all address bits above for sdrams with multiple bank select bits. 7 reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-22 mcf5307 users manual synchronous operation 11.4.3.3 dram controller mask registers (dmr0/dmr1) the dmr n , figure 11-17, include mask bits for the base address and for address attributes. they are the same as in asynchronous operation. table 11-14 describes dmr n elds. 6 imrs initiate mode register set ( mrs ) command. setting imrs generates a mrs command to the associated sdrams. in initialization, imrs should be set only after all dram controller registers are initialized and pall and refresh commands have been issued. after imrs is set, the next access to an sdram block programs the sdram s mode register. thus, the address of the access should be programmed to place the correct mode information on the sdram address pins. because the sdram does not register this information, it doesn t matter if the imrs access is a read or a write or what, if any, data is put onto the data bus. the dram controller clears imrs after the mrs command nishes. 0 take no action 1 initiate mrs command 5 4 ps port size. indicates the port size of the associated block of sdram, which allows for dynamic sizing of associated sdram accesses. ps functions the same in asynchronous operation. 00 32-bit port 01 8-bit port 1x 16-bit port 3 ip initiate precharge all ( pall ) command. the dram controller clears ip after the pall command is nished. accesses via ip should be no wider than the port size programmed in ps. 0 take no action. 1a pall command is sent to the associated sdram block. during initialization, this command is executed after all dram controller registers are programmed. after ip is set, the next write to an appropriate sdram address generates the pall command to the sdram block. 2 pm page mode. indicates how the associated sdram block supports page-mode operation. 0 page mode on bursts only. the dram controller dynamically bursts the transfer if it falls within a single page and the transfer size exceeds the port size of the sdram block. after the burst, the page closes and a precharge is issued. 1 continuous page mode. the page stays open and only scas needs to be asserted for sequential sdram accesses that hit in the same page, regardless of whether the access is a burst. 1 0 reserved, should be cleared. 31 1817 9876543210 field bam wp c/i am sc sd uc ud v reset uninitialized 0 r/w r/w addr mbar + 0x10c (dmr0), 0x114 (dmr1) figure 11-17. dram controller mask registers (dmr0 and dmr1) table 11-13. dacr0/dacr1 field descriptions (synchronous mode) (continued) bit name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-23 synchronous operation 11.4.4 general synchronous operation guidelines to reduce system logic and to support a variety of sdram sizes, the dram controller provides sdram control signals as well as a multiplexed row address and column address to the sdram. when sdram blocks are accessed, the dram controller can operate in either burst or continuous page mode. the following sections describe the dram controller interface to sdram, the supported bus transfers, and initialization. 11.4.4.1 address multiplexing table 11-6 shows the generic address multiplexing scheme for sdram con gurations. all possible address connection con gurations can be derived from this table. the following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the mcf5307 to sdram. to use the table 11-14. dmr0/dmr1 field descriptions bits name description 31 18 bam base address mask. masks the associated dacr n [ba]. lets the dram controller connect to various dram sizes. mask bits need not be contiguous (see section 11.5, sdram example. ) 0 the associated address bit is used in decoding the dram hit to a memory block. 1 the associated address bit is not used in the dram hit decode. 17 9 reserved, should be cleared. 8 wp write protect. determines whether the associated block of dram is write protected. 0 allow write accesses 1 ignore write accesses. the dram controller ignores write accesses to the memory block and an address exception occurs. write accesses to a write-protected dram region are compared in the chip select module for a hit. if no hit occurs, an external bus cycle is generated. if this external bus cycle is not acknowledged, an access exception occurs. 7 reserved, should be cleared. 6 1am x address modi er masks. determine which accesses can occur in a given dram block. 0 allow access type to hit in dram 1 do not allow access type to hit in dram bit associated access type access de?ition c/i cpu space/interrupt acknowledge movec instruction or interrupt acknowledge cycle am alternate master external or dma master sc supervisor code any supervisor-only instruction access sd supervisor data any data fetched during the instruction access uc user code any user instruction ud user data any user data 0 v valid. cleared at reset to ensure that the dram block is not erroneously decoded. 0 do not decode dram accesses. 1 registers controlling the dram block are initialized; dram accesses can be decoded. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-24 mcf5307 users manual synchronous operation tables, nd the one that corresponds to the number of column address lines on the sdram and to the port size as seen by the mcf5307, which is not necessarily the sdram port size. for example, if two 1m x 16-bit sdrams together form a 2m x 32-bit memory, the port size is 32 bits. most sdrams likely have fewer address lines than are shown in the tables, so follow only the connections shown until all sdram address lines are connected. table 11-15. mcf5307 to sdram interface (8-bit port, 9-column address lines) mcf5307 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 1819202122232425262728293031 column 012345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 table 11-16. mcf5307 to sdram interface (8-bit port,10-column address lines) mcf5307 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 19202122232425262728293031 column 01234567818 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 11-17. mcf5307 to sdram interface (8-bit port,11-column address lines) mcf5307 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 192122232425262728293031 column 0123456781820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 table 11-18. mcf5307 to sdram interface (8-bit port,12-column address lines) mcf5307 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 1921232425262728293031 column 012345678182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-25 synchronous operation table 11-19. mcf5307 to sdram interface (8-bit port,13-column address lines) mcf5307 pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 a25 a26 a27 a28 a29 a30 a31 row 1716151413121110 9 19212325262728293031 column 01234567818202224 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 11-20. mcf5307 to sdram interface (16-bit port, 8-column address lines) mcf5307 pins a16 a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16151413121110 9 171819202122232425262728293031 column 12345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 table 11-21. mcf5307 to sdram interface (16-bit port, 9-column address lines) mcf5307 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16151413121110 9 1819202122232425262728293031 column 1234567817 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 11-22. mcf5307 to sdram interface (16-bit port, 10-column address lines) mcf5307 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16151413121110 9 18202122232425262728293031 column 123456781719 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 table 11-23. mcf5307 to sdram interface (16-bit port, 11-column address lines) mcf5307 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 16151413121110 9 182022232425262728293031 column 12345678171921 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-26 mcf5307 users manual synchronous operation table 11-24. mcf5307 to sdram interface (16-bit port, 12-column address lines) mcf5307 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a24 a25 a26 a27 a28 a29 a30 a31 row 16151413121110 9 1820222425262728293031 column 1234567817192123 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 11-25. mcf5307to sdram interface (16-bit port, 13-column-address lines) mcf5307 pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a24 a26 a27 a28 a29 a30 a31 row 16151413121110 9 18202224262728293031 column 123456781719212325 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 table 11-26. mcf5307 to sdram interface (32-bit port, 8-column address lines) mcf5307 pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 171819202122232425262728293031 column 234567816 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 table 11-27. mcf5307 to sdram interface (32-bit port, 9-column address lines) mcf5307 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 1719202122232425262728293031 column 23456781618 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 table 11-28. mcf5307 to sdram interface (32-bit port, 10-column address lines) mcf5307 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 17192122232425262728293031 column 2345678161820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-27 synchronous operation 11.4.4.2 interfacing example the tables in the previous section can be used to con gure the interface in the following example. to interface one 2m x 32-bit x 4 bank sdram component (8 columns) to the mcf5307, the connections would be as shown in table 11-31. 11.4.4.3 burst page mode sdram can ef ciently provide data when an sdram page is opened. as soon as scas is issued, the sdram accepts a new address and asserts scas every clock for as long as accesses are in that page. in burst page mode, there are multiple read or write operations for every actv command in the sdram if the requested transfer size exceeds the port size of the associated sdram. the primary cycle of the transfer generates the actv and read or write commands; secondary cycles generate only read or write commands. as soon as the transfer completes, the pall command is generated to prepare for the next access. note that in synchronous operation, burst mode and address incrementing during burst cycles are controlled by the mcf5307 dram controller. thus, instead of the sdram enabling its internal burst incrementing capability, the mcf5307 controls this function. this means that the burst function that is enabled in the mode register of sdrams must be disabled when interfacing to the mcf5307. figure 11-18 shows a burst read operation. in this example, dacr[casl] = 01, for an sras -to-scas delay (t rcd ) of 2 bclko cycles. because t rcd is equal to the read cas table 11-29. mcf5307 to sdram interface (32-bit port, 11-column address lines) mcf5307 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 a24 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 171921232425262728293031 column 234567816182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 table 11-30. mcf5307 to sdram interface (32-bit port, 12-column address lines) mcf5307 pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 a25 a26 a27 a28 a29 a30 a31 row 151413121110 9 1719212325262728293031 column 23456781618202224 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 table 11-31. sdram hardware connections sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 = cmd ba0 ba1 mcf5307 pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-28 mcf5307 users manual synchronous operation latency (scas assertion to data out), this value is also 2 bclko cycles. notice that nop s are executed until the last data is read. a pall command is executed one cycle after the last data transfer. figure 11-18. burst read sdram access figure 11-19 shows the burst write operation. in this example, dacr[casl] = 01, which creates an sras -to-scas delay (t rcd ) of 2 bclko cycles. note that data is available upon scas assertion and a burst write cycle completes two cycles sooner than a burst read cycle with the same t rcd. the next bus cycle is initiated sooner, but cannot begin an sdram cycle until the precharge-to- actv delay completes. a[31:0] sras scas dramw d[31:0] t casl = 2 actv read nop nop ras [0] or [1] cas [3:0] nop pall row column column column column t rcd = 2 t ep bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-29 synchronous operation figure 11-19. burst write sdram access accesses in synchronous burst page mode always cause the following sequence: 1. actv command 2. nop commands to assure sras -to-scas delay (if cas latency is 1, there are no nop commands). 3. required number of read or write commands to service the transfer size with the given port size. 4. some transfers need more nop commands to assure the actv -to-precharge delay. 5. pall command 6. required number of idle clocks inserted to assure precharge-to- actv delay. 11.4.4.4 continuous page mode continuous page mode is identical to burst page mode, except that it allows the processor core to handle successive bus cycles that hit the same page without having to close the page. when the current bus cycle nishes, the mcf5307 core internal pipelined bus can predict whether the upcoming cycle will hit in the same page. if the next bus cycle is not pending or misses in the page, the pall command is generated to the sdram. if the next bus cycle is pending and hits in the page, the page is left open, and the next sdram access begins with a read or write command. a[31:0] s ras s cas dram w d[31:0] actv write pall nop ras [0] or [1] cas [3:0] t casl = 2 row column column column column t rp t rwl bclko nop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-30 mcf5307 users manual synchronous operation because of the nature of the internal cpu pipeline this condition does not occur often; however, the use of continuous page mode is recommended because it can provide a slight performance increase. figure 11-20 shows two read accesses in continuous page mode. note that there is no precharge between the two accesses. also notice that the second cycle begins with a read operation with no actv command. figure 11-20. synchronous, continuous page-mode access?onsecutive reads figure 11-21 shows a write followed by a read in continuous page mode. because the bus cycle is terminated with a write command, the second cycle begins sooner after the write than after the read. a read requires data to be returned before the bus cycle can terminate. note that in continuous page mode, secondary accesses output the column address only. a[31:0] sras scas dramw d[31:0] actv nop read nop ras [0] or [1] cas [3:0] read nop nop pall t casl = 2 t rcd = 2 t casl = 2 t ep row column column bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-31 synchronous operation figure 11-21. synchronous, continuous page-mode access?ead after write 11.4.4.5 auto-refresh operation the dram controller is equipped with a refresh counter and control. this logic is responsible for providing timing and control to refresh the sdram. once the refresh counter is set, and refresh is enabled, the counter counts to zero. at this time, an internal refresh request ag is set and the counter begins counting down again. the dram controller completes any active burst operation and then performs a pall operation. the dram controller then initiates a refresh cycle and clears the refresh request ag. this refresh cycle includes a delay from any precharge to the auto-refresh command, the auto-refresh command, and then a delay until any actv command is allowed. any sdram access initiated during the auto-refresh cycle is delayed until the cycle is completed. figure 11-22 shows the auto-refresh timing. in this case, there is an sdram access when the refresh request becomes active. the request is delayed by the precharge to actv delay programmed into the active sdram bank by the cas bits. the ref command is then generated and the delay required by dcr[rtim] is inserted before the next actv command is generated. in this example, the next bus cycle is initiated, but does not generate an sdram access until t rc is nished. because both chip selects are active during the ref command, it is passed to both blocks of external sdram. a[31:0] sras scas dramw d[31:0] actv nop read nop ras [0] or [1] cas [3:0] write nop nop nop pall row column column t casl = 3 t rcd = 3 t ep bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-32 mcf5307 users manual synchronous operation figure 11-22. auto-refresh operation 11.4.4.6 self-refresh operation self-refresh is a method of allowing the sdram to enter into a low-power state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the sdram. the dram controller supports self-refresh with dcr[is]. when is is set, the self command is sent to the sdram. when is is cleared, the selfx command is sent to the dram controller. figure 11-23 shows the self-refresh operation. figure 11-23. self-refresh operation a[31:0] sras scas dramw pall nop nop ras [0] or [1] ref actv t rcd = 2 t rc = 6 bclko sras scas dramw pall nop nop ras [0] or [1] self first scke possible actv selfx self- refresh active t rcd = 2 t rc = 6 bclko (dcr[coc] = 0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-33 synchronous operation 11.4.5 initialization sequence synchronous drams have a prescribed initialization sequence. the dram controller supports this sequence with the following procedure: 1. sdram control signals are reset to idle state. wait the prescribed period after reset before any action is taken on the sdrams. this is normally around 100 s. 2. initialize the dcr, dacr, and dmr in their operational con guration. do not yet enable pall or ref commands. 3. issue a pall command to the sdrams by setting dcr[ip] and accessing a sdram location. wait the time (determined by t rp ) before any other execution. 4. enable refresh (set dacr[re]) and wait for at least 8 refreshes to occur. 5. before issuing the mrs command, determine if the dmr mask bits need to be modi ed to allow the mrs to execute properly 6. issue the mrs command by setting dacr[imrs] and accessing a location in the sdram. note that mode register settings are driven on the sdram address bus, so care must be taken to change dmr[bam] if the mode register con guration does not fall in the address range determined by the address mask bits. after the mode register is set, dmr mask bits can be restored to their desired con guration. 11.4.5.1 mode register settings it is possible to con gure the operation of sdrams, namely their burst operation and cas latency, through the sdram component?s mode register. cas latency is a function of the speed of the sdram and the bus clock of the dram controller. the dram controller operates at a cas latency of 1, 2, or 3. although the mcf5307 dram controller supports bursting operations, it does not use the bursting features of the sdrams. because the mcf5307 can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a xed burst length in the sdrams mode register becomes problematic. therefore, the mcf5307 dram controller generates the burst cycles rather than the sdram device. because the mcf5307 generates a new address and a read or write command for each transfer within the burst, the sdram mode register should be set either to a burst length of one or to not burst. this allows bursting to be controlled by the mcf5307 instead. the sdram mode register is written by setting the associated block?s dacr[imrs]. first, the base address and mask registers must be set to the appropriate con guration to allow the mode register to be set. note that improperly set dmr mask bits may prevent access to the mode register address. thus, the user should determine the mapping of the mode register address to the mcf5307 address bits to nd out if an access is blocked. if the dmr setting prohibits mode register access, the dmr should be recon gured to enable the access and then set to its necessary con guration after the mrs command executes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-34 mcf5307 users manual sdram example the associated cbm bits should also be initialized. after dacr[imrs] is set, the next access to the sdram address space generates the mrs command to that sdram. the address of the access should be selected to place the correct mode information on the sdram address pins. the address is not multiplexed for the mrs command. the mrs access can be a read or write. the important thing is that the address output of that access needs the correct mode programming information on the correct address bits. figure 11-24 shows the mrs command, which occurs in the rst clock of the bus cycle. figure 11-24. mode register set ( mrs ) command 11.5 sdram example this example interfaces a 2m x 32-bit x 4 bank sdram component to a mcf5307 operating at 40 mhz. table 11-32 lists design speci cations for this example. table 11-32. sdram example specifications parameter speci?ation speed grade (-8e) 40 mhz (25-ns period) 10 rows, 8 columns two bank-select lines to access four internal banks actv -to-read/write delay (t rcd ) 20 ns (min.) period between auto refresh and actv command (t rc ) 70 ns actv command to precharge command (t ras ) 48 ns (min.) precharge command to actv command (t rp ) 20 ns (min.) last data input to pall command (t rwl ) 1 bus clock (25 ns) auto refresh period for 4096 rows (t ref ) 64 ms a[31:0] sras , scas dramw d[31:0] mrs ras [1] or [0] bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-35 sdram example 11.5.1 sdram interface con?uration to interface this component to the mcf5307 dram controller, use the connection table that corresponds to a 32-bit port size with 8 columns (table 11-26). two pins select one of four banks when the part is functional. table 11-33 shows the proper hardware hook-up. 11.5.2 dcr initialization at power-up, the dcr has the following con guration if synchronous operation and sdram address multiplexing is desired. this con guration results in a value of 0x8026 for dcr, as shown in table 11-34. 11.5.3 dacr initialization as shown in figure 11-26, in this example the sdram is programmed to access only the second 512-kbyte block of each 1-mbyte partition in the sdram (each 16 mbytes). the starting address of the sdram is 0xff80_0000. continuous page mode feature is used. table 11-33. sdram hardware connections mcf5307 pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 = cmd ba0 ba1 15 14 13 12 11 10 9 8 0 field so res nam coc is rtim rc setting 1 x 00000000100110 (hex)8026 figure 11-25. initialization values for dcr table 11-34. dcr initialization values bits name setting description 15 so 1 indicating synchronous operation 14 x don t care (reserved) 13 nam 0 indicating sdram controller multiplexes address lines internally 12 coc 0 scke is used as clock enable instead of command bit because user is not multiplexing address lines externally and requires external command feed. 11 is 0 at power-up, allowing power self-refresh state is not appropriate because registers are being set up. 10 9 rtim 00 because t rc value is 70 ns, indicating a 3-clock refresh-to- actv timing. 8 0 rc 0x26 speci cation indicates auto-refresh period for 4096 rows to be 64 ms or refresh every 15.625 s for each row, or 625 bus clocks at 40 mhz. because dcr[rc] is incremented by 1 and multiplied by 16, rc = (625 bus clocks/16) -1 = 38.06 = 0x38 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-36 mcf5307 users manual sdram example figure 11-26. sdram configuration the dacrs should be programmed as shown in figure 11-27. this con guration results in a value of dacr0 = 0xff88_0304, as described in table 11-35. dacr1 initialization is not needed because there is only one block. subsequently, dacr1[re,imrs,ip] should be cleared; everything else is a don?t care. 31 18 17 16 field ba setting 1111_1111_1000_10 xx (hex) 15 15 8 8 151413121110 876543210 field re casl cbm imrs ps ip pm setting 0 x 00 x 011 x 0 00 0 1 xx (hex) 0 3 0 4 figure 11-27. dacr register configuration table 11-35. dacr initialization values bits name setting description 31 18 ba base address. so dacr0[31 16] = 0xff88, which places the starting address of the sdram accessible memory at 0xff88_0000. 17 16 reserved. don t care. 15 re 0 0, which keeps auto-refresh disabled because registers are being set up at this time. 14 reserved. don t care. 13 12 casl 00 indicates a delay of data 1 cycle after cas is asserted 11 reserved. don t care. 10 8 cbm 011 command bit is pin 20 and bank selects are 21 and up. 7 reserved. don t care. 6 imrs 0 indicates mrs command has not been initiated. 5 4 ps 00 32-bit port. 3 ip 0 indicates precharge has not been initiated. bank 0 1 mbyte 512 kbyte 512 kbyte sdram component accessible memory bank 1 1 mbyte 512 kbyte 512 kbyte bank 2 1 mbyte 512 kbyte 512 kbyte bank 3 1 mbyte 512 kbyte 512 kbyte f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-37 sdram example 11.5.4 dmr initialization in this example, again, only the second 512-kbyte block of each 1-mbyte space is accessed in each bank. in addition the sdram component is mapped only to readable and writable supervisor and user data. the dmrs have the following con guration. with this con guration, the dmr0 = 0x0074_0075, as described in table 11-36. 2 pm 1 indicates continuous page mode 1 0 reserved. don t care. 31 18 17 16 field bam setting 00000000011101xx (hex) 0 0 7 4 15 9876543210 field wp c/i am sc sd uc ud v setting xxxxxx x0x1110101 (hex)0075 figure 11-28. dmr0 register table 11-36. dmr0 initialization values bits name setting description 31 16 bam with bits 17 and 16 as don t cares, bam = 0x0074, which leaves bank select bits and upper 512k select bits unmasked. note that bits 22 and 21 are set because they are used as bank selects; bit 20 is set because it controls the 1-mbyte boundary address. 15 9 reserved. don t care. 8 wp 0 allow reads and writes 7 reserved 6 c/i 1 disable cpu space access 5 am 1 disable alternate master access 4 sc 1 disable supervisor code accesses 3 sd 0 enable supervisor data accesses 2 uc 1 disable user code accesses 1 ud 0 enable user data accesses 0 v 1 enable accesses. table 11-35. dacr initialization values bits name setting description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-38 mcf5307 users manual sdram example 11.5.5 mode register initialization when dacr[imrs] is set, a bus cycle initializes the mode register. if the mode register setting is read on a[10:0] of the sdram on the rst bus cycle, the bit settings on the corresponding mcf5307 address pins must be determined while being aware of masking requirements. table 11-37 lists the desired initialization setting: next, this information is mapped to an address to determine the hexadecimal value. although a[31:20] corresponds to the address programmed in dacr0, according to how dacr0 and dmr0 are initialized, bit 19 must be set to hit in the sdram. thus, before the mode register bit is set, dmr0[19] must be set to enable masking. table 11-37. mode register initialization mcf5307 pins sdram pins mode register initialization a20 a10 reserved x a19 a9 wb 0 a18 a8 opmode 0 a17 a7 opmode 0 a9 a6 casl 0 a10 a5 casl 0 a11 a4 casl 1 a12 a3 bt 0 a13 a2 bl 0 a14 a1 bl 0 a15 a0 bl 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field setting xxxxxxxxxxxx0 0 0x (hex)0000 1514131211109876543210 field v setting 0000100 xxxxxxxxx (hex)0800 figure 11-29. mode register mapping to mcf5307 a[31:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 11. synchronous/asynchronous dram controller module 11-39 sdram example 11.5.6 initialization code the following assembly code initializes the sdram example. power-up sequence: move.w #0x8026, d0 //initialize dcr move.w d0, dcr move.l #0xff880300, d0 //initialize dacr0 move.l d0, dacr0 move.l #0x00740075, d0 //initialize dmr0 move.l d0, dmr0 precharge sequence: move.l #0xff880308, d0 //set dacr0[ip] move.l d0, dacr0 move.l #0xbeaddeed, d0 //write to memory location to init. precharge move.l d0, 0xff880000 refresh sequence: move.l #0xff888300, d0 //enable refresh bit in dacr0 move.l d0, dacr0 mode register initialization sequence: move.l #0x00600075, d0 //mask bit 19 of address move.l d0, dmr0 move.l #0xff888340, d0 //enable dacr0[imrs]; dacr0[re] remains set move.l d0, dacr0 move.l #0x00000000, d0 //access sdram address to initialize mode register move.l d0, 0xff800800 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
11-40 mcf5307 users manual sdram example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
part iii. peripheral module iii-i part iii peripheral module intended audience part iii describes the operation and con guration of the mcf5307 dma, timer, uart, and parallel port modules, and describes how they interface with the system integration unit, described in part ii. contents part iii contains the following chapters: chapter 12, ?dma controller module,? provides an overview of the dma controller module and describes in detail its signals and registers. the latter sections of this chapter describe operations, features, and supported data transfer modes in detail, showing timing diagrams for various operations. chapter 13, ?timer module,? describes con guration and operation of the two general-purpose timer modules, timer 0 and timer 1. it includes programming examples. chapter 14, ?uart modules,? describes the use of the universal asynchronous/synchronous receiver/transmitters (uarts) implemented on the mcf5307 and includes programming examples. chapter 15, ?parallel port (general-purpose i/o),? describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. it includes a code example for setting up the parallel port. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iii-ii mcf5307 users manual acronyms and abbreviations table iii-i describes acronyms and abbreviations used in part iii. table iii-i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion bist built-in self test codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing edo extended data output (dram) fifo first-in, rst-out gpio i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ifp instruction fetch pipeline ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lifo last-in, rst-out lru least recently used lsb least-signi cant byte lsb least-signi cant bit mac multiple accumulate unit mbar memory base address register msb most-signi cant byte msb most-signi cant bit mux multiplex nop no operation oep operand execution pipeline pc program counter pclk processor clock pll phase-locked loop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
part iii. peripheral module iii-iii plru pseudo least recently used por power-on reset pqfp plastic quad at pack risc reduced instruction set computing rx receive sim system integration module sof start of frame tap test access port ttl transistor-to-transistor logic tx transmit uart universal asynchronous/synchronous receiver transmitter table iii-i. acronyms and abbreviated terms (continued) term meaning f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iii-iv mcf5307 users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-1 chapter 12 dma controller module this chapter describes the mcf5307 dma controller module. it provides an overview of the module and describes in detail its signals and registers. the latter sections of this chapter describe operations, features, and supported data transfer modes in detail. 12.1 overview the direct memory access (dma) controller module provides an ef cient way to move blocks of data with minimal processor interaction. the dma module, shown in figure 12-1, provides four channels that allow byte, word, or longword operand transfers. each channel has a dedicated set of registers that de ne the source and destination addresses (sar n and dar n ), byte count (bcr n ), and control and status (dcr n and dsr n ). transfers can be dual or single address to off-chip devices or dual address to on-chip devices, such as uart, sdram controller, and parallel port. figure 12-1. dma signal diagram mux arbitration/ interface bus data path control internal external channel channel mux registered data path sar0 dar0 bcr0 dcr0 dsr0 channel 0 interrupts sar1 dar1 bcr1 dcr1 dsr1 channel 1 sar2 dar2 bcr2 dcr2 dsr2 channel 2 sar3 dar3 bcr3 dcr3 dsr3 channel 3 bus requests attributes current master attributes write bus data read bus data external bus address external bus size channel enables requests bus signals control control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-2 mcf5307 users manual dma signal description 12.1.1 dma module features the dma controller module features are as follows: four fully independent, programmable dma controller channels/bus modules auto-alignment feature for source or destination accesses dual- and single-address transfers two external request pins (dreq [1:0]) provided for channels 1 and 0 channel arbitration on transfer boundaries data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer continuous-mode and cycle-steal transfers independent transfer widths for source and destination independent source and destination address registers data transfer can occur in as few as two clocks 12.2 dma signal description table 12-1 brie y describes the dma module signals that provide handshake control for either a source or destination external device. table 12-1. dma signals signal i/o description dreq [1:0]/ pp[6:5] i external dma request. dreq [1:0] can serve as the dma request inputs or as two parallel port bits. they are programmable individually through the par. a peripheral device asserts these inputs to request an operand transfer between it and memory. dreq signals are asserted to initiate dma accesses in the respective channels. the system should drive unused dreq signals to logic high. although each channel has an individual dreq signal, in the mcf5307 only channels 0 and 1 connect to external dreq pins.dreq signals for channels 2 and 3 are connected to the uart0 and uart1 bus interrupt signals. tt[1:0]/ pp[1:0] o transfer type. a dma access is indicated by the transfer type pins, tt[1:0] = 01. the transfer modi er, tm[2:0] con gurations shown below are meaningful only if tt[1:0] = 01, indicating an external master or dma access. tm[2:0] /pp[4:2] o multiplexed transfer attribute pins. the encodings below are valid when tt[1:0] = 01 and internal dma channels are driving the bus. dma transfer information on tm[2:1] can be provided on every dma transfer or only on the last transfer by programming dcr[at]. tm[2:1]encoding 00 dma acknowledge information not provided 01 dma transfer, channel 0 10 dma transfer, channel 1 11 reserved tm0 encoding for dma as master (tt = 01) 0 single-address access negated 1 single-address access for tt[1:0] = 01, the tm0 encoding is independent of tm[2:1]. if dcr[saa] is set, tm0 designates a single-address dma access. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-3 dma transfer overview 12.3 dma transfer overview the dma module usually transfers data faster than the coldfire core can under software control. the term ?direct memory access? refers to peripheral device?s ability to access system memory directly, greatly improving overall system performance. the dma module consists of four independent, functionally equivalent channels, so references to dma in this chapter apply to any of the channels. it is not possible to implicitly address all four channels at once. the mcf5307 on-chip peripherals do not support single-address transfers. the processor generates dma requests internally by setting dcr[start]; a device can generate a dma request externally by using dreq pins. the processor can program bus bandwidth for each channel. the channels support cycle-steal and continuous transfer modes; see section 12.5.1, ?transfer requests (cycle-steal and continuous modes).? the dma controller supports dual- and single-address transfers as follows. in both, the dma channel supports 32 address bits and 32 data bits. dual-address transfers?a dual-address transfer consists of a read followed by a write and is initiated by an internal request using the start bit or by an external device using dreq . two types of transfer can occur, a read from a source device or a write to a destination device; see figure 12-2. figure 12-2. dual-address transfer single-address transfers?an external device can initiate a single-address transfer by asserting dreq . the mcf5307 provides address and control signals for single-address transfers. the external device reads to or writes from the speci ed address, as figure 12-3 shows. external logic is required. dma dma memory/ peripheral memory/ peripheral control and data control and data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-4 mcf5307 users manual dma controller module programming model figure 12-3. single-address transfers any operation involving the dma module follows the same three steps: 1. channel initialization?channel registers are loaded with control information, address pointers, and a byte-transfer count. 2. data transfer?the dma accepts requests for operand transfers and provides addressing and bus control for the transfers. 3. channel termination?occurs after the operation is nished, either successfully or due to an error. the channel indicates the operation status in the channel?s dsr, described in section 12.4.5, ?dma status registers (dsr0?dsr3).? 12.4 dma controller module programming model this section describes each internal register and its bit assignment. note that there is no way to prevent a write to a control register during a dma transfer. table 12-2 shows the mapping of dma controller registers. note the differences for the byte count registers depending on the value of mpark[bcr24bit]. dma memory dma peripheral control signals control signals control signals control signals data memory peripheral data write: read: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-5 dma controller module programming model table 12-2. memory map for dma controller module registers dma channel mbar offset [31:24] [23:16] [15:8] [7:0] 0 0x300 source address register 0 (sar0) [p. 12-6] 0x304 destination address register 0 (dar0) [p. 12-7] 0x308 dma control register 0 (dcr0) [p. 12-8] 0x30c byte count register 0 (bcr24bit = 0) 1 reserved 0x30c reserved byte count register 0 (bcr24bit = 1) 1 (bcr0) [p. 12-7] 0x310 dma status register 0 (dsr0) [p. 12-10] reserved 0x314 dma interrupt vector register 0 (divr0) [p. 12-11] reserved 1 0x340 source address register 1 (sar1) [p. 12-6] 0x344 destination address register 1 (dar1) [p. 12-7] 0x348 dma control register 1 (dcr1) [p. 12-8] 0x34c byte count register 1 (bcr24bit = 0) 1 reserved 0x34c reserved byte count register 1 (bcr24bit = 1) 1 (bcr1) [p. 12-7] 0x350 dma status register 1 (dsr1) [p. 12-10] reserved 0x354 dma interrupt vector register 1 (divr1) [p. 12-11] reserved 2 0x380 source address register 2 (sar2) [p. 12-6] 0x384 destination address register 2 (dar2) [p. 12-7] 0x388 dma control register 2 (dcr2) [p. 12-8] 0x38c byte count register 2 (bcr24bit = 0) 1 reserved 0x38c reserved byte count register 2 (bcr24bit = 1) 1 (bcr2) [p. 12-7] 0x390 dma status register 2 (dsr2) [p. 12-10] reserved 0x394 dma interrupt vector register 2 (divr2) [p. 12-11] reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-6 mcf5307 users manual dma controller module programming model note: external masters cannot access mcf5307 on-chip memories or mbar, but they can access dma module registers. 12.4.1 source address registers (sar0?ar3) sar n , figure 12-4, contains the address from which the dma controller requests data. in single-address mode, sar n provides the address regardless of the direction. note: sar/dar address ranges cannot be programmed to on-chip sram because it cannot be accessed by on-chip dma. 3 0x3c0 source address register 3 (sar3) [p. 12-6] 0x3c4 destination address register 3 (dar3) [p. 12-7] 0x3c8 dma control register 3 (dcr3) [p. 12-8] 0x3cc byte count register 3 (bcr24bit = 0) 1 reserved 0x3cc reserved byte count register 3 (bcr24bit = 1) 1 (bcr3) [p. 12-7] 0x3d0 dma status register 3 (dsr3) [p. 12-10] reserved 0x3d4 dma interrupt vector register 3 (divr3) [p. 12-11] reserved 1 on the original mcf5307 mask set (h55j), the bcr of the dma channels can accommodate only 16 bits. however, because the revised mcf5307 supports a 24-bit byte count range, the position of the bcr in the memory map depends on whether a 16- or 24-bit byte counter is selected. the 24-bit byte count can be selected by setting bcr24bit = 1, making dcr[at] available. the at bit selects whether dma channels assert acknowledge during the entire transfer or only at the nal transfer of a dma transaction. new applications should take advantage of the full range of the 24-bit byte counter, including the at bit. the 16-bit byte count option (bcr24bit = 0) retains compatibility with older mcf5307 revisions. 31 0 field sar reset 0000_0000_0000_0000_0000_0000_0000_0000 r/w r/w address mbar + 0x300, 0x340, 0x380, 0x3c0 figure 12-4. source address registers (sar n ) table 12-2. memory map for dma controller module registers (continued) dma channel mbar offset [31:24] [23:16] [15:8] [7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-7 dma controller module programming model 12.4.2 destination address registers (dar0?ar3) for dual-address transfers only, dar n , figure 12-5, holds the address to which the dma controller sends data. figure 12-5. destination address registers (dar n ) note: on-chip dmas do not maintain coherency with mcf5307 caches and so must not transfer data to cacheable memory. 12.4.3 byte count registers (bcr0?cr3) bcr n , figure 12-6 and figure 12-7, holds the number of bytes yet to be transferred for a given block.the offset within the memory map is based on the value of mpark[bcr24bit]. bcr n decrements on the successful completion of the address transfer of either a write transfer in dual-address mode or any transfer in single-address mode. bcr n decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively. figure 12-6 shows bcr for bcr24bit = 1. figure 12-6. byte count registers (bcr n )?cr24bit = 1 figure 12-7 shows bcr for bcr24bit = 0. 31 0 field dar reset 0000_0000_0000_0000_0000_0000_0000_0000 r/w r/w address mbar + 304, 0x344, 0x384, 0x3c4 31 24 23 0 field bcr reset 0000_0000_0000_0000_0000_0000 r/w r/w address mbar + 0x30c, 0x34c, 0x38c, 0x3ac f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-8 mcf5307 users manual dma controller module programming model figure 12-7. bcr n ?cr24bit = 0 dsr[done], shown in figure 12-9, is set when the block transfer is complete. when a transfer sequence is initiated and bcr n [bcr] is not divisible by 16, 4, or 2 when the dma is con gured for line, longword, or word transfers, respectively, dsr n [ce] is set and no transfer occurs. see section 12.4.5, ?dma status registers (dsr0?dsr3).? 12.4.4 dma control registers (dcr0?cr3) dcr n , figure 12-8, is used for con guring the dma controller module. note that dcr[at] is available only if bcr24bit = 1. table 12-3 describes dcr elds. bit 1514 13 1211109876543210 field bcr reset 0000_0000_0000_0000 r/w addr mbar + 0x30c, 0x34c, 0x38c, 0x3ac 31 30 29 28 27 25 24 23 22 21 20 19 18 17 16 field int eext cs aa bwc saa s_rw sinc ssize dinc dsize start reset 0000_0000_0000_0000 r/w r/w 15 14 0 field at 1 1 available only if bcr24bit = 1, otherwise reserved. reset 0 n/a r/w r/w address mbar + 0x308, 0x348, 0x388, 0x3a8 figure 12-8. dma control registers (dcr n ) table 12-3. dcr n field descriptions bits name description 31 int interrupt on completion of transfer. determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition. 0 no interrupt is generated. 1 internal interrupt signal is enabled. 30 eext enable external request. care should be taken because a collision can occur between the start bit and dreq when eext = 1. 0 external request is ignored. 1 enables external request to initiate transfer. internal request is always enabled. it is initiated by writing a 1 to the start bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-9 dma controller module programming model 29 cs cycle steal. 0 dma continuously makes read/write transfers until the bcr decrements to 0. 1 forces a single read/write transfer per request. the request may be internal by setting the start bit, or external by asserting dreq . 28 aa auto-align. aa and size determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size. see section 12.5.4.2, auto-alignment. 0 auto-align disabled 1 if ssize indicates a transfer no smaller than dsize, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. source alignment takes precedence over destination alignment. if auto-alignment is enabled, the appropriate address register increments, regardless of dinc or sinc. 27 25 bwc bandwidth control. indicates the number of bytes in a block transfer. when the byte count reaches a multiple of the bwc value, the dma releases the bus. for example, if bcr24bit is 0, bwc is 001 (512 bytes or value of 0x0200), and bcr is 0x1000, the bus is relinquished after bcr values of 0x2000, 0x1e00, 0x1c00, 0x1a00, 0x1800, 0x1600, 0x1400, 0x1200, 0x1000, 0x0e00, 0x0c00, 0x0a00, 0x0800, 0x0600, 0x0400, and 0x0200. if bcr24bit is 0, bwc is 110, and bcr is 33000, the bus is released after 232 bytes because the bcr is at 32768, a multiple of 16384. bwc bcr24bit = 0 bcr24bit = 1 000 dma has priority. it does not negate its request until its transfer completes. 001 512 16384 010 1024 32768 011 2048 65536 100 4096 131072 101 8192 262144 110 16384 524288 111 32768 1048576 24 saa single-address access. determines whether the dma channel is in dual- or single-address mode 0 dual-address mode. 1 single-address mode. the dma provides an address from the sar and directional control, bit s_rw, to allow two peripherals (one might be memory) to exchange data within a single access. data is not stored by the dma. 23 s_rw single-address access read/write value. valid only if saa = 1. speci es the value of the read signal during single-address accesses. this provides directional control to the bus controller. 0 forces the read signal to 0. 1 forces the read signal to 1. 22 sinc source increment. controls whether a source address increments after each successful transfer. 0 no change to sar after a successful transfer. 1 the sar increments by 1, 2, 4, or 16, as determined by the transfer size. 21 20 ssize source size. determines the data size of the source bus cycle for the dma control module. 00 longword 01 byte 10 word 11 line 19 dinc destination increment. controls whether a destination address increments after each successful transfer. 0 no change to the dar after a successful transfer. 1 the dar increments by 1, 2, 4, or 16, depending upon the size of the transfer. 18 17 dsize destination size. determines the data size of the destination bus cycle for the dma controller. 00 longword 01 byte 10 word 11 line table 12-3. dcr n field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-10 mcf5307 users manual dma controller module programming model 12.4.5 dma status registers (dsr0?sr3) in response to an event, the dma controller writes to the appropriate dsr n bit, figure 12-9. only a write to dsr n [done] results in action. table 12-4 describes dsr n elds. 16 start start transfer. 0 dma inactive 1 the dma begins the transfer in accordance to the values in the control registers. start is cleared automatically after one clock and is always read as logic 0. 15 at at is available only if bcr24bit = 1. dma acknowledge type. controls whether acknowledge information is provided for the entire transfer or only the nal transfer. 0 entire transfer. dma acknowledge information is displayed anytime the channel is selected as the result of an external request. 1 final transfer (when bcr reaches zero). for dual-address transfer, the acknowledge information is displayed for both the read and write cycles. 14 0 reserved, should be cleared. 76543210 field ce bes bed req bsy done reset 000 000 r/w r/w address mbar + 0x310, 0x350, 0x390, 0x3d0 figure 12-9. dma status registers (dsr n ) table 12-4. dsr n field descriptions bits name description 7 reserved, should be cleared. 6 ce con guration error. occurs when bcr, sar, or dar does not match the requested transfer size, or if bcr = 0 when the dma receives a start condition. ce is cleared at hardware reset or by writing a 1 to dsr[done]. 0 no con guration error exists. 1 a con guration error has occurred. 5 bes bus error on source 0 no bus error occurred. 1 the dma channel terminated with a bus error either during the read portion of a transfer or during an access in single-address mode (saa = 1). 4 bed bus error on destination 0 no bus error occurred. 1 the dma channel terminated with a bus error during the write portion of a transfer. 3 reserved, should be cleared. table 12-3. dcr n field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-11 dma controller module functional description 12.4.6 dma interrupt vector registers (divr0?ivr3) the contents of a dma interrupt vector register (divr n ), figure 12-10, are driven onto the internal bus in response to an interrupt acknowledge cycle. 12.5 dma controller module functional description in the following discussion, the term ?dma request? implies that dcr[start] or dcr[eext] is set, followed by assertion of dreq . the start bit is cleared when the channel begins an internal access. before initiating a dual-address access, the dma module veri es that dcr[ssize,dsize] are consistent with the source and destination addresses. if the source and destination are not the same size, the con guration error bit, dsr[ce], is also set. if misalignment is detected, no transfer occurs, ce is set, and, depending on the dcr con guration, an interrupt event is issued. note that if the auto-align bit, dcr[aa], is set, error checking is performed on appropriate registers. a read/write transfer reads bytes from the source address and writes them to the destination address. the number of bytes is the larger of the sizes speci ed by ssize and dsize. see section 12.4.4, ?dma control registers (dcr0?dcr3).? source and destination address registers (sar and dar) can be programmed in the dcr 2 req request 0 no request is pending or the channel is currently active. cleared when the channel is selected. 1 the dma channel has a transfer remaining and the channel is not selected. 1 bsy busy 0 dma channel is inactive. cleared when the dma has nished the last transaction. 1 bsy is set the rst time the channel is enabled after a transfer is initiated. 0 done transactions done. set when all dma controller transactions complete normally, as determined by transfer count and error conditions. when bcr reaches zero, done is set when the nal transfer completes successfully. done can also be used to abort a transfer by resetting the status bits. when a transfer completes, software must clear done before reprogramming the dma. 0 writing or reading a 0 has no effect. 1 dma transfer completed. writing a 1 to this bit clears all dma status bits and can be used as an interrupt handler to clear the dma interrupt and error bits. 7 0 field interrupt vector bits reset 0000_1111 r/w r/w address mbar + 0x314, 0x354, 0x394, 0x3d4 figure 12-10. dma interrupt vector registers (divr n ) table 12-4. dsr n field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-12 mcf5307 users manual dma controller module functional description to increment at the completion of a successful transfer. bcr decrements when an address transfer write completes for a single-address access (dcr[saa] = 0) or when saa = 1. 12.5.1 transfer requests (cycle-steal and continuous modes) the dma channel supports internal and external requests. a request is issued by setting dcr[start] or by asserting dreq . setting dcr[eext] enables recognition of external interrupts. internal interrupts are always recognized. bus usage is minimized for either internal or external requests by selecting between cycle-steal and continuous modes. cycle-steal mode (dcr[cs] = 1)?only one complete transfer from source to destination occurs for each request. if dcr[eext] is set, a request can be either internal or external. internal request is selected by setting dcr[start]. an external request is initiated by asserting dreq while eext is set. continuous mode (dcr[cs] = 0)?after an internal or external request, the dma continuously transfers data until bcr reaches zero or a multiple of dcr[bwc] or dsr[done] is set. if bcr is a multiple of bwc, the dma request signal is negated until the bus cycle terminates to allow the internal arbiter to switch masters. dcr[bwc] = 000 speci es the maximum transfer rate; other values specify a transfer rate limit. the dma performs the speci ed number of transfers, then relinquishes bus control. the dma negates its internal bus request on the last transfer before the bcr reaches a multiple of the boundary speci ed in bwc. on completion, the dma reasserts its bus request to regain mastership at the earliest opportunity. the minimum time that the dma loses bus control is one bus cycle. 12.5.2 data transfer modes each channel supports dual- and single-address transfers, described in the next sections. 12.5.2.1 dual-address transfers dual-address transfers consist of a source operand read and a destination operand write. the dma controller module begins a dual-address transfer sequence when dcr[saa] is cleared during a dma request. if no error condition exists, dsr[req] is set. dual-address read?the dma controller drives the sar value onto the internal address bus. if dcr[sinc] is set, the sar increments by the appropriate number of bytes upon a successful read cycle. when the appropriate number of read cycles complete (multiple reads if the destination size is wider than the source), the dma initiates the write portion of the transfer. if a termination error occurs, dsr[bes,done] are set and dma transactions stop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-13 dma controller module functional description dual-address write?the dma controller drives the dar value onto the address bus. if dcr[dinc] is set, dar increments by the appropriate number of bytes at the completion of a successful write cycle. the bcr decrements by the appropriate number of bytes. dsr[done] is set when bcr reaches zero. if the bcr is greater than zero, another read/write transfer is initiated. if the bcr is a multiple of dcr[bwc], the dma request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. if a termination error occurs, dsr[bes,done] are set and dma transactions stop. 12.5.2.2 single-address transfers single-address transfers consist of one dma bus cycle, allowing either a read or a write cycle to occur. the dma controller begins a single-address transfer sequence when dcr[saa] is set during a dma request. if no error condition exists, dsr[req] is set. when the channel is enabled, dsr[bsy] is set and req is cleared. sar contents are then driven onto the address bus and the value of dcr[s_rw] is driven on r/w . the bcr decrements on each successful address access until it is zero, when dsr[done] is set. if a termination error occurs, dsr[bes,done] are set and dma transactions stop. 12.5.3 channel initialization and startup before a block transfer starts, channel registers must be initialized with information describing con guration, request-generation method, and the data block. 12.5.3.1 channel prioritization the four dma channels are prioritized in ascending order (channel 0 having highest priority and channel 3 having the lowest) or as determined by dcr[bwc]. if bwc for a dma channel is 000, that channel has priority only over the channel immediately preceding it. for example, if dcr3[bwc] = 000, dma channel 3 has priority over dma channel 2 (assuming dcr2[bwc] 000) but not over dma channel 1. if dcr1[bwc] = dcr2[bwc] = 000, dma 1 has priority over dma 0 and dma 2. dcr2[bwc] = 000 in this case does not affect prioritization. prioritization of simultaneous external requests is either ascending or as determined by each channel?s bwc bits as described in the previous paragraphs. 12.5.3.2 programming the dma controller module note the following general guidelines for programming the dma: no mechanism exists to prevent writes to control registers during dma accesses. if the bwc of sequential channels are equal, channel priority is in ascending order. the sar is loaded with the source (read) address. if the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. if the transfer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-14 mcf5307 users manual dma controller module functional description is from memory to either a peripheral device or memory, the source address is the starting address of the data block. this can be any aligned byte address. in single-address mode, this data register is used regardless of transfer direction. the dar should contain the destination (write) address. if the transfer is from a peripheral device to memory, or memory to memory, the dar is loaded with the starting address of the data block to be written. if the transfer is from memory to a peripheral device, dar is loaded with the address of the peripheral data register. this address can be any aligned byte address. dar is not used in single-address mode. sar and dar change after each cycle depending on dcr[ssize,dsize,sinc,dinc] and on the starting address. increment values can be 1, 2, 4, or 16 for byte, word, longword, or line transfers, respectively. if the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer. bcr n [bcr] must be loaded with the number of byte transfers to occur. it is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. dsr must be cleared for channel startup. as soon as the channel has been initialized, it is started by writing a one to dcr[start] or asserting dreq , depending on the status of dcr[eext]. programming the channel for internal request causes the channel to request the bus and start transferring data immediately. if the channel is programmed for external request, dreq must be asserted before the channel requests the bus. changes to dcr are effective immediately while the channel is active. to avoid problems with changing a dma channel setup, write a one to dsr[done] to stop the dma channel. 12.5.4 data transfer this section includes timing diagrams that illustrate the interaction of signals in dma data transfers. it also describes auto-alignment and bandwidth control. 12.5.4.1 external request and acknowledge operation channels 0 and 1 initiate transfers to an external module by means of dreq [1:0]. the request for channels 2 and 3 are connected internally to the uart0 and uart1 interrupt signals, respectively. if dcr[eext] = 1 and the channel is idle, the dma initiates a transfer when dreq is asserted. figure 12-11 shows the minimum 4-clock cycle delay from when dreq is sampled asserted to when a dma bus cycle begins. this delay may be longer, depending on dma priority, bus arbitration, dram refresh operations, and other factors. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-15 dma controller module functional description figure 12-11. dreq timing constraints, dual-address dma transfer although figure 12-11 does not show tm0 signaling a dma acknowledgement, this signal can provide an external request acknowledge response, as shown in subsequent diagrams. to initiate a request, dreq need only be asserted long enough to be sampled on one rising clock edge. however, note the following regarding the negation of dreq : in cycle-steal mode (dcr[cs] = 1), the read/write transaction is limited to a single transfer. dreq must be negated appropriately to avoid generating another request. ? for dual-address transfers, dreq must be negated before ts is asserted for the write portion, as shown in figure 12-11, clock cycle 7. ? for single-address transfers, dreq must be negated before ts is asserted for the transfer, as shown in figure 12-13, clock cycle 4. in burst mode, (dcr[cs] = 0), multiple read/write transfers can occur on the bus as programmed. dreq need not be negated until dsr[done] is set, indicating the block transfer is complete. another transfer cannot be initiated until the dma registers are reprogrammed. figure 12-12 shows a dual-address, peripheral-to-sdram dma transfer. the dma is not parked on the bus, so the diagram shows how the cpu can generate multiple bus cycles during dma transfers. it also shows tm0 timing. the tt signals indicate whether the cpu (0) or dma (1) has bus mastership. tm2 indicates dual-address mode. if dcr[at] is 1, tm is asserted during the nal transfer. if dcr[at] is 0, tm asserts during all dma accesses. dreq0 tt1 tt0 ts cs t a r/w 0 clkin 1234567891011 a[31:0] read write tm0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-16 mcf5307 users manual dma controller module functional description figure 12-12. dual-address, peripheral-to-sdram, lower-priority dma transfer figure 12-13 shows a single-address dma transfer in which the peripheral is reading from memory. note that tm2 is high, indicating a single-address transfer. note that dreq is negated in clock 4, before the assertion of ts in clock 6. as tip a[31:0] siz[1:0] d[31:0] cs x t a dramw sras scas ras [1:0] cas [3:0] tt[1:0] tm2 dreq0 ts r/w clkin 0 01 0 1 precharge cpu dma read cpu dma write cpu tm0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 12. dma controller module 12-17 dma controller module functional description figure 12-13. single-address dma transfer 12.5.4.2 auto-alignment auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. to use this feature, dcr[aa] must be set. the source is auto-aligned if ssize indicates a transfer size larger than dsize. source alignment takes precedence over the destination when the source and destination sizes are equal. otherwise, the destination is auto-aligned. the address register chosen for alignment increments regardless of the increment value. con guration error checking is performed on registers not chosen for alignment. if bcr is greater than 16, the address determines transfer size. bytes, words, or longwords are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size. if bcr is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. for example, aa = 1, sar = 0x0001, bcr = 0x00f0, ssize = 00 (longword), and dsize = 01 (byte). because ssize > dsize, the source is auto-aligned. error checking is performed on destination registers. the access sequence is as follows: 1. read byte from 0x0001?write 1 byte, increment sar. 2. read word from 0x0002?write 2 bytes, increment sar. 3. read longword from 0x0004?write 4 bytes, increment sar. 0 clkin 1234567891011 dreq0 ts a[31:0], siz[1:0] t a cs x , as tip d[31:0] oe , be /bwe r/w tm2 tt0 tt1 tm0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12-18 mcf5307 users manual dma controller module functional description 4. repeat longwords until sar = 0x00f0. 5. read byte from 0x00f0?write byte, increment sar. if dsize is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the con gured size. 12.5.4.3 bandwidth control bandwidth control makes it possible to force the dma off the bus to allow access to another device. dcr[bwc] provides seven levels of block transfer sizes. if the bcr decrements to a multiple of the decode of the bwc, the dma bus request negates until the bus cycle terminates. if a request is pending, the arbiter may then pass bus mastership to another device. if auto-alignment is enabled, dcr[aa] = 1, the bcr may skip over the programmed boundary, in which case, the dma bus request is not negated. if bwc = 000, the request signal remains asserted until bcr reaches zero. dma has priority over the core. note that in this scheme, the arbiter can always force the dma to relinquish the bus. see section 6.2.10.1, ?default bus master park register (mpark).? 12.5.5 termination an unsuccessful transfer can terminate for one of the following reasons: error conditions?when the mcf5307 encounters a read or write cycle that terminates with an error condition, dsr[bes] is set for a read and dsr[bed] is set for a write before the transfer is halted. if the error occurred in a write cycle, data in the internal holding register is lost. interrupts?if dcr[int] is set, the dma drives the appropriate internal interrupt signal. the processor can read dsr to determine whether the transfer terminated successfully or with an error. dsr[done] is then written with a one to clear the interrupt and the done and error bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 13. timer module 13-1 chapter 13 timer module this chapter describes the con guration and operation of the two general-purpose timer modules (timer 0 and timer 1). it includes programming examples. 13.1 overview the timer module incorporates two independent, general-purpose 16-bit timers, timer 0 and timer 1. the output of an 8-bit prescaler clocks each timer. there are two sets of registers, one for each timer. the timers can operate from the system bus clock (bclko) or from an external clocking source using one of the tin signals. if bclko is selected, it can be divided by 16 or 1. figure 13-1 is a block diagram of one of the two identical ti5mer modules. figure 13-1. timer block diagram timer divider timer mode register (tmr n ) prescaler mode bits timer counter (tcn n ) 15 0 timer reference register (trr n ) 15 0 timer capture register (tcr n ) 15 0 timer event register (ter n ) capture detection tin tout general-purpose timer clock (contains incrementing value) (reference value for comparison with tcn) (latches tcn value when triggered by tin) (indicates capture or when tcn = trr n ) irq n clock generator system bus clock ( 1 or 16) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
13-2 mcf5307 users manual general-purpose timer units 13.1.1 key features each general-purpose 16-bit timer unit has the following features: maximum period of 5.96 seconds at 45 mhz 27-ns resolution at 45 mhz programmable sources for the clock input, including external clock input-capture capability with programmable trigger edge on input pin output-compare with programmable mode for the output pin free run and restart modes maskable interrupts on input capture or reference-compare 13.2 general-purpose timer units the general-purpose timer units provide the following features: each timer can be programmed to count and compare to a reference value stored in a register or capture the timer value at an edge detected on tin. system bus clock can be divided by 16 or 1. this clock is input to the prescaler. tin is fed directly into the 8-bit prescaler. the maximum value of tin is 1/5 of clkin, as described in chapter 20, ?electrical speci cations.? the 8-bit prescaler clock divides the clocking source and is user-programmable from 1 to 256. programmed events generate interrupts. the timer output signal (tout) can be con gured to toggle or pulse on an event. 13.3 general-purpose timer programming model the following features are programmable through the timer registers, shown in table 13-1: prescaler?the prescaler clock input is selected from bclko (divided by 1 or 16) or from the corresponding timer input, tin. tin is synchronized to bclko. the synchronization delay is between two and three bclko clocks. the corresponding tmr n [iclk] selects the clock input source. a programmable prescaler divides the clock input by values from 1 to 256. the prescaler is an input to the 16-bit counter. capture mode?each timer has a 16-bit timer capture register (tcr0 and tcr1) that latches the counter value when the corresponding input capture edge detector senses a de ned tin transition. the capture edge bits (tmr n [ce]) select the type of transition that triggers the capture, sets the timer event register capture event bit, ter n [cap], and issues a maskable interrupt. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 13. timer module 13-3 general-purpose timer programming model reference compare?a timer can be con gured to count up to a reference value, at which point ter n [ref] is set. if tmr n [ori] is one, an interrupt is issued. if the free run/restart bit tmr n [frr] is set, a new count starts. if it is clear, the timer keeps running. output mode?when a timer reaches the reference value selected by tmr n [om], it can send an output signal on tout n . tout n can be an active-low pulse or a toggle of the current output under program control. note: although external devices cannot access mcf5307 on-chip memories or mbar, they can access timer module registers. the timer module registers, shown in table 13-1, can be modi ed at any time. 13.3.1 timer mode registers (tmr0/tmr1) timer mode registers (tmr0/tmr1), figure 13-2, program the prescaler and various timer modes. table 13-2 describes tmr n elds. table 13-1. general-purpose timer module memory map mbar offset [31:24] [23:16] [15:8] [7:0] 0x140 timer 0 mode register (tmr0) [p. 13-3] reserved 0x144 timer 0 reference register (trr0) [p. 13-4] reserved 0x148 timer 0 capture register (tcr0) [p. 13-4] reserved 0x14c timer 0 counter (tcn0) [p. 13-5] reserved 0x150 reserved timer 0 event register (ter0) [p. 13-5] reserved 0x180 timer 1 mode register (tmr1) [p. 13-3] reserved 0x184 timer 1 reference register (trr1) [p. 13-4] reserved 0x188 timer 1 capture register (tcr1) [p. 13-4] reserved 0x18c timer 1 counter (tcn1) [p. 13-5] reserved 0x190 reserved timer 1 event register (ter1) [p. 13-5] reserved 15 876543210 field ps ce om ori frr clk rst reset 0000_0000_0000_0000 r/w r/w address mbar + 0x140 (tmr0); + 0x180 (tmr1) figure 13-2. timer mode registers (tmr0/tmr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
13-4 mcf5307 users manual general-purpose timer programming model 13.3.2 timer reference registers (trr0/trr1) each timer reference register (trr0/trr1), figure 13-3, contains the reference value compared with the respective free-running timer counter (tcn0/tcn1) as part of the output-compare function. the reference value is not matched until tcn n equals trr n . = 13.3.3 timer capture registers (tcr0/tcr1) each timer capture register (tcr0/tcr1), figure 13-4, latches the corresponding tcn n value during a capture operation when an edge occurs on tin, as programmed in tmr n . table 13-2. tmr n field descriptions bits name description 15 8 ps prescaler value. the prescaler is programmed to divide the clock input (bclko/(16 or 1) or clock on tin) by values from 1 (ps = 0000_0000) to 256 (ps = 1111_1111). 7 6 ce capture edge and enable interrupt 00 disable interrupt on capture event 01 capture on rising edge only and enable interrupt on capture event 10 capture on falling edge only and enable interrupt on capture event 11 capture on any edge and enable interrupt on capture event 5 om output mode 0 active-low pulse for one bclko cycle (22 ns at 45 mhz, 33 ns at 30 mhz, 44 ns at 22.5 mhz). 1 toggle output. 4 ori output reference interrupt enable. if ori is set when ter n [ref] = 1, an interrupt occurs. 0 disable interrupt for reference reached (does not affect interrupt on capture function). 1 enable interrupt upon reaching the reference value. 3 frr free run/restart 0 free run. timer count continues to increment after reaching the reference value. 1 restart. timer count is reset immediately after reaching the reference value. 2 1 clk input clock source for the timer 00 stop count 01 system bus clock divided by 1 10 system bus clock divided by 16. note that this clock source is not synchronized to the timer; thus successive time-outs may vary slightly. 11 tin pin (falling edge) 0 rst reset timer. performs a software timer reset similar to an external reset, although other register values can still be written while rst = 0. a transition of rst from 1 to 0 resets register values. the timer counter is not clocked unless the timer is enabled. 0 reset timer (software reset) 1 enable timer 15 0 field ref reset 1111_1111_1111_1111 r/w r/w address mbar + 0x144 (trr0),+ 0x184 (trr1) figure 13-3. timer reference registers (trr0/trr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 13. timer module 13-5 general-purpose timer programming model bclko is assumed to be the clock source. tin cannot simultaneously function as a clocking source and as an input capture pin. 13.3.4 timer counters (tcn0/tcn1) the current value of the 16-bit, incrementing timer counters (tcn0/tcn1), figure 13-5, can be read anytime without affecting counting. writing to tcn n clears it. the timer counter decrements on the clock source rising edge (bclko 1, bclko 16, or tin). 13.3.5 timer event registers (ter0/ter1) each timer event register (ter0/ter1), figure 13-6, reports capture or reference events events the timer recognizes by setting ter n [cap] or ter n [ref], which it does regardless of the corresponding interrupt-enable bit values, tmr n [ori,ce]. writing a 1 to either ref or cap clears it (writing a 0 does not affect bit value); both bits can be cleared at the same time. ref and cap must be cleared early in the exception handler, before the timer negates the irq n to the interrupt controller. 15 0 field cap (16-bit capture counter value) reset 0000_0000_0000_0000 r/w read only address mbar + 0x148 (tcr0); + 0x188 (tcr1) figure 13-4. timer capture register (tcr0/tcr1) 15 0 field 16-bit timer counter value count reset 0000_0000_0000_0000 r/w r/w (to reset) address mbar + 0x14c (tcn0); + 0x18c (tcn1) figure 13-5. timer counters (tcn0/tcn1) 7210 field ref cap reset 0000_0000 r/w r/w (ones clear/zeros have no effect) address mbar + 0x151 (ter0); + 0x191 (ter1) figure 13-6. timer event registers (ter0/ter1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
13-6 mcf5307 users manual code example table 13-3 describes ter n elds. 13.4 code example the following code provides an example of how to initialize timer 0 and how to use the timer for counting time-out periods. mbarx equ 0x10000 ;defines the module base address at 0x10000 tmr0 equ mbarx+0x140;timer 0 register tmr1 equ mbarx+0x180 ;timer 1 register trr0 equ mbarx+0x144 ;timer 0 reference register trr1 equ mbarx+0x184 ;timer 1 reference register tcr0 equ mbarx+0x148 ;timer 0 capture register tcr1 equ mbarx+0x188 ;timer 1 capture register tcn0 equ mbarx+0x14c ;timer 0 counter tcn1 equ mbarx+0x18c ;timer 1 counter ter0 equ mbarx+0x151 ;timer 0 event register ter1 equ mbarx+0x191 ;timer 1 event register * tmr0 is defined as: * *[ps]= 0xff, divide clock by 256 *[ce] = 00disable interrupt *[om] = 0 output=active-low pulse *[ori] = 0, disable ref.interrupt *[frr] = 1, restart mode enabled *[clk] = 10, bclko/16 *[rst] = 0, timer 0 disabled move.w #0xff0c,d0 move.w d0,tmr0 move.w #0x0000,d0;writing to the timer counter with any move.w do,tcn0 ;value resets it to zero move.w #afaf,do ;set the timer 0 reference to be move.w #d0,trr0 ;defined as 0xafaf the simple example below uses 0 to count time-out loops. a time-out occurs when the reference value, 0xafaf, is reached. timer0_ex clr.l do clr.l d1 clt.l d2 move.w #0x0000,d0 move,w d0,tcn0;reset the counter to 0x0000 move.b #0x03,d0 ;writing ones to ter0[ref,cap] move.b d0,ter0 ;clears the event flags table 13-3. ter n field descriptions bits name description 7 2 reserved 1 ref output reference event. the counter has reached the trr n value. setting tmr n [ori] enables the interrupt request caused by this event. writing a one to ref clears the event condition. 0 cap capture event. the counter value has been latched into tcr n . setting tmr n [ce] enables the interrupt request caused by this event. writing a 1 to cap clears the event condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 13. timer module 13-7 calculating time-out values move.w tmr0,d0;save the contents of tmr0 while setting bset #0,d0 ;the 0 bit. this enables timer 0 and starts counting move.w d0, tmr0 ;load the value back into the register, setting tmr0[rst] t0_loop move.b ter0,d1 ;load ter0 and see if btst #1,d1 ;ter0[ref] has been set beq t0_loop addi.l #1,d2;increment d2 cmp.l #5,d2;did d2 reach 5? (i.e. timer ref has timed) beq t0_finish;if so, end timer0 example. otherwise jump back. move.b #0x02,d0 ;writing one to ter0[ref] clears the event flag move.b d0,ter0 jmp t0_loop t0_finish halt;end processing. example is finished 13.5 calculating time-out values the formula below determines time-out periods for various reference values: time-out period = (1/clock frequency) x (1 or 16) x (tmr n [ps] + 1) x (trr n [ref]) when calculating time-out periods, add 1 to the prescaler to simplify calculating, because tmr n [ps] = 0x00 yields a prescaler of 1 and tmr n [ps] = 0xff yields a prescaler of 256. for example, if a 45-mhz timer clock is divided by 16, tmr n [ps] = 0x7f, and the timer is referenced at 0xabcd (43,981 decimal), the time-out period is as follows: time-out period = (1/45) x (16) x (127 + 1) x (43,981) = 1.67 s the time-out values in table 13-5 represent the time it takes the counter value in tcn n value to go from 0x0000 to the default reference value, trr n [ref] = 0xffff. time-out values shown for bclko are divided by 1 and by 16 (tmr n [clk] is 01 or 10, respectively). any clock source (bclko 1, bclko 16, or tin) can be prescaled using tmr n [ps]. the bclko frequency depends on the prescaler value (tmr n [ps]) and on the pll clock setting, as described inchapter 7, ?phase-locked loop (pll).? table 13-5. calculated time-out values (90-mhz processor clock) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz 0 0 0.0233 0.03495 0.0466 0.00146 0.00218 0.00291 1 1 0.0466 0.06991 0.09321 0.00291 0.00437 0.00583 2 2 0.06991 0.10486 0.13981 0.00437 0.00655 0.00874 3 3 0.09321 0.13981 0.18641 0.00583 0.00874 0.01165 4 4 0.11651 0.17476 0.23302 0.00728 0.01092 0.01456 5 5 0.13981 0.20972 0.27962 0.00874 0.01311 0.01748 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
13-8 mcf5307 users manual calculating time-out values 6 6 0.16311 0.24467 0.32622 0.01019 0.01529 0.02039 7 7 0.18641 0.27962 0.37283 0.01165 0.01748 0.0233 8 8 0.20972 0.31457 0.41943 0.01311 0.01966 0.02621 9 9 0.23302 0.34953 0.46603 0.01456 0.02185 0.02913 10 0a 0.25632 0.38448 0.51264 0.01602 0.02403 0.03204 11 0b 0.27962 0.41943 0.55924 0.01748 0.02621 0.03495 12 0c 0.30292 0.45438 0.60584 0.01893 0.0284 0.03787 13 0d 0.32622 0.48934 0.65245 0.02039 0.03058 0.04078 14 0e 0.34953 0.52429 0.69905 0.02185 0.03277 0.04369 15 0f 0.37283 0.55924 0.74565 0.0233 0.03495 0.0466 16 10 0.39613 0.59419 0.79226 0.02476 0.03714 0.04952 17 11 0.41943 0.62915 0.83886 0.02621 0.03932 0.05243 18 12 0.44273 0.6641 0.88546 0.02767 0.04151 0.05534 19 13 0.46603 0.69905 0.93207 0.02913 0.04369 0.05825 20 14 0.48934 0.734 0.97867 0.03058 0.04588 0.06117 21 15 0.51264 0.76896 1.02527 0.03204 0.04806 0.06408 22 16 0.53594 0.80391 1.07188 0.0335 0.05024 0.06699 23 17 0.55924 0.83886 1.11848 0.03495 0.05243 0.06991 24 18 0.58254 0.87381 1.16508 0.03641 0.05461 0.07282 25 19 0.60584 0.90877 1.21169 0.03787 0.0568 0.07573 26 1a 0.62915 0.94372 1.25829 0.03932 0.05898 0.07864 27 1b 0.65245 0.97867 1.30489 0.04078 0.06117 0.08156 28 1c 0.67575 1.01362 1.3515 0.04223 0.06335 0.08447 29 1d 0.69905 1.04858 1.3981 0.04369 0.06554 0.08738 30 1e 0.72235 1.08353 1.4447 0.04515 0.06772 0.09029 31 1f 0.74565 1.11848 1.49131 0.0466 0.06991 0.09321 32 20 0.76896 1.15343 1.53791 0.04806 0.07209 0.09612 33 21 0.79226 1.18839 1.58451 0.04952 0.07427 0.09903 34 22 0.81556 1.22334 1.63112 0.05097 0.07646 0.10194 35 23 0.83886 1.25829 1.67772 0.05243 0.07864 0.10486 36 24 0.86216 1.29324 1.72432 0.05389 0.08083 0.10777 37 25 0.88546 1.3282 1.77093 0.05534 0.08301 0.11068 38 26 0.90877 1.36315 1.81753 0.0568 0.0852 0.1136 39 27 0.93207 1.3981 1.86414 0.05825 0.08738 0.11651 40 28 0.95537 1.43305 1.91074 0.05971 0.08957 0.11942 41 29 0.97867 1.46801 1.95734 0.06117 0.09175 0.12233 42 2a 1.00197 1.50296 2.00395 0.06262 0.09393 0.12525 43 2b 1.02527 1.53791 2.05055 0.06408 0.09612 0.12816 44 2c 1.04858 1.57286 2.09715 0.06554 0.0983 0.13107 45 2d 1.07188 1.60782 2.14376 0.06699 0.10049 0.13398 table 13-5. calculated time-out values (90-mhz processor clock) (continued) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 13. timer module 13-9 calculating time-out values 46 2e 1.09518 1.64277 2.19036 0.06845 0.10267 0.1369 47 2f 1.11848 1.67772 2.23696 0.06991 0.10486 0.13981 48 30 1.14178 1.71267 2.28357 0.07136 0.10704 0.14272 49 31 1.16508 1.74763 2.33017 0.07282 0.10923 0.14564 50 32 1.18839 1.78258 2.37677 0.07427 0.11141 0.14855 51 33 1.21169 1.81753 2.42338 0.07573 0.1136 0.15146 52 34 1.23499 1.85248 2.46998 0.07719 0.11578 0.15437 53 35 1.25829 1.88744 2.51658 0.07864 0.11796 0.15729 54 36 1.28159 1.92239 2.56319 0.0801 0.12015 0.1602 55 37 1.30489 1.95734 2.60979 0.08156 0.12233 0.16311 56 38 1.3282 1.99229 2.65639 0.08301 0.12452 0.16602 57 39 1.3515 2.02725 2.703 0.08447 0.1267 0.16894 58 3a 1.3748 2.0622 2.7496 0.08592 0.12889 0.17185 59 3b 1.3981 2.09715 2.7962 0.08738 0.13107 0.17476 60 3c 1.4214 2.1321 2.84281 0.08884 0.13326 0.17768 61 3d 1.4447 2.16706 2.88941 0.09029 0.13544 0.18059 62 3e 1.46801 2.20201 2.93601 0.09175 0.13763 0.1835 63 3f 1.49131 2.23696 2.98262 0.09321 0.13981 0.18641 64 40 1.51461 2.27191 3.02922 0.09466 0.14199 0.18933 65 41 1.53791 2.30687 3.07582 0.09612 0.14418 0.19224 66 42 1.56121 2.34182 3.12243 0.09758 0.14636 0.19515 67 43 1.58451 2.37677 3.16903 0.09903 0.14855 0.19806 68 44 1.60782 2.41172 3.21563 0.10049 0.15073 0.20098 69 45 1.63112 2.44668 3.26224 0.10194 0.15292 0.20389 70 46 1.65442 2.48163 3.30884 0.1034 0.1551 0.2068 71 47 1.67772 2.51658 3.35544 0.10486 0.15729 0.20972 72 48 1.70102 2.55153 3.40205 0.10631 0.15947 0.21263 73 49 1.72432 2.58649 3.44865 0.10777 0.16166 0.21554 74 4a 1.74763 2.62144 3.49525 0.10923 0.16384 0.21845 75 4b 1.77093 2.65639 3.54186 0.11068 0.16602 0.22137 76 4c 1.79423 2.69135 3.58846 0.11214 0.16821 0.22428 77 4d 1.81753 2.7263 3.63506 0.1136 0.17039 0.22719 78 4e 1.84083 2.76125 3.68167 0.11505 0.17258 0.2301 79 4f 1.86414 2.7962 3.72827 0.11651 0.17476 0.23302 80 50 1.88744 2.83116 3.77487 0.11796 0.17695 0.23593 81 51 1.91074 2.86611 3.82148 0.11942 0.17913 0.23884 82 52 1.93404 2.90106 3.86808 0.12088 0.18132 0.24176 83 53 1.95734 2.93601 3.91468 0.12233 0.1835 0.24467 84 54 1.98064 2.97097 3.96129 0.12379 0.18569 0.24758 85 55 2.00395 3.00592 4.00789 0.12525 0.18787 0.25049 table 13-5. calculated time-out values (90-mhz processor clock) (continued) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
13-10 mcf5307 users manual calculating time-out values 86 56 2.02725 3.04087 4.05449 0.1267 0.19005 0.25341 87 57 2.05055 3.07582 4.1011 0.12816 0.19224 0.25632 88 58 2.07385 3.11078 4.1477 0.12962 0.19442 0.25923 89 59 2.09715 3.14573 4.1943 0.13107 0.19661 0.26214 90 5a 2.12045 3.18068 4.24091 0.13253 0.19879 0.26506 91 5b 2.14376 3.21563 4.28751 0.13398 0.20098 0.26797 92 5c 2.16706 3.25059 4.33411 0.13544 0.20316 0.27088 93 5d 2.19036 3.28554 4.38072 0.1369 0.20535 0.27379 94 5e 2.21366 3.32049 4.42732 0.13835 0.20753 0.27671 95 5f 2.23696 3.35544 4.47392 0.13981 0.20972 0.27962 96 60 2.26026 3.3904 4.52053 0.14127 0.2119 0.28253 97 61 2.28357 3.42535 4.56713 0.14272 0.21408 0.28545 98 62 2.30687 3.4603 4.61373 0.14418 0.21627 0.28836 99 63 2.33017 3.49525 4.66034 0.14564 0.21845 0.29127 100 64 2.35347 3.53021 4.70694 0.14709 0.22064 0.29418 101 65 2.37677 3.56516 4.75354 0.14855 0.22282 0.2971 102 66 2.40007 3.60011 4.80015 0.15 0.22501 0.30001 103 67 2.42338 3.63506 4.84675 0.15146 0.22719 0.30292 104 68 2.44668 3.67002 4.89335 0.15292 0.22938 0.30583 105 69 2.46998 3.70497 4.93996 0.15437 0.23156 0.30875 106 6a 2.49328 3.73992 4.98656 0.15583 0.23375 0.31166 107 6b 2.51658 3.77487 5.03316 0.15729 0.23593 0.31457 108 6c 2.53988 3.80983 5.07977 0.15874 0.23811 0.31749 109 6d 2.56319 3.84478 5.12637 0.1602 0.2403 0.3204 110 6e 2.58649 3.87973 5.17297 0.16166 0.24248 0.32331 111 6f 2.60979 3.91468 5.21958 0.16311 0.24467 0.32622 112 70 2.63309 3.94964 5.26618 0.16457 0.24685 0.32914 113 71 2.65639 3.98459 5.31279 0.16602 0.24904 0.33205 114 72 2.67969 4.01954 5.35939 0.16748 0.25122 0.33496 115 73 2.703 4.05449 5.40599 0.16894 0.25341 0.33787 116 74 2.7263 4.08945 5.4526 0.17039 0.25559 0.34079 117 75 2.7496 4.1244 5.4992 0.17185 0.25777 0.3437 118 76 2.7729 4.15935 5.5458 0.17331 0.25996 0.34661 119 77 2.7962 4.1943 5.59241 0.17476 0.26214 0.34953 120 78 2.8195 4.22926 5.63901 0.17622 0.26433 0.35244 121 79 2.84281 4.26421 5.68561 0.17768 0.26651 0.35535 122 7a 2.86611 4.29916 5.73222 0.17913 0.2687 0.35826 123 7b 2.88941 4.33411 5.77882 0.18059 0.27088 0.36118 124 7c 2.91271 4.36907 5.82542 0.18204 0.27307 0.36409 125 7d 2.93601 4.40402 5.87203 0.1835 0.27525 0.367 table 13-5. calculated time-out values (90-mhz processor clock) (continued) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 13. timer module 13-11 calculating time-out values 126 7e 2.95931 4.43897 5.91863 0.18496 0.27744 0.36991 127 7f 2.98262 4.47392 5.96523 0.18641 0.27962 0.37283 128 80 3.00592 4.50888 6.01184 0.18787 0.2818 0.37574 129 81 3.02922 4.54383 6.05844 0.18933 0.28399 0.37865 130 82 3.05252 4.57878 6.10504 0.19078 0.28617 0.38157 131 83 3.07582 4.61373 6.15165 0.19224 0.28836 0.38448 132 84 3.09912 4.64869 6.19825 0.1937 0.29054 0.38739 133 85 3.12243 4.68364 6.24485 0.19515 0.29273 0.3903 134 86 3.14573 4.71859 6.29146 0.19661 0.29491 0.39322 135 87 3.16903 4.75354 6.33806 0.19806 0.2971 0.39613 136 88 3.19233 4.7885 6.38466 0.19952 0.29928 0.39904 137 89 3.21563 4.82345 6.43127 0.20098 0.30147 0.40195 138 8a 3.23893 4.8584 6.47787 0.20243 0.30365 0.40487 139 8b 3.26224 4.89335 6.52447 0.20389 0.30583 0.40778 140 8c 3.28554 4.92831 6.57108 0.20535 0.30802 0.41069 141 8d 3.30884 4.96326 6.61768 0.2068 0.3102 0.4136 142 8e 3.33214 4.99821 6.66428 0.20826 0.31239 0.41652 143 8f 3.35544 5.03316 6.71089 0.20972 0.31457 0.41943 144 90 3.37874 5.06812 6.75749 0.21117 0.31676 0.42234 145 91 3.40205 5.10307 6.80409 0.21263 0.31894 0.42526 146 92 3.42535 5.13802 6.8507 0.21408 0.32113 0.42817 147 93 3.44865 5.17297 6.8973 0.21554 0.32331 0.43108 148 94 3.47195 5.20793 6.9439 0.217 0.3255 0.43399 149 95 3.49525 5.24288 6.99051 0.21845 0.32768 0.43691 150 96 3.51856 5.27783 7.03711 0.21991 0.32986 0.43982 151 97 3.54186 5.31279 7.08371 0.22137 0.33205 0.44273 152 98 3.56516 5.34774 7.13032 0.22282 0.33423 0.44564 153 99 3.58846 5.38269 7.17692 0.22428 0.33642 0.44856 154 9a 3.61176 5.41764 7.22352 0.22574 0.3386 0.45147 155 9b 3.63506 5.4526 7.27013 0.22719 0.34079 0.45438 156 9c 3.65837 5.48755 7.31673 0.22865 0.34297 0.4573 157 9d 3.68167 5.5225 7.36333 0.2301 0.34516 0.46021 158 9e 3.70497 5.55745 7.40994 0.23156 0.34734 0.46312 159 9f 3.72827 5.59241 7.45654 0.23302 0.34953 0.46603 160 a0 3.75157 5.62736 7.50314 0.23447 0.35171 0.46895 161 a1 3.77487 5.66231 7.54975 0.23593 0.35389 0.47186 162 a2 3.79818 5.69726 7.59635 0.23739 0.35608 0.47477 163 a3 3.82148 5.73222 7.64295 0.23884 0.35826 0.47768 164 a4 3.84478 5.76717 7.68956 0.2403 0.36045 0.4806 165 a5 3.86808 5.80212 7.73616 0.24176 0.36263 0.48351 table 13-5. calculated time-out values (90-mhz processor clock) (continued) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
13-12 mcf5307 users manual calculating time-out values 166 a6 3.89138 5.83707 7.78276 0.24321 0.36482 0.48642 167 a7 3.91468 5.87203 7.82937 0.24467 0.367 0.48934 168 a8 3.93799 5.90698 7.87597 0.24612 0.36919 0.49225 169 a9 3.96129 5.94193 7.92257 0.24758 0.37137 0.49516 170 aa 3.98459 5.97688 7.96918 0.24904 0.37356 0.49807 171 ab 4.00789 6.01184 8.01578 0.25049 0.37574 0.50099 172 ac 4.03119 6.04679 8.06238 0.25195 0.37792 0.5039 173 ad 4.05449 6.08174 8.10899 0.25341 0.38011 0.50681 174 ae 4.0778 6.11669 8.15559 0.25486 0.38229 0.50972 175 af 4.1011 6.15165 8.20219 0.25632 0.38448 0.51264 176 b0 4.1244 6.1866 8.2488 0.25777 0.38666 0.51555 177 b1 4.1477 6.22155 8.2954 0.25923 0.38885 0.51846 178 b2 4.171 6.2565 8.342 0.26069 0.39103 0.52138 179 b3 4.1943 6.29146 8.38861 0.26214 0.39322 0.52429 180 b4 4.21761 6.32641 8.43521 0.2636 0.3954 0.5272 181 b5 4.24091 6.36136 8.48181 0.26506 0.39759 0.53011 182 b6 4.26421 6.39631 8.52842 0.26651 0.39977 0.53303 183 b7 4.28751 6.43127 8.57502 0.26797 0.40195 0.53594 184 b8 4.31081 6.46622 8.62162 0.26943 0.40414 0.53885 185 b9 4.33411 6.50117 8.66823 0.27088 0.40632 0.54176 186 ba 4.35742 6.53612 8.71483 0.27234 0.40851 0.54468 187 bb 4.38072 6.57108 8.76144 0.27379 0.41069 0.54759 188 bc 4.40402 6.60603 8.80804 0.27525 0.41288 0.5505 189 bd 4.42732 6.64098 8.85464 0.27671 0.41506 0.55342 190 be 4.45062 6.67593 8.90125 0.27816 0.41725 0.55633 191 bf 4.47392 6.71089 8.94785 0.27962 0.41943 0.55924 192 c0 4.49723 6.74584 8.99445 0.28108 0.42161 0.56215 193 c1 4.52053 6.78079 9.04106 0.28253 0.4238 0.56507 194 c2 4.54383 6.81574 9.08766 0.28399 0.42598 0.56798 195 c3 4.56713 6.8507 9.13426 0.28545 0.42817 0.57089 196 c4 4.59043 6.88565 9.18087 0.2869 0.43035 0.5738 197 c5 4.61373 6.9206 9.22747 0.28836 0.43254 0.57672 198 c6 4.63704 6.95555 9.27407 0.28981 0.43472 0.57963 199 c7 4.66034 6.99051 9.32068 0.29127 0.43691 0.58254 200 c8 4.68364 7.02546 9.36728 0.29273 0.43909 0.58545 201 c9 4.70694 7.06041 9.41388 0.29418 0.44128 0.58837 202 ca 4.73024 7.09536 9.46049 0.29564 0.44346 0.59128 203 cb 4.75354 7.13032 9.50709 0.2971 0.44564 0.59419 204 cc 4.77685 7.16527 9.55369 0.29855 0.44783 0.59711 205 cd 4.80015 7.20022 9.6003 0.30001 0.45001 0.60002 table 13-5. calculated time-out values (90-mhz processor clock) (continued) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 13. timer module 13-13 calculating time-out values 206 ce 4.82345 7.23517 9.6469 0.30147 0.4522 0.60293 207 cf 4.84675 7.27013 9.6935 0.30292 0.45438 0.60584 208 d0 4.87005 7.30508 9.74011 0.30438 0.45657 0.60876 209 d1 4.89335 7.34003 9.78671 0.30583 0.45875 0.61167 210 d2 4.91666 7.37498 9.83331 0.30729 0.46094 0.61458 211 d3 4.93996 7.40994 9.87992 0.30875 0.46312 0.61749 212 d4 4.96326 7.44489 9.92652 0.3102 0.46531 0.62041 213 d5 4.98656 7.47984 9.97312 0.31166 0.46749 0.62332 214 d6 5.00986 7.51479 10.01973 0.31312 0.46967 0.62623 215 d7 5.03316 7.54975 10.06633 0.31457 0.47186 0.62915 216 d8 5.05647 7.5847 10.11293 0.31603 0.47404 0.63206 217 d9 5.07977 7.61965 10.15954 0.31749 0.47623 0.63497 218 da 5.10307 7.6546 10.20614 0.31894 0.47841 0.63788 219 db 5.12637 7.68956 10.25274 0.3204 0.4806 0.6408 220 dc 5.14967 7.72451 10.29935 0.32185 0.48278 0.64371 221 dd 5.17297 7.75946 10.34595 0.32331 0.48497 0.64662 222 de 5.19628 7.79441 10.39255 0.32477 0.48715 0.64953 223 df 5.21958 7.82937 10.43916 0.32622 0.48934 0.65245 224 e0 5.24288 7.86432 10.48576 0.32768 0.49152 0.65536 225 e1 5.26618 7.89927 10.53236 0.32914 0.4937 0.65827 226 e2 5.28948 7.93423 10.57897 0.33059 0.49589 0.66119 227 e3 5.31279 7.96918 10.62557 0.33205 0.49807 0.6641 228 e4 5.33609 8.00413 10.67217 0.33351 0.50026 0.66701 229 e5 5.35939 8.03908 10.71878 0.33496 0.50244 0.66992 230 e6 5.38269 8.07404 10.76538 0.33642 0.50463 0.67284 231 e7 5.40599 8.10899 10.81198 0.33787 0.50681 0.67575 232 e8 5.42929 8.14394 10.85859 0.33933 0.509 0.67866 233 e9 5.4526 8.17889 10.90519 0.34079 0.51118 0.68157 234 ea 5.4759 8.21385 10.95179 0.34224 0.51337 0.68449 235 eb 5.4992 8.2488 10.9984 0.3437 0.51555 0.6874 236 ec 5.5225 8.28375 11.045 0.34516 0.51773 0.69031 237 ed 5.5458 8.3187 11.0916 0.34661 0.51992 0.69323 238 ee 5.5691 8.35366 11.13821 0.34807 0.5221 0.69614 239 ef 5.59241 8.38861 11.18481 0.34953 0.52429 0.69905 240 f0 5.61571 8.42356 11.23141 0.35098 0.52647 0.70196 241 f1 5.63901 8.45851 11.27802 0.35244 0.52866 0.70488 242 f2 5.66231 8.49347 11.32462 0.35389 0.53084 0.70779 243 f3 5.68561 8.52842 11.37122 0.35535 0.53303 0.7107 244 f4 5.70891 8.56337 11.41783 0.35681 0.53521 0.71361 245 f5 5.73222 8.59832 11.46443 0.35826 0.5374 0.71653 table 13-5. calculated time-out values (90-mhz processor clock) (continued) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
13-14 mcf5307 users manual calculating time-out values 246 f6 5.75552 8.63328 11.51103 0.35972 0.53958 0.71944 247 f7 5.77882 8.66823 11.55764 0.36118 0.54176 0.72235 248 f8 5.80212 8.70318 11.60424 0.36263 0.54395 0.72527 249 f9 5.82542 8.73813 11.65084 0.36409 0.54613 0.72818 250 fa 5.84872 8.77309 11.69745 0.36555 0.54832 0.73109 251 fb 5.87203 8.80804 11.74405 0.367 0.5505 0.734 252 fc 5.89533 8.84299 11.79065 0.36846 0.55269 0.73692 253 fd 5.91863 8.87794 11.83726 0.36991 0.55487 0.73983 254 fe 5.94193 8.9129 11.88386 0.37137 0.55706 0.74274 255 ff 5.96523 8.94785 11.93046 0.37283 0.55924 0.74565 table 13-5. calculated time-out values (90-mhz processor clock) (continued) tmr[ps] tmr[clk] = 10 (system bus clock/16) tmr[clk] = 01 (system bus clock/1) decimal hex 45 mhz 30 mhz 22.5 mhz 45 mhz 30 mhz 22.5 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-1 chapter 14 uart modules this chapter describes the use of the universal asynchronous/synchronous receiver/transmitters (uarts) implemented on the mcf5307 and includes programming examples. all references to uart refer to one of these modules. 14.1 overview the mcf5307 contains two independent uarts. each uart can be clocked by bclko, eliminating the need for an external crystal. as figure 14-1 shows, each uart module interfaces directly to the cpu and consists of the following: serial communication channel programmable transmitter and receiver clock generation internal channel control logic interrupt control logic figure 14-1. simplified block diagram the serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from bclko or an external clock using the timer pin. the transmitter converts parallel data from the cpu to a serial bit stream, inserting appropriate start, stop, and parity bits. it outputs the resulting stream on the channel transmitter serial data output (txd). see section 14.5.2.1, ?transmitting.? the receiver converts serial data from the channel receiver serial data input (rxd) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. the receiver may be polled- or interrupt-driven. see section 14.5.2.2, ?receiver.? serial interrupt control logic cts rts rxd txd or external clock (tin) internal channel control logic programmable clock communications channel generation system integration module (sim) interrupt controller uart bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-2 mcf5307 users manual serial module overview 14.2 serial module overview the mcf5307 contains two independent uart modules, whose features are as follows: each can be clocked by bclko, eliminating a need for an external crystal full-duplex asynchronous/synchronous receiver/transmitter channel quadruple-buffered receiver double-buffered transmitter independently programmable receiver and transmitter clock sources programmable data format: ? 5?8 data bits plus parity ? odd, even, no parity, or force parity ? one, one-and-a-half, or two stop bits each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode automatic wake-up mode for multidrop applications four maskable interrupt conditions uart0 and uart1 have interrupt capability to dma channels 2 and 3, respectively, when either the rxrdy or ffull bit is set in the usr. parity, framing, and overrun error detection false-start bit detection line-break detection and generation detection of breaks originating in the middle of a character start/end break interrupt/status 14.3 register descriptions this section contains a detailed description of each register and its speci c function. flowcharts in section 14.5.6, ?programming,? describe basic uart module programming. the operation of the uart module is controlled by writing control bytes into the appropriate registers. table 14-1 is a memory map for uart module registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-3 register descriptions table 14-1. uart module programming model mbar offset [31:24] [23:16] [15:8] [7:0] uart0 uart1 0x1c0 0x200 uart mode registers 1 (umr1 n ) [p. 14-4], (umr2 n ) [p. 14-6] 0x1c4 0x204 (read) uart status registers (usr n ) [p. 14-7] (write) uart clock-select register 1 (ucsr n ) [p. 14-8] 0x1c8 0x208 (read) do not access 2 (write) uart command registers (ucr n ) [p. 14-9] 0x1cc 0x20c (uart/read) uart receiver buffers (urb n ) [p. 14-11] (uart/write) uart transmitter buffers (utb n ) [p. 14-11] 0x1d0 0x210 (read) uart input port change registers (uipcr n ) [p. 14-12] (write) uart auxiliary control registers 1 (uacr n ) [p. 14-12] 0x1d4 0x214 (read) uart interrupt status registers (uisr n ) [p. 14-13] (write) uart interrupt mask registers (uimr n ) [p. 14-13] 0x1d8 0x218 uart divider upper registers (udu n ) [p. 14-14] 0x1dc 0x21c uart divider lower registers (udl n ) [p. 14-14] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-4 mcf5307 users manual register descriptions note: uart registers are accessible only as bytes. although external masters cannot access on-chip memories or mbar, they can access any uart registers. 14.3.1 uart mode registers 1 (umr1 n ) the uart mode registers 1 (umr1 n ) control con guration. umr1 n can be read or written when the mode register pointer points to it, at reset or after a reset mode register pointer command using ucr n [misc]. after umr1 n is read or written, the pointer points to umr2 n . 0x1e0 0x1ec 0x220 0x22c do not access 2 0x1f0 0x230 uart interrupt vector register (uivr n ) [p. 14-15] 0x1f4 0x234 (read) uart input port registers (uip n ) [p. 14-15] (write) do not access 2 0x1f8 0x238 (read) do not access 2 (write) uart output port bit set command registers (uop1 n 3 ) [p. 14-15] 0x1fc 0x23c (read) do not access 2 (write) uart output port bit reset command registers (uop0 n 3 ) [p. 14-15] 1 umr1 n , umr2 n , and ucsr n should be changed only after the receiver/transmitter is issued a software reset command. that is, if channel operation is not disabled, undesirable results may occur. 2 this address is for factory testing. reading this location results in undesired effects and possible incorrect transmission or reception of characters. register contents may also be changed. 3 address-triggered commands table 14-1. uart module programming model (continued) mbar offset [31:24] [23:16] [15:8] [7:0] uart0 uart1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-5 register descriptions table 14-2 describes umr1 n elds. 7 6 543210 field rxrts rxirq/ffull err pm pt b/c reset 0000_0000 r/w r/w address mbar + 0x1c0 (uart0), 0x200 (uart1). after umr1 n is read or written, the pointer points to umr2 n . figure 14-2. uart mode registers 1 (umr1 n ) table 14-2. umr1 n field descriptions bits name description 7 rxrts receiver request-to-send. allows the r ts output to control the cts input of the transmitting device to prevent receiver overrun. if both the receiver and transmitter are incorrectly programmed for r ts control, r ts control is disabled for both. transmitter rts control is con gured in umr2 n [txrts]. 0 the receiver has no effect on r ts . 1 when a valid start bit is received, r ts is negated if the uart's fifo is full. r ts is reasserted when the fifo has an empty position available. 6 rxirq/ ffull receiver interrupt select. 0 rxrdy is the source that generates irq. 1 ffull is the source that generates irq. 5 err error mode. con gures the fifo status bits, usr n [rb,fe,pe]. 0 character mode. the usr n values re ect the status of the character at the top of the fifo. err must be 0 for correct a/d ag information when in multidrop mode. 1 block mode. the usr n values are the logical or of the status for all characters reaching the top of the fifo because the last reset error status command for the channel was issued. see section 14.3.5, uart command registers (ucrn). 4 3 pm parity mode. selects the parity or multidrop mode for the channel. the parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. the value of pm affects pt, as shown below. 2 pt parity type. pm and pt together select parity type (pm = 0x) or determine whether a data or address character is transmitted (pm = 11). pm parity mode parity type (pt= 0) parity type (pt= 1) 00 with parity even parity odd parity 01 force parity low parity high parity 10 no parity n/a 11 multidrop mode data character address character 1 0 b/c bits per character. select the number of data bits per character to be sent. the values shown do not include start, parity, or stop bits. 00 5 bits 01 6 bits 10 7 bits 11 8 bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-6 mcf5307 users manual register descriptions 14.3.2 uart mode register 2 (umr2 n ) uart mode registers 2 (umr2 n ) control uart module con guration. umr2 n can be read or written when the mode register pointer points to it, which occurs after any access to umr1 n . umr2 n accesses do not update the pointer. table 14-3 describes umr2 n elds. 76543 0 field cm txrts txcts sb reset 0000_0000 r/w r/w address mbar + 0x1c0, 0x200. after umr1 n is read or written, the pointer points to umr2 n . figure 14-3. uart mode register 2 (umr2 n ) table 14-3. umr2 n field descriptions bits name description 7 6 cm channel mode. selects a channel mode. section 14.5.3, looping modes, describes individual modes. 00 normal 01 automatic echo 10 local loop-back 11 remote loop-back 5 txrts transmitter ready-to-send. controls negation of r ts to automatically terminate a message transmission. attempting to program a receiver and transmitter in the same channel for r ts control is not permitted and disables r ts control for both. 0 the transmitter has no effect on r ts . 1 in applications where the transmitter is disabled after transmission completes, setting this bit automatically clears uop[rts] one bit time after any characters in the channel transmitter shift and holding registers are completely sent, including the programmed number of stop bits. 4 txcts transmitter clear-to-send. if both txcts and txrts are enabled, txcts controls the operation of the transmitter. 0 cts has no effect on the transmitter. 1 enables clear-to-send operation. the transmitter checks the state of cts each time it is ready to send a character. if cts is asserted, the character is sent; if it is negated, the channel txd remains in the high state and transmission is delayed until cts is asserted. changes in cts as a character is being sent do not affect its transmission. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-7 register descriptions 14.3.3 uart status registers (usr n ) the usr n , figure 14-4, shows status of the transmitter, the receiver, and the fifo. table 14-4 describes usr n elds. 3 0 sb stop-bit length control. selects the length of the stop bit appended to the transmitted character. stop-bit lengths of 9/16th to 2 bits are programmable for 6 8 bit characters. lengths of 1 1/16th to 2 bits are programmable for 5-bit characters. in all cases, the receiver checks only for a high condition at the center of the rst stop-bit position, that is, one bit time after the last data bit or after the parity bit, if parity is enabled. if an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects 2 stop bits for transmission. sb 5 bits 6? bits sb 5 bits 6? bits sb 5? bits sb 5? bits 0000 1.063 0.563 0100 1.313 0.813 1000 1.563 1100 1.813 0001 1.125 0.625 0101 1.375 0.875 1001 1.625 1101 1.875 0010 1.188 0.688 0110 1.438 0.938 1010 1.688 1110 1.938 0011 1.250 0.750 0111 1.500 1.000 1011 1.750 1111 2.000 76543210 field rb fe pe oe txemp txrdy ffull rxrdy reset 0000_0000 r/w read only address mbar + 0x1c4 (usr0), 0x204 (usr1) figure 14-4. uart status register (usr n ) table 14-4. usr n field descriptions bits name description 7 rb received break. the received break circuit detects breaks that originate in the middle of a received character. however, a break in the middle of a character must persist until the end of the next detected character time. 0 no break was received. 1 an all-zero character of the programmed length was received without a stop bit. rb is valid only when rxrdy = 1. only a single fifo position is occupied when a break is received. further entries to the fifo are inhibited until rxd returns to the high state for at least one-half bit time, which is equal to two successive edges of the uart clock. 6 fe framing error. 0 no framing error occurred. 1 no stop bit was detected when the corresponding data character in the fifo was received. the stop-bit check occurs in the middle of the rst stop-bit position. fe is valid only when rxrdy = 1. table 14-3. umr2 n field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-8 mcf5307 users manual register descriptions 14.3.4 uart clock-select registers (ucsr n ) the uart clock-select registers (ucsr n ) select an external clock on the tin input (divided by 1 or 16) or a prescaled bclko as the clocking source for the transmitter and receiver. see section 14.5.1, ?transmitter/receiver clock source.? the transmitter and receiver can use different clock sources. to use bclko for both, set ucsr n to 0xdd. 5 pe parity error. valid only if rxrdy = 1. 0 no parity error occurred. 1 if umr1 n [pm] = 0x (with parity or force parity), the corresponding character in the fifo was received with incorrect parity. if umr1 n [pm] = 11 (multidrop), pe stores the received a/d bit. 4 oe overrun error. indicates whether an overrun occurs. 0 no overrun occurred. 1 one or more characters in the received data stream have been lost. oe is set upon receipt of a new character when the fifo is full and a character is already in the shift register waiting for an empty fifo position. when this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. oe is cleared by the reset error status command in ucr n . 3 txemp transmitter empty. 0 the transmitter buffer is not empty. either a character is being shifted out, or the transmitter is disabled. the transmitter is enabled/disabled by programming ucr n [tc]. 1 the transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). this bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. 2 txrdy transmitter ready. 0 the cpu loaded the transmitter holding register or the transmitter is disabled. 1 the transmitter holding register is empty and ready for a character. txrdy is set when a character is sent to the transmitter shift register and when the transmitter is rst enabled. if the transmitter is disabled, characters loaded into the transmitter holding register are not sent. 1 ffull fifo full. 0 the fifo is not full but may hold up to two unread characters. 1 a character was received and is waiting in the receiver buffer fifo. 0 rxrdy receiver ready 0 the cpu has read the receiver buffer and no characters remain in the fifo after this read. 1 one or more characters were received and are waiting in the receiver buffer fifo. 7430 field rcs tcs reset 0000_0000 r/w write only address mbar + 0x1c4 (ucsr0), 0x204 (ucsr1) figure 14-5. uart clock-select register (ucsr n ) table 14-4. usr n field descriptions (continued) bits name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-9 register descriptions table 14-5 describes ucsr n elds. 14.3.5 uart command registers (ucr n ) the uart command registers (ucr n ), figure 14-6, supply commands to the uart. only multiple commands that do not con ict can be speci ed in a single write to a ucr n . for example, reset transmitter and enable transmitter cannot be speci ed in one command. table 14-6 describes ucr n elds and commands. examples in section 14.5.2, ?transmitter and receiver operating modes,? show how these commands are used. table 14-5. ucsr n field descriptions bits name description 7 4 rcs receiver clock select. selects the clock source for the receiver channel. 1101 prescaled bclko 1110 tin divided by 16 1111 tin 3 0 tcs transmitter clock select. selects the clock source for the transmitter channel. 1101 prescaled bclko 1110 tin divided by 16 1111 tin 76 43210 field misc tc rc reset 0000_0000 r/w write only address mbar + 0x1c8, 0x208 figure 14-6. uart command register (ucr n ) table 14-6. ucr n field descriptions bits value command description 7 reserved, should be cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-10 mcf5307 users manual register descriptions 6 4 misc field (this eld selects a single command.) 000 no command 001 reset mode register pointer causes the mode register pointer to point to umr1 n . 010 reset receiver immediately disables the receiver, clears usr n [ffull,rxrdy], and reinitializes the receiver fifo pointer. no other registers are altered. because it places the receiver in a known state, use this command instead of receiver disable when recon guring the receiver. 011 reset transmitter disables the transmitter and clears usr n [txemp,txrdy]. no other registers are altered. because it places the transmitter in a known state, use this command instead of transmitter disable when recon guring the transmitter. 100 reset error status lears usr n [rb,fe,pe,oe]. also used in block mode to clear all error bits after a data block is received. 101 reset break change interrupt clears the delta break bit, uisr n [db]. 110 start break forces txd low. if the transmitter is empty, the break may be delayed up to one bit time. if the transmitter is active, the break starts when character transmission completes. the break is delayed until any character in the transmitter shift register is sent. any character in the transmitter holding register is sent after the break. the transmitter must be enabled for the command to be accepted. this command ignores the state of cts . 111 stop break causes txd to go high (mark) within two bit times. any characters in the transmitter buffer are sent. 3 2 tc field (this eld selects a single command) 00 no action taken causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 transmitter enable enables operation of the channel s transmitter. usr n [txemp,txrdy] are set. if the transmitter is already enabled, this command has no effect. 10 transmitter disable terminates transmitter operation and clears usr n [txemp,txrdy]. if a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. if the transmitter is already disabled, the command has no effect. 11 reserved, do not use. table 14-6. ucr n field descriptions (continued) bits value command description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-11 register descriptions 14.3.6 uart receiver buffers (urb n ) the receiver buffers contain one serial shift register and three receiver holding registers, which act as a fifo. rxd is connected to the serial shift register. the cpu reads from the top of the stack while the receiver shifts and updates from the bottom when the shift register is full (see figure 14-20). rb contains the character in the receiver. 14.3.7 uart transmitter buffers (utb n ) the transmitter buffers consist of the transmitter holding register and the transmitter shift register. the holding register accepts characters from the bus master if channel?s usr n [txrdy] is set. a write to the transmitter buffer clears txrdy, inhibiting any more characters until the shift register can accept more data. when the shift register is empty, it checks if the holding register has a valid character to be sent (txrdy = 0). if there is a valid character, the shift register loads it and sets usr n [txrdy] again. writes to the transmitter buffer when the channel?s txrdy = 0 and when the transmitter is disabled have no effect on the transmitter buffer. figure 14-8 shows utb0. tb contains the character in the transmitter buffer. 1 0 rc (this eld selects a single command) 00 no action taken causes the receiver to stay in its current mode. if the receiver is enabled, it remains enabled; if disabled, it remains disabled. 01 receiver enable if the uart module is not in multidrop mode (umr1 n [pm] 11), receiver enable enables the channel's receiver and forces it into search-for-start-bit state. if the receiver is already enabled, this command has no effect. 10 receiver disable disables the receiver immediately. any character being received is lost. the command does not affect receiver status bits or other control registers. if the uart module is programmed for local loop-back or multidrop mode, the receiver operates even though this command is selected. if the receiver is already disabled, the command has no effect. 11 reserved, do not use. 7 0 field rb reset 0000_0000 r/w read only address mbar + 0x1cc,0x20c figure 14-7. uart receiver buffer (urb0) table 14-6. ucr n field descriptions (continued) bits value command description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-12 mcf5307 users manual register descriptions 14.3.8 uart input port change registers (uipcr n ) the input port change registers (uipcr n ), figure 14-9, hold the current state and the change-of-state for cts . table 14-7 describes uipcr n elds. 14.3.9 uart auxiliary control register (uacr n ) the uart auxiliary control registers (uacr n ), figure 14-7, control the input enable. 7 0 field tb reset 0000_0000 r/w write only address mbar + 0x1cc,0x20c figure 14-8. uart transmitter buffer (utb0) 7 543 10 field cos 111 cts reset 0000 0 11 cts r/w read only address mbar + 0x1d0 (uipcr0), 0x210 (uipcr1) figure 14-9. uart input port change register (uipcr n ) table 14-7. uipcr n field descriptions bits name description 7 5 reserved, should be cleared. 4 cos change of state (high-to-low or low-to-high transition). 0 no change-of-state since the cpu last read uipcr n . reading uipcr n clears uisr n [cos]. 1 a change-of-state longer than 25 50 s occurred on the cts input. uacr n can be programmed to generate an interrupt to the cpu when a change of state is detected. 3 1 reserved, should be cleared. 0 cts current state. starting two serial clock periods after reset, cts re ects the state of cts . if cts is detected asserted at that time, cos is set, which initiates an interrupt if uacr n [iec] is enabled. 0 the current state of the cts input is asserted. 1 the current state of the cts input is negated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-13 register descriptions table 14-8 describes uacr n elds. 14.3.10 uart interrupt status/mask registers (uisr n /uimr n ) the uart interrupt status registers (uisr n ), figure 14-11, provide status for all potential interrupt sources. uisr n contents are masked by uimr n . if corresponding uisr n and uimr n bits are set, the internal interrupt output is asserted. if a uimr n bit is cleared, the state of the corresponding uisr n bit has no effect on the output. note: true status is provided in the uisr n regardless of uimr n settings. uisr n is cleared when the uart module is reset. table 14-9 describes uisr n and uimr n elds. 7 10 field iec reset 0000_0000 r/w write only address mbar + 0x1d0 (uacr0), 0x210 (uacr1) figure 14-10. uart auxiliary control register (uacr n ) table 14-8. uacr n field descriptions bits name description 7 1 reserved, should be cleared. 0 iec input enable control. 0 setting the corresponding uipcr n bit has no effect on uisr n [cos]. 1 uisr n [cos] is set and an interrupt is generated when the uipcr n [cos] is set by an external transition on the cts input (if uimr n [cos] = 1). 76 32 1 0 field cos db ffull/rxrdy txrdy reset 0000_0000 r/w read only for status, write only for mask. address mbar + 0x1d4 (uisr0), 0x214 (uisr1); mbar + 0x1d4 (uimr0), 0x214 (uimr1) figure 14-11. uart interrupt status/mask registers (uisr n /uimr n ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-14 mcf5307 users manual register descriptions 14.3.11 uart divider upper/lower registers (udu n /udl n ) the udu n registers (formerly called ubg1 n ) holds the msb, and the udl n registers (formerly ubg2 n ) hold the lsb of the preload value. udu n and udl n concatenate to provide a divider to bclko for transmitter/receiver operation, as described in section 14.5.1.2.1, ?bclko baud rates.? note: the minimum value that can be loaded on the concatenation of udu n with udl n is 0x0002. both udu n and udl n are write-only and cannot be read by the cpu. table 14-9. uisr n /uimr n field descriptions bits name description 7 cos change-of-state. 0 uipcr n [cos] is not selected. 1 change-of-state occurred on cts and was programmed in uacr n [iec] to cause an interrupt. 6 3 reserved, should be cleared. 2 db delta break. 0 no new break-change condition to report. section 14.3.5, uart command registers (ucrn), describes the reset break - change interrupt command. 1 the receiver detected the beginning or end of a received break. 1 ffull/ rxrdy rxrdy (receiver ready) if umr1 n [ffull/rxrdy] = 0; fifo full (ffull) if umr1 n [ffull/rxrdy] = 1. duplicate of usr n [ffull/rxrdy]. if ffull is enabled for uart0 or uart1, dma channels 2 or 3 are respectively interrupted when the fifo is full. 0 txrdy transmitter ready. this bit is the duplication of usr n [txrdy]. 0 the transmitter holding register was loaded by the cpu or the transmitter is disabled. characters loaded into the transmitter holding register when txrdy = 0 are not sent. 1 the transmitter holding register is empty and ready to be loaded with a character. 7 0 field divider msb reset 0000_0000 r/w r/w address mbar + 0x1d8 (udu0), 0x218 (udu1) figure 14-12. uart divider upper register (udu n ) 7 0 field divider lsb reset 0000_0000 r/w r/w address mbar + 0x1dc (udl0), 0x21c (udl1) figure 14-13. uart divider lower register (udl n ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-15 register descriptions 14.3.12 uart interrupt vector register (uivr n ) the uivr n , figure 14-14, contain the 8-bit internal interrupt vector number (ivr). table 14-10 describes uivr n elds. 14.3.13 uart input port register (uip n ) the uart input port registers (uip n ), figure 14-15, show the current state of the cts input. table 14-11 describes uip n elds. 14.3.14 uart output port command registers (uop1 n /uop0 n ) in uart mode, the r ts output can be asserted by writing a 1 to uop1 n [rts] and negated by writing a 1 to uop0 n [rts]. see figure 14-16. 7 0 field ivr reset 0000_1111 r/w r/w address mbar + 0x1f0 (uivr0), 0x230 (uivr1) figure 14-14. uart interrupt vector register (uivr n ) table 14-10. uivr n field descriptions bits name description 7 0 ivr interrupt vector. indicates the vector number where the address of the exception handler for the speci ed interrupt is located. uivr n is reset to 0x0f, indicating an uninitialized interrupt condition. 7 10 field cts reset 1111_1111 r/w read only address mbar + 0x1f4 (uip0), 0x234 (uip1) figure 14-15. uart input port register (uip n ) table 14-11. uip n field descriptions bits name description 7 1 reserved, should be cleared. 0 cts current state. the cts value is latched and re ects the state of the input pin when uip n is read. note: this bit has the same function and value as uipcr n [rts]. 0 the current state of the cts input is logic 0. 1 the current state of the cts input is logic 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-16 mcf5307 users manual uart module signal de?itions table 14-12 describes uop1 elds. 14.4 uart module signal de?itions figure 14-17 shows both the external and internal signal groups. figure 14-17. uart block diagram showing external and internal interface signals an internal interrupt request signal (irq ) is provided to notify the interrupt controller of an interrupt condition. the output is the logical nor of unmasked uisr n bits. the interrupt level of a uart module is programmed in the interrupt controller in the system integration module (sim). the uart can use the autovector for the programmed interrupt level or supply the vector from the uivr n when the uart interrupt is acknowledged. 7 10 field rts reset 0000_0000 r/w write only addr uart0: mbar + 0x1f8 (uop1), 0x1fc (uop0); uart1 0x238 (uop1), 0x23c (uop0) figure 14-16. uart output port command register (uop1/uop0) table 14-12. uop1/uop0 field descriptions bits name description 7 1 reserved, should be cleared. 0 rts output port parallel output. controls assertion (uop1)/negation (uop0) of r ts output. 0 not affected. 1 asserts r ts (uop1). negates r ts (uop0). internal four-character receive buffer two-character transmit buffer input port output port interface uart module address bus control cts r ts rxd txd control logic or external clock (tin) internal bus data to cpu irq to interrupt controller (sim) external interface signals bclko clock source generator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-17 uart module signal de?itions the interrupt level, priority, and auto-vectoring capability is programmed in sim register icr4 for uart0 and icr5 for uart1. see section 9.2.1, ?interrupt control registers (icr0?icr9).? note that the uarts can also automatically transfer data by using the dma rather than interrupting the core. when uimr[ffull] is 1 and a receiver?s fifo is full, it can send an interrupt to a dma channel so the fifo data can be transferred to memory. note also that uart0 and uart1?s interrupt requests are connected to dma channel 2 and channel 3, respectively. table 14-13 brie y describes the uart module signals. note: the terms ?assertion? and ?negation? are used to avoid confusion between active-low and active-high signals. ?asserted? indicates that a signal is active, independent of the voltage level; ?negated? indicates that a signal is inactive. figure 14-18 shows a signal con guration for a uart/rs-232 interface. figure 14-18. uart/rs-232 interface table 14-13. uart module signals signal description transmitter serial data output (txd) txd is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loop-back mode. data is shifted out on txd on the falling edge of the clock source, with the least signi cant bit (lsb) sent rst. receiver serial data input (rxd) data received on rxd is sampled on the rising edge of the clock source, with the lsb received rst. clear-to- send (cts ) this input can generate an interrupt on a change of state. request-to- send (r ts ) this output can be programmed to be negated or asserted automatically by either the receiver or the transmitter. when connected to a transmitter s cts , r ts can control serial data ow. r ts do2 di1 cts txd rxd di2 do1 rs-232 transceiver uart f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-18 mcf5307 users manual operation 14.5 operation this section describes operation of the clock source generator, transmitter, and receiver. 14.5.1 transmitter/receiver clock source bclko serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to the uart. the clock generator cannot produce standard baud rates if bclko is used, so the 16-bit divider should be used. 14.5.1.1 programmable divider as figure 14-19 shows, the uart transmitter and receiver can use the following clock sources: an external clock signal on the tin pin that can be divided by 16. when not divided, tin provides a synchronous clock mode; when divided by 16, it is asynchronous . bclko supplies an asynchronous clock source that is divided by 32 and then divided by the 16-bit value programmed in udu n and udl n . see section 14.3.11, ?uart divider upper/lower registers (udun/udln).? the choice of tin or bclko is programmed in the ucsr. figure 14-19. clocking source diagram note: if tin is a clocking source for either the timer or uart, the timer module cannot use tin for timer capture. uart on-chip tin x1 prescaler x16 prescaler clock generator 16-bit divider x32 prescaler tin clocking sources programmed in ucsr timer module tout tin txd rxd tx rx rx buffer tx buffer bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-19 operation 14.5.1.2 calculating baud rates the following sections describe how to calculate baud rates. 14.5.1.2.1 bclko baud rates when bclko is the uart clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated udu n and udl n registers. using a 45-mhz bclko, the baud-rate calculation is as follows: let baud rate = 9600, then therefore udu = 0x00 and udl = 0x92. 14.5.1.2.2 external clock an external source clock (tin) can be used as is or divided by 16. 14.5.2 transmitter and receiver operating modes figure 14-20 is a functional block diagram of the transmitter and receiver showing the command and operating registers, which are described generally in the following sections and described in detail in section 14.3, ?register descriptions.? baudrate 45mhz 32 divider [] ----------------------------------- - = divider 45mhz 32 9600 [] ---------------------------- - 146 decimal () 0092 hexadecimal () == = baudrate externalclockfrequency 16or1 --------------------------------------------------------------------- = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-20 mcf5307 users manual operation figure 14-20. transmitter and receiver functional diagram receiver shift register uart command register (ucr0) w uart status register (usr0) r transmitter shift register uart mode register 1 (umr1) r/w uart mode register 2 (umr2) r/w transmitter holding register w receiver holding register 3 receiver holding register 2 receiver holding register 1 r uart receive uart buffer (urb0) (4 registers) uart0 external interface rxd txd transmitter buffer (utb0) (2 registers) fifo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-21 operation 14.5.2.1 transmitting the transmitter is enabled through the uart command register (ucr n ). when it is ready to accept a character, the uart sets usr n [txrdy]. the transmitter converts parallel data from the cpu to a serial bit stream on txd. it automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. the lsb is sent rst. data is shifted from the transmitter output on the falling edge of the clock source. after the stop bits are sent, if no new character is in the transmitter holding register, the txd output remains high (mark condition) and the transmitter empty bit, usr n [txemp], is set. transmission resumes and txemp is cleared when the cpu loads a new character into the uart transmitter buffer (utb n ). if the transmitter receives a disable command, it continues until any character in the transmitter shift register is completely sent. if the transmitter is reset through a software command, operation stops immediately (see section 14.3.5, ?uart command registers (ucrn)?). the transmitter is reenabled through the ucr n to resume operation after a disable or software reset. if the clear-to-send operation is enabled, cts must be asserted for the character to be transmitted. if cts is negated in the middle of a transmission, the character in the shift register is sent and txd remains in mark state until cts is reasserted. if the transmitter is forced to send a continuous low condition by issuing a send break command, the transmitter ignores the state of cts . if the transmitter is programmed to automatically negate r ts when a message transmission completes, r ts must be asserted manually before a message is sent. in applications in which the transmitter is disabled after transmission is complete and r ts is appropriately programmed, r ts is negated one bit time after the character in the shift register is completely transmitted. the transmitter must be manually reenabled by reasserting r ts before the next message is to be sent. figure 14-21 shows the functional timing information for the transmitter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-22 mcf5307 users manual operation figure 14-21. transmitter timing diagram 14.5.2.2 receiver the receiver is enabled through its ucr n , as described in section 14.3.5, ?uart command registers (ucrn).? figure 14-22 shows receiver functional timing. c1 1 c2 c3 break c4 c6 txd transmitter enabled usr n [txrdy] w 2 wwwwwww cts 3 r ts 4 manually asserted by bit - set command manually asserted start break c5 not transmitted c6 c4 stop break c3 c2 c1 1 c1 in transmission 3 umr2 n [txcts] = 1 1 c n = transmit characters 2 w = write 4 umr2 n [txrts] = 1 inter nal module select f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-23 operation figure 14-22. receiver timing when the receiver detects a high-to-low (mark-to-space) transition of the start bit on rxd, the state of rxd is sampled each 16 clock for eight clocks, starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). if rxd is sampled high, the start bit is invalid and the search for the valid start bit begins again. if rxd is still low, a valid start bit is assumed and the receiver continues sampling the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. data on the rxd input is sampled on the rising edge of the programmed clock source. the lsb is received rst. the data is then transferred to a receiver holding register and usr n [rxrdy] is set. if the character is less than eight bits, the most signi cant unused bits in the receiver holding register are cleared. after the stop bit is detected, the receiver immediately looks for the next start bit. however, if a non-zero character is received without a stop bit (framing error) and rxd remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit were detected. parity error, framing error, overrun error, and received break conditions set the respective pe, fe, oe, rb error and break ags in the usr n at the received character boundary and are valid only if usr n [rxrdy] is set. if a break condition is detected (rxd is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register (rhr) and usr n [rb,rxrdy] are set. rxd must return to a high condition for at least one-half bit time before a search for the next start bit begins. c1 c2 c4 c6 c7 c8 c3 c5 c6, c7, and c8 will be los t (c2) status data (c3) status data (c4) status data c5 will be lost reset by command txd receiver enabled usr n [rxrdy] overrun r ts 4 inter nal module select usr n [ffull] (c1) status data usr n [oe] automatically asserted when ready to receive manually asserted first time, automatically negated if overrun occurs uop0[rts] = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-24 mcf5307 users manual operation the receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. if the break begins in the middle of a character, the receiver places the damaged character in the rx fifo stack and sets the corresponding usr n error bits and usr n [rxrdy]. then, if the break lasts until the next character time, the receiver places an all-zero character into the rx fifo and sets usr n [rb,rxrdy]. 14.5.2.3 fifo stack the fifo stack is used in the uart?s receiver buffer logic. the stack consists of three receiver holding registers. the receive buffer consists of the fifo and a receiver shift register connected to the rxd (see figure 14-20). data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the fifo. thus, data owing from the receiver to the cpu is quadruple-buffered. in addition to the data byte, three status bits, parity error (pe), framing error (fe), and received break (rb), are appended to each data character in the fifo; oe (overrun error) is not appended. by programming the err bit in the channel?s mode register (umr1 n ), status is provided in character or block modes. usr n [rxrdy] is set when at least one character is available to be read by the cpu. a read of the receiver buffer produces an output of data from the top of the fifo stack. after the read cycle, the data at the top of the fifo stack and its associated status bits are popped and the receiver shift register can add new data at the bottom of the stack. the fifo-full status bit (ffull) is set if all three stack positions are lled with data. either the rxrdy or ffull bit can be selected to cause an interrupt. the two error modes are selected by umr1 n [err] as follows: in character mode (umr1 n [err] = 0, status is given in the usr n for the character at the top of the fifo. in block mode, the usr n shows a logical or of all characters reaching the top of the fifo stack since the last reset error status command. status is updated as characters reach the top of the fifo stack. block mode offers a data-reception speed advantage where the software overhead of error-checking each character cannot be tolerated. however, errors are not detected until the check is performed at the end of an entire message?the faulting character is not identi ed. in either mode, reading the usr n does not affect the fifo. the fifo is popped only when the receive buffer is read. the usr n should be read before reading the receive buffer. if all three receiver holding registers are full, a new character is held in the receiver shift register until space is available. however, if a second new character is received, the contents of the the character in the receiver shift register is lost, the fifos are unaffected, and usr n [oe] is set when the receiver detects the start bit of the new overrunning character. to support ow control, the receiver can be programmed to automatically negate and assert r ts , in which case the receiver automatically negates r ts when a valid start bit is detected and the fifo stack is full. the receiver asserts r ts when a fifo position becomes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-25 operation available; therefore, overrun errors can be prevented by connecting r ts to the cts input of the transmitting device. note: the receiver can still read characters in the fifo stack if the receiver is disabled. if the receiver is reset, the fifo stack, r ts control, all receiver status bits, and interrupt requests are reset. no more characters are received until the receiver is reenabled. 14.5.3 looping modes the uart can be con gured to operate in various looping modes as shown in figure 14-22 on page 14-23. these modes are useful for local and remote system diagnostic functions. the modes are described in the following paragraphs and in section 14.3, ?register descriptions.? the uart?s transmitter and receiver should be disabled when switching between modes. the selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. 14.5.3.1 automatic echo mode in automatic echo mode, shown in figure 14-23, the uart automatically resends received data bit by bit. the local cpu-to-receiver communication continues normally, but the cpu-to-transmitter link is disabled. in this mode, received data is clocked on the receiver clock and resent on txd. the receiver must be enabled, but the transmitter need not be. figure 14-23. automatic echo because the transmitter is inactive, usr n [txemp,txrdy] are inactive and data is sent as it is received. received parity is checked but is not recalculated for transmission. character framing is also checked, but stop bits are sent as they are received. a received break is echoed as received until the next valid start bit is detected. 14.5.3.2 local loop-back mode figure 14-24 shows how txd and rxd are internally connected in local loop-back mode. this mode is for testing the operation of a local uart module channel by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations. cpu disabled disabled rxd input txd input tx rx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-26 mcf5307 users manual operation figure 14-24. local loop-back features of this local loop-back mode are as follows: transmitter and cpu-to-receiver communications continue normally in this mode. rxd input data is ignored txd is held marking the receiver is clocked by the transmitter clock. the transmitter must be enabled, but the receiver need not be. 14.5.3.3 remote loop-back mode in remote loop-back mode, shown in figure 14-25, the channel automatically transmits received data bit by bit on the txd output. the local cpu-to-transmitter link is disabled. this mode is useful in testing receiver and transmitter operation of a remote channel. for this mode, the transmitter uses the receiver clock. because the receiver is not active, received data cannot be read by the cpu and error status conditions are inactive. received parity is not checked and is not recalculated for transmission. stop bits are sent as they are received. a received break is echoed as received until the next valid start bit is detected. figure 14-25. remote loop-back 14.5.4 multidrop mode setting umr1 n [pm] programs the uart to operate in a wake-up mode for multidrop or multiprocessor applications. in this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations. although slave stations have their channel receivers disabled, they continuously monitor the master?s data stream. when the master sends an address character, the slave receiver channel noti es its respective cpu by setting usr n [rxrdy] and generating an interrupt (if programmed to do so). each slave station cpu then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. slave stations not addressed continue monitoring the data stream. data elds in the data stream are separated by an address character. after cpu disabled disabled rxd input txd input tx rx cpu disabled disabled rxd input txd input tx rx disabled disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-27 operation a slave receives a block of data, its cpu disables the receiver and repeats the process.functional timing information for multidrop mode is shown in figure 14-26. figure 14-26. multidrop mode timing diagram a character sent from the master station consists of a start bit, a programmed number of data bits, an address/data (a/d) bit ag, and a programmed number of stop bits. a/d = 1 indicates an address character; a/d = 0 indicates a data character. the polarity of a/d is selected through umr1 n [pt]. umr1 n should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer. in multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. if the receiver is disabled, it sets the rxrdy bit and loads the character into the receiver holding register fifo stack provided the received a/d bit is a one (address tag). the character is discarded if the received a/d bit is zero (data tag). if the receiver is enabled, all received characters are transferred to the cpu through the receiver holding register stack during read operations. in either case, the data bits are loaded into the data portion of the stack while the a/d bit is loaded into the status portion of the stack normally used for a parity error (usr n [pe]). framing error, overrun error, and break detection operate normally. the a/d bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. messages in this add1 txd transmitter enabled usr n [txrdy] c0 add2 11 inter nal module select a/d a/d a/d add1 rxd receiver enabled usr n [rxrdy] c0 add2 11 inter nal module select a/d a/d a/d 0 a/d 0 a/d (c0) status data (add 2) status data add 1 peripheral station master station umr1 n [pm] = 11 umr1 n [pm] = 11 umr1 n [pt] = 1 add 1 umr1 n [pt] = 0 c0 umr1 n [pt] = 2 add 2 umr1 n [pm] = 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-28 mcf5307 users manual operation mode may still contain error detection and correction information. one way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. 14.5.5 bus operation this section describes bus operation during read, write, and interrupt acknowledge cycles to the uart module. 14.5.5.1 read cycles the uart module responds to reads with byte data. reserved registers return zeros. 14.5.5.2 write cycles the uart module accepts write data as bytes. write cycles to read-only or reserved registers complete normally without exception processing, but data is ignored. note: the uart module is accessed by the cpu with zero wait states, as bclko is used for the uart module. 14.5.5.3 interrupt acknowledge cycles the uart module supplies the interrupt vector in response to a uart iack cycle. if uivr n is not initialized to provide a vector number, a spurious exception is taken if an interrupt is generated. this works in conjunction with the interrupt controller, which allows a programmable priority level. 14.5.6 programming the software owchart, figure 14-27, consists of the following: uart module initialization?these routines consist of sinit and chchk (sheets 1 and 2). before sinit is called at system initialization, the calling routine allocates 2 words on the system stack. on return to the calling routine, sinit passes uart status data on the stack. if sinit nds no errors, the transmitter and receiver are enabled. sinit calls chchk to perform the checks. when called, sinit places the uart in local loop-back mode and checks for the following errors: ? transmitter never ready ? receiver never ready ? parity error ? incorrect character received i/o driver routine?this routine (sheets 4 and 5) consists of inch, the terminal input character routine which gets a character from the receiver, and outch, which sends a character to the transmitter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-29 operation interrupt handling?consists of sirq (sheet 4), which is executed after the uart module generates an interrupt caused by a change-in-break (beginning of a break). sirq then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 14.5.6.1 uart module initialization sequence note: uart module registers can be accessed by word or byte operations, but only data byte d[7:0] is valid. table 14-14 shows the uart module initialization sequence. table 14-14. uart module initialization sequence register setting ucr n reset the receiver and transmitter. reset the mode pointer (misc[2 0] = 0b001). uivr n program the vector number for a uart module interrupt. uimr n enable the preferred interrupt sources. uacr n initialize the input enable control (iec bit). ucsr n select the receiver and transmitter clock. use timer as source if required. umr1 n if preferred, program operation of receiver ready-to-send (rxrts bit). select receiver-ready or fifo-full noti cation (rxrdy/ffull bit). select character or block error mode (err bit). select parity mode and type (pm and pt bits). select number of bits per character (b/cx bits). umr2 n select the mode of operation (cmx bits). if preferred, program operation of transmitter ready-to-send (txrts). if preferred, program operation of clear-to-send (txcts bit). select stop-bit length (sbx bits). ucr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-30 mcf5307 users manual operation figure 14-27. uart mode programming flowchart (sheet 1 of 5) serial module initiate: channel interrupts save channel status any errors ? enable receiver assert request to send return sinit chk1 enabla y n sinitr call chchk enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-31 operation figure 14-27. uart mode programming flowchart (sheet 2 of 5) y n chchk place channel in local loopback mode enable transmitter clear status word is transmitter ready ? waited too long ? waited too long ? n y send character to transmitter has character been received ? chchk txchk sndchr rxchk n y n set transmitter- never-ready flag set receiver- never-ready flag a b y y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-32 mcf5307 users manual operation figure 14-27. uart mode programming flowchart (sheet 3 of 5) b y n n a y a b y n return have framing error ? set framing error flag have parity error ? set parity error flag get character from receiver same as transmitted character ? set incorrect character flag disable transmitter restore to original mode frchk rstchn prchk chrchk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 14. uart modules 14-33 operation figure 14-27. uart mode programming flowchart (sheet 4 of 5) was irq caused by beginning of a break ? clear change-in- break status bit has end-of-break irq arrived yet ? clear change-in- break status bit remove break character from receiver fifo replace return address on system stack and monitor warm start address rte sirqr n y n does channel a receiver have a character ? place character in d0 n y abrki1 abrki y inch return sirq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14-34 mcf5307 users manual operation figure 14-27. uart mode programming flowchart (sheet 5 of 5) outch n y is transmitter ready ? send character to transmitter return f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 15. parallel port (general-purpose i/o) 15-1 chapter 15 parallel port (general-purpose i/o) this chapter describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. it includes a code example for setting up the parallel port. 15.1 parallel port operation the mcf5307 parallel port module has 16 signals, which are programmed as follows: the pin assignment register (par) selects the function of the 16 multiplexed pins. port a data direction register (paddr) determines whether pins con gured as parallel port signals are inputs or outputs. the port a data register (padat) shows the status of the parallel port signals. the operations of the par, paddr, and padat are described in the following sections. 15.1.1 pin assignment register (par) the pin assignment register (par), which is part of the system integration module (sim), de nes how each par bit determines each pin function, as shown in figure 15-1. if pp[9:8]/a[25:24] are unavailable because a[25:0] are needed for external addressing, pp[15:10]/a[31:26] can be con gured as general-purpose i/o. table 15-1 summarizes mcf5307 parallel port pins, described in detail in chapter 17, ?signal descriptions.? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field par15 par14 par13 par12 par11 par10 par9 par8 par7 par6 par5 par4 par3 par2 par1 par0 par[ n ] = 0 pp15 pp14 pp13 pp12 pp11 pp10 pp9 pp8 pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 par[ n ] = 1 a31 a30 a29 a28 a27 a26 a25 a24 tip dreq0 dreq1 tm2 tm1 tm0 tt1 tt0 reset determined by driving d4/addr_config with a 1 or 0 when rsti negates. the system is con gured as pp[15:0] if d4 is low; otherwise alternate pin functions selected by par[ n ] = 1 are used. r/w r/w address address mbar + 0x004 figure 15-1. parallel port pin assignment register (par) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
15-2 mcf5307 users manual parallel port operation 15.1.2 port a data direction register (paddr) the paddr determines the signal direction of each parallel port pin programmed as a general-purpose i/o port in the par. table 15-2 describes paddr elds. 15.1.3 port a data register (padat) the padat value for inputs corresponds to the logic level at the pin; for outputs, the value corresponds to the logic level driven onto the pin. note the following: padat has no effect on pins not con gured for general-purpose i/o. padat settings do not affect inputs. padat bit values determine the corresponding logic levels of pins con gured as outputs. table 15-1. parallel port pin descriptions pin description pp[15:8]/ a[31:24] msb of the address bus/parallel port. programmed through par[15 8]. if a par bit is 0, the associated pin functions as a parallel port signal. if a bit is 1, the pin functions as an address bus signal. if all pins are address signals, as much as 4 gbytes of memory space are available. tip /pp7 transfer-in-progress output/parallel port bit 7. programmed through par[7]. assertion indicates a bus transfer is in progress; negation indicates an idle bus cycle if the bus is still granted to the processor. note that tip is held asserted on back-to-back bus cycles. dreq [1:0]/ pp[6:5] dma request inputs/two bits of the parallel port. programmed through par[6 5]. these inputs are asserted by a peripheral device to request a dma transfer. tm[2:0]/ pp[4:2]] transfer type outputs/parallel port bits 4 2. programmed through par[4 2]. for dma transfers, these signals provide acknowledge information. for emulation transfers, tm[2:0] indicate user or data transfer types. for cpu space transfers, tm[2:0] are low. for interrupt acknowledge transfers, tm[2:0] carry the interrupt level being acknowledged. tt[1:0]/ pp[1:0] transfer type outputs/parallel port bits 1 0. programmed through par[1 0]. when the mcf5307 is bus master, it outputs these signals. they indicate the current bus access type. 15 0 field paddr reset 0000_0000_0000_0000 r/w r/w address address mbar + 0x244 figure 15-2. port a data direction register (paddr) table 15-2. paddr field description bits name description 15 0 paddr data direction bits. each data direction bit selects the direction of the signal as follows: 0 signal is de ned as an input. 1 signal is de ned as an output. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 15. parallel port (general-purpose i/o) 15-3 parallel port operation padat can be written to anytime. a read from padat returns values of corresponding pins con gured as general-purpose i/o in the par and designated as inputs by the paddr. table 15-3 shows relationships between padat bits and parallel port pins when padat is accessed. the effect differs when the parallel port pin is an input or output. the following results occur when a parallel port pin is con gured as an input: when the padat is read, the value returned is the logic value on the pin. when the padat is written, the register contents are updated without affecting the logic value on the pin. the following results occur when a parallel port pin is con gured as an output: when the padat is read, the register contents are returned and the pin is the logic value of the register. when the padat is written, the register contents are updated and the pin is the logic value of the register. these relationships are also described in table 15-3. note: although external devices cannot access the mcf5307?s on-chip memories or mbar, they can access any parallel port module registers in the sim. 15.1.4 code example the following code example shows how to set up the parallel port. here, pp[7:0] are general-purpose i/o, pp[3:0] are inputs, and pp[7:4] are outputs. 15 0 field padat reset 0000_0000_0000_0000 r/w r/w address address mbar+0x248 figure 15-3. port a data register (padat) table 15-3. relationship between padat register and parallel port pin (pp) pp status padat r/w effect on padat effect on pp input read register bit value is the pin s logic value no effect. source of logic value write register contents updated no effect on the logic value at the pin output read register contents are returned pin is the logic value of the register bit write register contents updated pin is the logic value of the register bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
15-4 mcf5307 users manual parallel port operation mbarx equ 0x00010000 par equ mbarx+0x004 paddr equ mbarx+0x244 padat equ mbarx+0x248 move.l #mbarx,d0 ;because mbar is an internal register, mbarx is used as movec d0, mbar ;label for the memory map address move.w #0x00ff,d0 move.w d0,par ;set up the par. pp[7:0] set up as i/o move.w #0x00f0,d0 move.w d0,paddr ;set pp[7:4] as outputs; pp[3:0] as inputs move.b #0xa0,d0 move.b d0,padat ;0xa0 written into padat; pp[7:4] being outputs, ;pp[7:4] becomes 1010; i.e. pp7, pp5 = 1 and ;pp6, pp4 = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
part iv. hardware interface iv-i part iv hardware interface intended audience part iv is intended for hardware designers who need to know the functions and electrical characteristics of the mcf5407 interface. it includes a pinout, and both electrical and functional descriptions of the mcf5307 signals. it also describes how these signals interact to support the variety of bus operations shown in timing diagrams. contents part iv contains the following chapters: chapter 16, ?mechanical data,? provides a functional pin listing and package diagram for the mcf5307. chapter 17, ?signal descriptions,? provides an alphabetical listing of mcf5307 signals. this chapter describes the mcf5307 signals. in particular, it shows which are inputs or outputs, how they are multiplexed, which signals require pull-up resistors, and the state of each signal at reset. chapter 18, ?bus operation,? describes data transfers, error conditions, bus arbitration, and reset operations. it describes transfers initiated by the mcf5307 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. note that chapter 11, ?synchronous/asynchronous dram controller module,? describes dram cycles. chapter 19, ?ieee 1149.1 test access port (jtag),? describes con guration and operation of the mcf5307 jtag test implementation. it describes the use of jtag instructions and provides information on how to disable jtag functionality. chapter 20, ?electrical speci cations,? describes ac and dc electrical speci cations and thermal characteristics for the mcf5307. because additional speeds may have become available since the publication of this book, consult motorola?s coldfire web page, http://www.motorola.com/cold re, to con rm that this is the latest information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iv-ii mcf5307 users manual suggested reading the following literature may be helpful with respect to the topics in part iv: ieee standard test access port and boundary-scan architecture ieee supplement to standard test access port and boundary-scan architecture (1149.1) acronyms and abbreviations table iv-i describes acronyms and abbreviations used in part iv. table iv-i. acronyms and abbreviated terms term meaning bdm background debug mode bist built-in self test bsdl boundary-scan description language dma direct memory access dsp digital signal processing edo extended data output (dram) gpio i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lsb least-signi cant byte lsb least-signi cant bit mac multiple accumulate unit mbar memory base address register msb most-signi cant byte msb most-signi cant bit mux multiplex pclk processor clock pll phase-locked loop por power-on reset pqfp plastic quad at pack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
part iv. hardware interface iv-iii risc reduced instruction set computing rx receive sim system integration module tap test access port ttl transistor-to-transistor logic tx transmit table iv-i. acronyms and abbreviated terms (continued) term meaning f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iv-iv mcf5307 users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 16. mechanical data 16-1 chapter 16 mechanical data this chapter provides a function pin listing and package diagram for the mcf5307. see the website [http://www.motorola.com/cold re] for any updated information. 16.1 package the mcf5307 is assembled in a 208-pin, thermally enhanced plastic qfp package. 16.2 pinout the mcf5307 pinout is detailed in the following tables, including the primary and secondary functions of multiplexed signals. additional columns indicate the output drive capability of each pin, whether it is internally synchronized, and if the signal can change on a negative clock transition. these tables show mcf5307 pin numbers, including signal multiplexing. additional columns indicate the direction, description, and output drive capability of each pin. table 16-1. pins 1?2 (left, top-to-bottom) pin alternate function i/o description drive (ma) no name 1 vcc power input 2a0 i/o address bus bit 8 3a1 i/o address bus bit 8 4 gnd ground pin 5a2 i/o address bus bit 8 6a3 i/o address bus bit 8 7 vcc power input 8a4 i/o address bus bit 8 9a5 i/o address bus bit 8 10 gnd ground pin 11 a6 i/o address bus bit 8 12 a7 i/o address bus bit 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-2 mcf5307 users manual pinout 13 vcc power input 14 a8 i/o address bus bit 8 15 a9 i/o address bus bit 8 16 a10 i/o address bus bit 8 17 gnd ground pin 18 a11 i/o address bus bit 8 19 a12 i/o address bus bit 8 20 a13 i/o address bus bit 8 21 vcc power input 22 a14 i/o address bus bit 8 23 a15 i/o address bus bit 8 24 a16 i/o address bus bit 8 25 gnd ground pin 26 a17 i/o address bus bit 8 27 a18 i/o address bus bit 8 28 a19 i/o address bus bit 8 29 vcc power input 30 a20 i/o address bus bit 8 31 a21 i/o address bus bit 8 32 a22 i/o address bus bit 8 33 gnd ground pin 34 a23 i/o address bus bit 8 35 pp8 a24 i/o parallel port bit/address bus bit 8 36 pp9 a25 i/o parallel port bit/address bus bit 8 37 vcc power input 38 pp10 a26 i/o parallel port bit/address bus bit 8 39 pp11 a27 i/o parallel port bit/address bus bit 8 40 pp12 a28 i/o parallel port bit/address bus bit 8 41 gnd ground pin 42 pp13 a29 i/o parallel port bit/address bus bit 8 43 pp14 a30 i/o parallel port bit/address bus bit 8 44 pp15 a31 i/o parallel port bit/address bus bit 8 45 vcc power input 46 siz0 i/o size attribute 8 47 siz1 i/o size attribute 8 table 16-1. pins 1?2 (left, top-to-bottom) (continued) pin alternate function i/o description drive (ma) no name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 16. mechanical data 16-3 pinout 48 gnd ground pin 49 oe o output enable for chip selects 8 50 cs0 o chip select 8 51 cs1 o chip select 8 52 vcc power input table 16-2. pins 53?04 (bottom, left-to-right) pin alternate function i/o description drive (ma) no name 53 gnd ground pin 54 cs2 o chip select 8 55 cs3 o chip select 8 56 cs4 o chip select 8 57 vcc power input 58 cs5 o chip select 8 59 cs6 o chip select 8 60 cs7 o chip select 8 61 gnd ground pin 62 as i/o address strobe 8 63 r/w i/o read/wr ite 8 64 t a i/o transfer acknowledge 8 65 vcc power input 66 ts i/o transfer start 8 67 rsti i reset 68 irq7 i interrupt request 69 gnd ground pin 70 irq5 irq4 i interrupt request 71 irq3 irq6 i interrupt request 72 irq1 irq2 i interrupt request 73 vcc power input 74 br o bus request 8 75 bd o bus driven 8 76 bg i bus grant 77 gnd ground pin table 16-1. pins 1?2 (left, top-to-bottom) (continued) pin alternate function i/o description drive (ma) no name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-4 mcf5307 users manual pinout 78 tout1 o timer output 8 79 tout0 o timer output 8 80 tin0 i timer input 81 vcc power input 82 tin1 i timer input 83 ras0 o dram row address strobe 16 84 ras1 o dram row address strobe 16 85 gnd ground pin 86 cas0 o dram column address strobe 16 87 cas1 o dram column address strobe 16 88 cas2 o dram column address strobe 16 89 vcc power input 90 cas3 o dram column address strobe 16 91 dramw o dram write 16 92 sras o sdram row address strobe 16 93 gnd ground pin 94 scas o sdram column address strobe 16 95 scke o sdram clock enable 16 96 be0 bwe0 o byte enable/byte write enable 8 97 vcc power input 98 be1 bwe1 o byte enable/byte write enable 8 99 be2 bwe2 o byte enable/byte write enable 8 100 be3 bwe3 o byte enable/byte write enable 8 101 gnd ground pin 102 scl i/od 1 serial clock line 8 103 sda i/od 1 serial data line 8 104 gnd ground pin 1 od: open-drain output table 16-3. pins 105?56 (right, bottom-to-top) pin alternate function i/o description drive (ma) no name 105 vcc power input 106 d31 i/o data bus 8 table 16-2. pins 53?04 (bottom, left-to-right) (continued) pin alternate function i/o description drive (ma) no name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 16. mechanical data 16-5 pinout 107 d30 i/o data bus 8 108 d29 i/o data bus 8 109 gnd ground pin 110 d28 i/o data bus 8 111 d27 i/o data bus 8 112 d26 i/o data bus 8 113 vcc power input 114 d25 i/o data bus 8 115 d24 i/o data bus 8 116 d23 i/o data bus 8 117 gnd ground pin 118 d22 i/o data bus 8 119 d21 i/o data bus 8 120 d20 i/o data bus 8 121 vcc power input 122 d19 i/o data bus 8 123 d18 i/o data bus 8 124 d17 i/o data bus 8 125 gnd ground pin 126 d16 i/o data bus 8 127 d15 i/o data bus 8 128 d14 i/o data bus 8 129 vcc power input 130 d13 i/o data bus 8 131 d12 i/o data bus 8 132 d11 i/o data bus 8 133 gnd ground pin 134 d10 i/o data bus 8 135 d9 i/o data bus 8 136 d8 i/o data bus 8 137 vcc power input 138 d7 cs_conf2 i/o data bus/chip select con guration 8 139 d6 cs_conf1 i/o data bus/chip select con guration 8 140 d5 cs_conf0 i/o data bus/chip select con guration 8 141 gnd ground pin table 16-3. pins 105?56 (right, bottom-to-top) (continued) pin alternate function i/o description drive (ma) no name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-6 mcf5307 users manual pinout 142 d4 addr_conf i/o data bus/address con guration 8 143 d3 freq1 i/o data bus/clkin frequency 8 144 d2 freq0 i/o data bus/clkin frequency 8 145 vcc power input 146 d1 divide1 i/o data bus/divide control pclk:bclko 8 147 d0 divide0 i/o data bus/divide control pclk:bclko 8 148 gnd ground pin 149 dsclk trst i debug serial clock/jtag reset 150 tck tck i jtag clock 151 dso tdo o debug serial out/jtag data out 8 152 vcc power input 153 dsi tdi i debug serial input/jtag data in 154 bkpt tms i debug breakpoint/jtag mode select 155 hiz i high impedance override 156 gnd ground pin table 16-4. pins 157?08 (top, right - to - left) pin alternate function i/o description drive (ma) no name 157 vcc power input 158 cts1 i uart1 clear-to-send 159 r ts1 o uart1 request-to-send 8 160 rxd1 i uart1 receive data 161 txd1 o uart1 transmit data 8 162 gnd ground pin 163 cts0 i uart0 clear-to-send 164 r ts0 o uart0 request-to-send 8 165 rxd0 i uart0 receive data 166 txd0 o uart0 transmit data 8 167 vcc power input 168 edgesel i sdram bus clock edge select 169 gnd ground pin 170 bclko o bus clock output 16 table 16-3. pins 105?56 (right, bottom-to-top) (continued) pin alternate function i/o description drive (ma) no name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 16. mechanical data 16-7 pinout 171 vcc power input 172 rst o o processor reset output 8 173 gnd ground pin 174 clkin i clock input 175 vcc power input 176 mtmod0 i jtag/bdm select (tie high or low) 177 mtmod1 i tie high or low 178 pgnd pll ground pin 179 nc o 180 pvcc filter supply for pll 181 mtmod2 i tie high or low 182 mtmod3 i tie high or low 183 gnd ground pin 184 pstclk o processor status clock 8 185 vcc power input 186 ddata0 o debug data 8 187 ddata1 o debug data 8 188 gnd ground pin 189 ddata2 o debug data 8 190 ddata3 o debug data 8 191 vcc power input 192 pst0 o processor status 8 193 pst1 o processor status 8 194 gnd ground pin 195 pst2 o processor status 8 196 pst3 o processor status 8 197 vcc power input 198 pp7 tip i/o parallel port bit/transfer in progress 8 199 pp6 dreq0 i/o parallel port bit/dma request 8 200 pp5 dreq1 i/o parallel port bit/dma request 8 201 gnd ground pin 202 pp4 tm2 i/o parallel port bit/transfer modi er 8 203 pp3 tm1 i/o parallel port bit/transfer modi er 8 204 pp2 tm0 i/o parallel port bit/transfer modi er 8 205 vcc power input table 16-4. pins 157?08 (top, right - to - left) (continued) pin alternate function i/o description drive (ma) no name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-8 mcf5307 users manual mechanical diagram 16.3 mechanical diagram figure 16-1 is a mechanical diagram of the 208-pin qfp mcf5307. 206 pp1 tt1 i/o parallel port bit/transfer type 8 207 pp0 tt0 i/o parallel port bit/transfer type 8 208 gnd ground pin table 16-4. pins 157?08 (top, right - to - left) (continued) pin alternate function i/o description drive (ma) no name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 16. mechanical data 16-9 case drawing figure 16-1. mechanical diagram 16.4 case drawing figure 16-2 and figure 16-3 show the mcf5307 case drawings. vcc a0 a1 gnd a2 a3 vcc a4 a5 gnd a6 a7 vcc a8 a9 a10 gnd a11 a12 a13 vcc a14 a15 a16 gnd a17 a18 a19 vcc a20 a21 a22 gnd a23 pp8 pp9 vcc pp10 pp11 pp12 gnd pp13 pp14 pp15 vcc siz0 siz1 gnd oe cs0 cs1 vcc gnd cs2 cs3 cs4 vcc cs5 cs6 cs7 gnd as r/w t a vcc ts rsti irq7 gnd irq5 irq3 irq1 vcc br bd bg gnd tout1 tout0 tin0 vcc tin1 ras0 ras1 gnd cas0 cas1 cas2 vcc cas3 dramw sras gnd scas scke be0 vcc be1 be2 be3 gnd scl sda gnd vcc d31 d30 d29 gnd d28 d27 d26 vcc d25 d24 d23 gnd d22 d21 d20 vcc d19 d18 d17 gnd d16 d15 d14 vcc d13 d12 d11 gnd d10 d9 d8 vcc d7 d6 d5 gnd d4 d3 d2 vcc d1 d0 gnd dsclk tck dso vcc dsi bkpt hiz gnd vcc cts1 r ts1 rxd1 txd1 gnd cts0 r ts0 rxd0 txd0 vcc edgesel gnd bclko vcc rst o gnd clkin vcc mtmod0 mtmod1 pgnd nc pvcc mtmod2 mtmod3 gnd pstclk vcc ddata0 ddata1 gnd ddata2 ddata3 evcc pst0 pst1 gnd pst2 pst3 vcc pp7 pp6 pp5 gnd pp4 pp3 pp2 vcc pp1 pp0 gnd 1 52 53 104 105 208 157 156 10 5 10 15 20 25 30 35 40 45 50 145 150 140 135 130 125 120 115 110 105 155 60 55 65 70 75 80 85 90 95 100 200 205 195 190 185 180 175 170 165 160 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-10 mcf5307 users manual case drawing figure 16-2. mcf5307 case drawing (general view) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 16. mechanical data 16-11 case drawing figure 16-3. case drawing (details) the dimensions in figure 16-2 and figure 16-3 are referenced in table 16-5. table 16-5. dimensions reference dimension (millimeters) minimum maximum a 4.10 a1 0.25 0.50 a2 3.20 3.60 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 d 30.60 bsc view a: three places section a-a: 160 places rotated 90?cw view b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-12 mcf5307 users manual case drawing d1 28.00 bsc e 0.50 bsc e 30.60 bsc e1 28.00 bsc l 0.45 0.75 l1 1.30 ref r1 0.08 r2 0.08 0.25 s 0.20 ? 0* 8* ? 10* ? 2 5* 16* table 16-5. dimensions (continued) reference dimension (millimeters) minimum maximum f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-1 chapter 17 signal descriptions this chapter describes mcf5307 signals. it includes an alphabetical listing of signals, showing multiplexing, whether it is an input or output to the mcf5307, the state at reset, and whether a pull-up resistor should be used. the following chapter, chapter 18, ?bus operation,? describes how these signals interact. note: the terms ?assertion? and ?negation? are used to avoid confusion when dealing with a mixture of active-low and active-high signals. the term ?asserted? indicates that a signal is active, independent of the voltage level. the term ?negated? indicates that a signal is inactive. active-low signals, such as sras and t a , are indicated with an overbar. 17.1 overview figure 17-1 shows the block diagram of the mcf5307 with the signal interface. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-2 mcf5307 users manual overview figure 17-1. mcf5307 block diagram with signal interfaces table 17-1 lists the mcf5307 signals grouped by functionality. tdo/dso tdi/dsi tms/bkpt tck parallel interface chip uart0 serial i/o clkin tin[1:0] tout[1:0] t a r/w siz[1:0] d[31:0] a[23:0] irq7 irq5 irq3 jtag port selects coldfire v3 core 4-kbyte sram mac bus txd0 rxd0 r ts0 cts0 txd1 rxd1 r ts1 cts1 ras [1:0] cas [3:0] dramw 2 4 24 32 be[ 3:0]/bwe [3:0] cs [7:0] 8 4 2 as br bg bd trst /dsclk hiz rsti port 1 2 2 2 test controller irq1 oe dma pstclk bclko 2 dreq [1:0]/ sras scas scke a[31:24]/pp[15:8] 8 ts tm[2:0]/pp[4:2] 2 4 mtmod[3:0] 4 edgesel tt[1:0]]/pp[1:0] rst o tip /pp7 i 2 c module 2 scl sda 1 note: parallel port pins (pp n ) are multiplexed with other bus functions as shown. 2 i 2 c is a philips proprietary interface internal bus arbiter external to internal bus uart1 serial i/o dual timer module interrupt controller dram controller system module 8-kbyte pp[6:5] integration module ddata[3:0] debug module div (sim) pll unified cache 4 pst[3:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-3 overview table 17-1. mcf5307 signal index signal name abbreviation function i/o reset pull-up page section 17.2, ?cf5307 bus signals 17-7 address a[31:0] 32-bit address bus. a[4:2] indicate the interrupt level for external interrupts. i/o three state 17-7 data d[31:0] data bus. d[7:0] are loaded at reset for bus con guration. i/o three state 17-8 read/write r/w identi es read and write transfers i/o three state up 17-8 size siz[1:0] indicates the data transfer size i/o three state 17-8 transfer start ts indicates the start of a bus transfer i/o three state 17-9 address strobe as indicates a bus cycle has been initiated and address is stable i/o three state up 17-9 transfer acknowledge t a assertion terminates transfer synchronously i/o three state up 17-9 transfer in progress tip /pp7 indicates a bus cycle is in progress; multiplexed with pp7 o parallel port 17-10 transfer type tt[1:0] indicates transfer type: normal, cpu space, emulator mode, or dma; multiplexed with pp[1:0] o parallel port 17-10 transfer modi er tm[2:0] provides transfer modi er information; multiplexed with pp[4:2]. o parallel port 17-10 section 17.3, ?nterrupt control signals 17-12 interrupt request irq7 , irq5 , irq3 , irq1 four external interrupts are set to default levels 1,3,5,7; user-alterable. i up 17-12 section 17.4, ?us arbitration signals 17-12 bus request br indicates processor needs bus o high 17-12 bus grant bg arbiter asserts to grant mastership. i note 1 17-12 bus driven bd indicates processor is driving bus o high 17-13 section 17.5, ?lock and reset signals 17-13 reset in rsti processor reset input i up 17-13 clock input clkin input used to clock internal logic i 17-13 bus clock out bclko bus clock reference output o 17-13 reset out rst o processor reset output o low 17-13 auto-acknowledge con guration 2 aa_config controls auto acknowledge timing for cs0 at reset i 17-14 port size con guration 2 ps_config[1:0] controls port size for cs0 at reset i user cfg 17-14 address con guration 2 addr_config programs parallel i/o ports i user cfg 17-14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-4 mcf5307 users manual overview frequency control pll freq[1:0] indicates clkin frequency range. i 17-15 divide control pclk to bclko divide[1:0] indicates the bclko/pstclk ratio. i 17-15 section 17.6, ?hip-select module signals 17-15 chip selects[7:0] cs[ 7:0] enables peripherals at programmed addresses; cs0 provides boot rom selection. o high 17-16 byte enable[3:0]/ byte write enable[3:0] be [3:0]/ bwe [3:0] be [3:0] select bytes in memory. o high 17-16 output enable oe output enable for chip select read cycles o high 17-16 section 17.7, ?ram controller signals 17-16 row address strobe ras [1:0] dram row address strobe o high 17-16 column address strobe cas [3:0] dram column address strobe o high 17-16 dram write dramw asserted for dram write; negated for dram read o high 17-17 synchronous column address strobe scas sdram column address strobe o high 17-17 synchronous row address strobe sras sdram row address strobe o high 17-17 synchronous clock enable scke clock enable for external sdram o low 17-17 synchronous edge select edgesel timing select for external sdram i user cfg 17-17 section 17.8, ?ma controller module signals 17-17 dma request dreq [1:0] external dma transfer request; multiplexed with pp[6:5] i 17-18 section 17.9, ?erial module signals 17-18 receive data rxd[1:0] receive serial data input for uart i 17-18 transmit data txd[1:0] transmit serial data output for uart o high 17-18 request-to-send r ts [1:0] uart asserts when ready to receive data query. o high 17-18 clear-to-send cts [1:0] signals uart that data can be sent to peripheral i 17-18 section 17.10, ?imer module signals 17-18 timer input tin[1:0] clock input to timer or trigger to timer value capture logic i 17-19 timer outputs tout[1:0] outputs waveform or pulse. o high 17-19 section 17.11, ?arallel i/o port (pp[15:0]) 17-19 table 17-1. mcf5307 signal index (continued) signal name abbreviation function i/o reset pull-up page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-5 overview table 17-2 lists signals in alphabetical order by abbreviated name. parallel port pp[15:0] interfaces with i/o; multiplexed with bus address and attribute signals. i/o input 17-19 section 17.12, ? 2 c module signals 17-19 serial clock line scl clock signal for i 2 c operation i/o open drain up 17-19 serial data line sda serial data port for i 2 c operation i/o open drain up 17-19 section 17.13, ?ebug and test signals 17-20 motorola test mode mtmod0 puts processor in functional or emulator mode i user cfg 17-20 motorola test mode mtmod[3:1] reserved i down 17-20 high impedance hiz assertion three-states all outputs i up 17-20 processor clock out pstclk output clock used for pstddata o 17-20 processor status pst[3:0] displays captured processor data . o driven 17-20 debug data ddata[3:0] displays captured processor data and breakpoint status. o driven 17-20 section 17.14, ?ebug module/jtag signals 17-21 test clock tck clock signal for ieee 1149.1 jtag i low 17-23 test reset/ development serial clock trst /dsclk asynchronous reset for jtag; debug module clock input i up 17-21 test mode select/ breakpoint tms/bkpt tms (jtag)/hardware breakpoint (debug) i up 17-22 test data input/ development serial input tdi/dsi multiplexed serial input for the jtag or background debug module i up 17-22 test data output/ development serial output tdo/dso multiplexed serial output for the jtag or background debug module o driven 17-22 1 if there is no arbiter, bg should be tied low; otherwise, it should be negated. 2 these data pins are sampled at reset for con guration. table 17-2. mcf507 alphabetical signal index abbreviation signal name function i/o page aa_config auto-acknowledge con guration clock/reset i 17-14 addr_config address con guration clock/reset i 17-14 as address strobe bus i/o 17-9 a[31:0] address bus i/o 17-7 table 17-1. mcf5307 signal index (continued) signal name abbreviation function i/o reset pull-up page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-6 mcf5307 users manual overview bclko bus clock out clock/reset o 17-13 bd bus driven bus arbitration o 17-13 be [3:0]/bwe [3:0] byte enable[3:0]/byte write enable[3:0] chip select o 17-16 bg bus grant bus arbitration i 17-12 br bus request bus arbitration o 17-12 cas [3:0] column address strobe dram o 17-16 clkin clock input clock/reset i 17-13 cs[ 7:0] chip selects[7:0] uart o 17-16 cts [1:0] clear-to-send serial module i 17-18 ddata[3:0] debug data debug o 17-20 clock/reset i 17-15 dramw dram write dram o 17-17 dreq [1:0] dma request dma i 17-18 d[31:0] data bus i/o 17-8 edgesel sync edge select dram i 17-17 clock/reset i 17-15 hiz high impedance debug i 17-20 irq7 , irq5 , irq3 , irq1 interrupt request interrupt control i 17-12 mtmod[3:0] motorola test mode debug i 17-20 oe output enable chip select o 17-16 pp[15:0] parallel port parallel port i/o 17-19 pstclk processor clock out debug o 17-20 pst[:0] processor status debug o 17-20 ps_config[1:0] port size con guration clock/reset i 17-14 r/w read/write bus i/o 17-8 ras [1:0] row address strobe dram o 17-16 rsti reset in clock/reset i 17-13 rst o reset out clock/reset o 17-13 r ts [1:0] request-to-send serial module o 17-18 rxd[1:0] receive data serial module i 17-18 scas synchronous column address strobe dram o 17-17 scke synchronous clock enable dram o 17-17 scl serial clock line i 2 c i/o 17-19 sda serial data line i 2 c i/o 17-19 siz[1:0] size bus i/o 17-8 table 17-2. mcf507 alphabetical signal index (continued) abbreviation signal name function i/o page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-7 mcf5307 bus signals 17.2 mcf5307 bus signals the bus signals provide the external bus interface to the mcf5307. 17.2.1 address bus the address bus provides the address of the byte or most-signi cant byte (msb) of the word or longword being transferred. the address lines also serve as the dram addressing, providing multiplexed row and column address signals. when an external device has ownership of the mcf5307 bus, the device must drive the address bus and assert ts or as to indicate the start of a bus cycle. during an interrupt acknowledge access, a[4:2] indicate the interrupt level being acknowledged. 17.2.1.1 address bus (a[23:0]) the lower 24 bits of the address bus become valid when ts is asserted. a[4:2] indicate the interrupt level during interrupt acknowledge cycles. 17.2.1.2 address bus (a[31:24]/pp[15:8]) these multiplexed pins can serve as the most-signi cant byte of the address bus, or as the most-signi cant byte of the parallel port. programming the par in the system integration module (sim) determines the function of each of these eight multiplexed pins. these pins are programmable on a bit-by-bit basis. sras synchronous row address strobe dram o 17-17 t a transfer acknowledge bus i/o 17-9 tck test clock jtag i 17-23 tdi/dsi test data input/development serial input jtag i 17-22 tdo/dso test data output/development serial output jtag o 17-22 tin[1:0] timer input timer i 17-19 tip transfer in progress bus o 17-10 tms/bkpt test mode select/breakpoint jtag i 17-22 tm[2:0] transfer modi er bus o 17-10 tout[1:0] timer outputs timer o 17-19 trst /dsclk test reset/development serial clock jtag i 17-21 ts transfer start bus i/o 17-9 tt[1:0] transfer type bus o 17-10 txd[1:0] transmit data serial module o 17-18 table 17-2. mcf507 alphabetical signal index (continued) abbreviation signal name function i/o page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-8 mcf5307 users manual mcf5307 bus signals a[31:24]?pins are con gured as address bits by setting corresponding par bits; they represent the most-signi cant address bus bits. as much as 4 gbytes of memory are available when all of these pins are programmed as address signals. pp[15:8]?pins are con gured as parallel port signals by clearing corresponding par bits; these represent the most-signi cant parallel port bits. 17.2.2 data bus (d[31:0]) the data bus is bidirectional and non-multiplexed. data is sampled by the mcf5307 on the rising bclko edge. the data bus port width, wait states, and internal termination are initially de ned for the boot chip select by d[7:0] during reset. the port width for each chip select and dram bank are programmable. the data bus uses a default con guration if none of the chip selects or dram bank match the address decode. the default con guration is a 32-bit port with external termination and burst-inhibited transfers. the data bus can transfer byte, word, or longword data widths. all 32 data bus signals are driven during writes, regardless of port width and operand size. d[7:0] are used during reset initialization as inputs to con gure the functions as described in table 17-3. they are de ned in section 17.5.5, ?data/con guration pins (d[7:0]).? 17.2.3 read/write (r/w ) when the mcf5307 is the bus master, it drives the r/w signal to indicate the direction of subsequent data transfers. it is driven high during read bus cycles and driven low during write bus cycles. this signal is an input during an external master access. 17.2.4 size (siz[1:0]) when it is the bus master, the mcf5307 outputs these signals to indicate the requested data transfer size. table 17-4 shows the de nition of the bus request size encodings. when the mcf5307 device is not the bus master, these signals function as inputs. note that for misaligned transfers, siz[1:0] indicate the size of each transfer. for example, if a longword access occurs at a misaligned offset of 0x1, a byte is transferred rst (siz[1:0] table 17-3. data pin configuration pin function section d7 auto-acknowledge con guration (aa_config) section 17.5.5.2, d7 auto acknowledge con guration (aa_config) d[6:5] port size con guration (ps_config[1:0]) section 17.5.5.3, d[6:5] port size con guration (ps_config[1:0]) d4 address con guration (addr_config/d4) section 17.5.6, d4 address con guration (addr_config) d[3:2] frequency control pll (freq[1:0]) section 17.5.7, d[3:2] frequency control pll (freq[1:0] ) d[1:0] divide control (divide[1:0]) section 17.5.8, d[1:0] divide control pclk to bclko (divide[1:0]) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-9 mcf5307 bus signals = 01), a word is next transferred at offset 0x2 (siz[1:0] = 10), then the nal byte is transferred at offset 0x4 (siz[1:0] = 01). for aligned transfers larger than the port size, siz[1:0] behaves as follows: if bursting is used, siz[1:0] stays at the size of transfer. if bursting is inhibited, siz[1:0] rst shows the size of the transfer and then shows the port size. for burst-inhibited transfers, siz[1:0] changes with each ts assertion to re ect the next transfer size. for transfers to port sizes smaller than the transfer size, siz[1:0] indicates the size of the entire transfer on the rst access and the size of the current port transfer on subsequent transfers. for example, for a longword write to an 8-bit port, siz[1:0] = 00 for the rst byte transfer and 01 for the next three. 17.2.5 transfer start (ts ) the mcf5307 asserts ts during the rst clock cycle when address and attributes (tm, tt, tip , r/w , and siz) are valid. ts is negated in the following clock cycle. when the mcf5307 is not the bus master, ts is an input. 17.2.6 address strobe (as ) address strobe (as ) is asserted to indicate when the address is stable at the start of a bus cycle. the address and attributes are guaranteed to be valid during the entire period that as is asserted. this signal is asserted and negated on the falling edge of the clock. when the mcf5307 is not the bus master, as is an input. 17.2.7 transfer acknowledge (t a ) when the mcf5307 is bus master, the external system drives this input to terminate the bus transfer. the bus continues to be driven until this synchronous signal is asserted. for write cycles, the processor continues to drive data one clock after t a is asserted. during read cycles, the peripheral must continue to drive data until t a is recognized. if all bus cycles support fast termination, ta can be tied low. however, note that t a cannot be tied low if potential external bus masters are present. the mcf5307 drives ta for an table 17-4. bus cycle size encoding siz[1:0] port size 00 longword 01 byte 10 word 11 line f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-10 mcf5307 users manual mcf5307 bus signals external master access. this condition is indicated by the am bit in the chip-select mask register (csmr) being cleared. see chapter 10, ?chip-select module.? 17.2.8 transfer in progress (tip /pp7) the tip /pp7 pin is programmed in the par to serve as the transfer-in-progress output or as a parallel port bits. the tip output is asserted indicating a bus transfer is in progress. it is negated during idle bus cycles if the bus is still granted to the processor. it is three-stated for external master accesses. note that tip is held asserted on back-to-back bus cycles. 17.2.9 transfer type (tt[1:0]/pp[1:0]) the tt[1:0]/pp[1:0] pins are programmed in the par to serve as the transfer type outputs or as two parallel port bits. when the mcf5307 is bus master and tt[1:0] are enabled, these signals are driven as outputs only. if an external master owns the bus and tt[1:0] are enabled, these pins are three-stated by the mcf5307 and can be driven by the external master. table 17-5 shows the de nition of the encodings. 17.2.10 transfer modi?r (tm[2:0]/pp[4:2]) the tm[2:0]/pp[4:2] pins are programmed in the par to serve as the transfer modi er outputs or as three parallel port bits. these outputs provide supplemental information for each transfer type; see table 17-6 through table 17-10. when the mcf5307 is the bus master and tm[2:0] are enabled, these signals are driven as outputs only. if an external device is bus master and tm[2:0] are enabled, these pins are three-stated by the mcf5307 and can be driven by the external master. table 17-5. bus cycle transfer type encoding tt[1:0] transfer type 00 normal access 01 dma access 10 emulator access 11 cpu space or interrupt acknowledge table 17-6. tm[2:0] encodings for tt = 00 (normal access) tm[2:0] transfer modi?r 000 cache push access 001 user data access 010 user code access 011 100 reserved 101 supervisor data access f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-11 mcf5307 bus signals as shown in table 17-7, if the dma is bus master (tt = 01), tm[2:0] indicate the type of dma access and provide the dma acknowledgement information for channels 0 and 1. note: when tt= 01, the tm0 encoding is independent from tm[2:1] encoding. table 17-9 shows tm[2:0] encodings for emulator mode accesses. the tm signals indicate user or data transfer types during emulation transfers, while for interrupt acknowledge transfers, the tm signals carry the interrupt level being acknowledged; see table 17-10. 110 supervisor code access 111 reserved table 17-7. tm 0 encoding for dma as master (tt = 01) tm0 transfer modi?r encoding 0 single-address access negated 1 single-address access table 17-8. tm[ 2: 1] encoding for dma as master (tt = 01) tm[2:1] transfer modi?r encoding 00 dma acknowledges negated 01 dma acknowledge, channel 0 10 dma acknowledge, channel 1 11 reserved table 17-9. tm[2:0] encodings for tt = 10 (emulator access) tm[2:0] transfer modi?r 000 100 reserved 101 emulator mode data access 110 emulator mode code access 111 reserved table 17-10. tm[2:0] encodings for tt = 11 (interrupt level) tm[2:0] transfer modi?r 000 cpu space 001 interrupt level 1 acknowledge table 17-6. tm[2:0] encodings for tt = 00 (normal access) (continued) tm[2:0] transfer modi?r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-12 mcf5307 users manual interrupt control signals 17.3 interrupt control signals the interrupt control signals supply the external interrupt level to the mcf5307 device. 17.3.1 interrupt request ( irq1 /irq2 , irq3 /irq6 , irq5 /irq4 , and irq7 ) the irq1 , irq3 , irq5 , and irq7 signals are the default interrupt request signals (irq n ). however, by setting the appropriate bit in the interrupt port assignment register (irqpar), irq1 , irq3 , and irq5 can be changed to function as irq2 , irq6 , and irq4 , respectively. see section 9.2.4, ?interrupt port assignment register (irqpar).? 17.4 bus arbitration signals the bus arbitration signals provide the external bus arbitration control for the mcf5307. 17.4.1 bus request (br ) the br output indicates to an external arbiter that the processor is requesting to be bus master for one or more bus cycles. br is negated when the mcf5307 begins an access to the external bus with no other internal accesses pending. br remains negated until another internal request occurs. 17.4.2 bus grant (bg ) an external arbiter asserts the bg input to indicate that the mcf5307 can take control of the bus on the next rising edge of bclko. when the arbiter negates bg , the mcf5307 will release the bus as soon as the current transfer completes. the external arbiter must not grant the bus to any other master until both bd and bg are negated. 010 interrupt level 2 acknowledge 011 interrupt level 3 acknowledge 100 interrupt level 4 acknowledge 101 interrupt level 5 acknowledge 110 interrupt level 6 acknowledge 111 interrupt level 7 acknowledge table 17-10. tm[2:0] encodings for tt = 11 (interrupt level) (continued) tm[2:0] transfer modi?r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-13 clock and reset signals 17.4.3 bus driven (bd ) the mcf5307 asserts bd to indicate that it is the current master and is driving the bus. the mcf5307 behaves as follows: if the mcf5307 is the bus master but is not using the bus, bd is asserted. if the mcf5307 loses mastership during a transfer, it completes the last transfer of the access, negates bd , and three-states all bus signals on the rising edge of bclko. if the mcf5307 loses bus mastership during an idle clock cycle, it three-states all bus signals on the rising edge of bclko. bd cannot be negated unless bg is negated. 17.5 clock and reset signals the clock and reset signals con gure the mcf5307 and provide interface signals to the external system. 17.5.1 reset in (rsti ) asserting rsti causes the mcf5307 to enter reset exception processing. when rsti is recognized, br and bd are negated and the address bus, data bus, tt, siz, r/w , as , and ts are three-stated. rst o is asserted automatically when rsti is asserted. 17.5.2 clock input (clkin) clkin is the mcf5307 input clock frequency to the on-board phase-locked-loop (pll) clock generator. clkin is used to internally clock or sequence the mcf5307 internal bus interface at a selected multiple of the input frequency used for internal module logic. 17.5.3 bus clock output (bclko) the internal pll generates bclko and can be programmed to be 1/2, 1/3, or 1/4 of the processor clock frequency. bclko should be used as the bus timing reference. 17.5.4 reset out (rst o ) after rsti is asserted, the pll temporarily loses its lock, during which time rst o is asserted. when the pll regains its lock, rst o negates again. this signal can be used to reset external devices. 17.5.5 data/con?uration pins (d[7:0]) this section describes data pins, d[7:0], that are read at reset for con guration. table 17-11 shows pin assignments. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-14 mcf5307 users manual clock and reset signals 17.5.5.1 d[7:5boot chip-select (cs0 ) con?uration d[7:5] determine defaults for the global chip select (cs0 ), the only chip select valid at reset. these signals correspond to bits in chip-select con guration register 0 (cscr0). 17.5.5.2 d7?uto acknowledge con?uration (aa_config) at reset, the enabling and disabling of auto acknowledge for boot cs0 is determined by the logic level driven on d7 at the rising edge of rsti . aa_config is multiplexed with d7 and sampled only at reset. the d7 logic level is re ected as the reset value of cscr[aa]. table 17-12 shows how the d7 logic level corresponds to the auto acknowledge timing for cs0 at reset. note that auto acknowledge can be disabled by driving a logic 0 on d7 at reset. 17.5.5.3 d[6:5]?ort size con?uration (ps_config[1:0]) the default port size value of the boot cs0 is determined by the logic levels driven on d[6:5] at the rising edge of rsti , which are re ected as the reset value of cscr[ps]. table 17-13 shows how the logic levels of d[6:5] correspond to the cs0 port size at reset. 17.5.6 d4?ddress con?uration (addr_config) the address con guration signal (addr_config) programs the par of the parallel i/o port to be either parallel i/o or to be the upper address bus bits along with various attribute and control signals at reset to give the user the option to access a broader addressing range table 17-11. data pin configuration pin function d7 auto-acknowledge con guration (aa_config) d[6:5] port size con guration (ps_config[1:0]) d4 address con guration (addr_config/d4) d[3:2] frequency control pll (freq[1:0]) d[1:0] divide control (divide[1:0]) table 17-12. d7 selection of cs0 automatic acknowledge d7 (cscr0[aa]) boot cs0 aa 0 disabled 1 enabled with 15 wait states table 17-13. d6 and d5 selection of cs0 port size d[6:5] (cscr0[ps]) boot cs0 port size 00 32-bit port 01 8-bit port 1x 16-bit port f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-15 chip-select module signals of memory if desired. addr_config is multiplexed with d4 and its con guration is sampled at reset as shown in table 17-14. 17.5.7 d[3:2]?requency control pll (freq[1:0]) the frequency control pll input bus (freq[1:0]) indicates the clkin frequency range. these signals are multiplexed with d[3:2] and are sampled during the assertion of reset . these signals indicate the operating frequency range to the pll, as shown in table 17-15. note that these signals do not affect the pll frequency but are required to set up the analog pll. 17.5.8 d[1:0]?ivide control pclk to bclko (divide[1:0]) this 2-bit input bus indicates the bclko/pstclk ratio. these signals are sampled during the assertion of reset and indicate the ratios shown in table 17-16. 17.6 chip-select module signals the mcf5307 device provides eight programmable chip-select signals that can directly interface with sram, eprom, eeprom, and peripherals. these signals are asserted and negated on the falling edge of the clock. table 17-14. d4/addr_config, address pin assignment d4/addr_config par con?uration at reset 0 pp[15:0], defaulted to inputs upon reset 1 a[31:24]/tip /dreq [1:0]/tm[2:0]/tt[1:0] table 17-15. clkin frequency freq[1:0]/d[3:2] clkin frequency (mhz) 00 16.6 27.999 01 28 38.999 10 39 45 11 reserved table 17-16. bclko/pstclk divide ratios divide[1:0]/d[1:0] ratio of bclko/pstclk 00 1/4 01 reserved 10 1/2 11 1/3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-16 mcf5307 users manual dram controller signals 17.6.1 chip-select (cs [7:0]) each chip select can be programmed for a base address location and for masking addresses, port size and burst-capability indication, wait-state generation, and internal/external termination. reset clears all chip select programming; cs 0 is the only chip select initialized out of reset. cs 0 is also unique because it can function at reset as a global chip select that allows boot rom to be selected at any de ned address space. port size and termination (internal vs. external) for boot cs 0 are con gured by the levels on d[7:5] on the rising edge of rsti , as described in section 17.5.5.1, ?d[7:5boot chip-select (cs0) con guration.? the chip-select implementation is described in chapter 10, ?chip-select module.? 17.6.2 byte enables/byte write enables (be [3:0]/bwe [3:0]) the four byte enables are multiplexed with the mcf5307 byte-write-enable signals. each pin can be individually programmed through the chip-select control registers (cscrs). for each chip select, assertion of byte enables for reads and byte-write enables for write cycles can be programmed. alternatively, users can program byte-write enables to assert on writes and no byte enable assertion for read transfers. 17.6.3 output enable (oe ) the output enable (oe ) signal is sent to the interfacing memory and/or peripheral to enable a read transfer. oe is asserted only when a chip select matches the current address decode. 17.7 dram controller signals the dram signals in the following sections interface to external dram. dram with widths of 8, 16, and 32 bits are supported and can access as much as 512 mbytes of dram. 17.7.1 row address strobes (ras [1:0]) the row address strobes (ras [1:0]) interface to ras inputs on industry-standard adrams. when sdrams are used, these signals interface to the chip-select lines of the sdrams within a memory block. thus, there is one ras line for each memory block. 17.7.2 column address strobes (cas [3:0]) the column address strobes (cas [3:0]) interface to cas inputs on industry-standard drams. these provide cas for a given adram block. when sdrams are used, cas signals control the byte enables for standard sdrams (referred to as dqm x ). cas3 accesses the lsb and cas0 accesses the msb of data. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-17 dma controller module signals 17.7.3 dram write (dramw ) the dram write signal (dramw ) is asserted to signify that a dram write cycle is underway. a read bus cycle is indicated by the negation of dramw . 17.7.4 synchronous dram column address strobe (scas ) the synchronous dram column address strobe (scas ) is registered during synchronous mode to route directly to the scas signal of sdrams. 17.7.5 synchronous dram row address strobe (sras ) the synchronous dram row address strobe output (sras ) is registered during synchronous mode to route directly to the sras signal of external sdrams. 17.7.6 synchronous dram clock enable (scke) the synchronous dram clock enable output (scke) is registered during synchronous mode to route directly to the scke signal of external sdrams. this signal provides the clock enable to the sdram. 17.7.7 synchronous edge select (edgesel) the synchronous edge select input (edgesel) helps select additional output hold times for signals that interface to external sdrams. it provides the following three modes of operation for sdram control signals: when edgesel is tied high, sdram control signals change on the rising edge of bclko. when edgesel is tied low, sdram control signals change on the falling edge of bclko. when edgesel is tied to the external clock (normally buffered bclko), which drives the sdram and other devices, sdram signals are generated within the mcf5307 make a transition on the rising edge of the sdram clock. see figure 11-14 on page 11-19. this loop-back con guration provides additional output hold time for mcf5307 interface signals provided to the sdram. in this case, the sdram clock operates at the bclko frequency, with a possible slight phase delay. 17.8 dma controller module signals the dma controller module uses the signals in the following subsections to provide external request for either a source or destination. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-18 mcf5307 users manual serial module signals 17.8.1 dma request (dreq [1:0]/pp[6:5]) the dma request pins (dreq [1:0]/pp[6:5]) can serve as the dma request inputs or as two bits of the parallel port, as determined by individually programmable bits in the par. these inputs are asserted by a peripheral device to request an operand transfer between that peripheral and memory by either channel 0 or 1 of the on-chip dma. note that dma acknowledge indication is displayed on tm[2:0], during dma transfers of channel 0 and 1. 17.9 serial module signals the signals in the following sections are used to transfer serial data between the two uart modules and external peripherals. 17.9.1 transmitter serial data output (txd) txd is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loop-back mode. data is shifted out least-signi cant bit (lsb) rst on txd on the falling edge of the clock source. 17.9.2 receiver serial data input (rxd) data received on rxd is sampled on the rising edge of the clock source, with the lsb received rst. 17.9.3 clear to send (cts ) this input can generate an interrupt on a change of state. 17.9.4 request to send (r ts ) this output can be programmed to be negated or asserted automatically by either the receiver or the transmitter. when connected to a transmitter?s cts , r ts can control serial data ow. 17.10 timer module signals the signals in the following sections are external interfaces to the two general-purpose mcf5307 timers. these 16-bit timers can capture timer values, trigger external events or internal interrupts, or count external events. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-19 parallel i/o port (pp[15:0]) 17.10.1 timer inputs (tin[1:0]) tin[1:0] can be programmed as clocks that cause events in the counter and prescalers. they can also cause captures on the rising edge, falling edge, or both edges. 17.10.2 timer outputs (tout1, tout0) the programmable timer outputs (tout1 and tout0) pulse or toggle on various timer events. 17.11 parallel i/o port (pp[15:0]) this 16-bit bus is dedicated for general-purpose i/o. the parallel port is multiplexed with the a[31:24], tt[1:0], tm[2:0], tip , and dreq [1:0]. these 16 bits are programmed for functionality with the par in the sim. the system designer controls the reset value of this register by driving d4 with a 1 or 0 on the rising edge of rsti (reset input to mcf5307 device). at reset, the system is con gured as pp[15:0] if d4 is 0; otherwise alternate pin functions selected by par = 1 are used. motorola recommends that d4 be driven during reset to a logic level. 17.12 i 2 c module signals the i 2 c module acts as a two-wire, bidirectional serial interface between the mcf5307 and peripherals with an i 2 c interface (such as led controller, a-to-d converter, or d-to-a converter). devices connected to the i 2 c must have open-drain or open-collector outputs. 17.12.1 i 2 c serial clock (scl) the bidirectional, open-drain i 2 c serial clock signal (scl) is the clock signal for i 2 c module operation. the i 2 c module controls this signal when the bus is in master mode; all i 2 c devices drive this signal to synchronize i 2 c timing. 17.12.2 i 2 c serial data (sda) the bidirectional, open-drain i 2 c serial data signal (sda) is the data input/output for the serial i 2 c interface. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-20 mcf5307 users manual debug and test signals 17.13 debug and test signals the signals in this section interface with external i/o to provide processor status signals. 17.13.1 test mode (mtmod[3:0]) the test mode signals choose between multiplexed debug module and jtag signals. if mtmod0 is low, the part is in normal and background debug mode (bdm); if it is high, it is in normal and jtag mode. all other mtmod values are reserved; mtmod[3:1] should be tied to ground and mtmod[3:0] should not be changed while rsti is negated. 17.13.2 high impedance (hiz ) the assertion of hiz forces all output drivers to high-impedance state. the timing on hiz is independent of the clock. note that hiz does not override the jtag operation; tdo/dso can be forced to high impedance by asserting trst . 17.13.3 processor clock output (pstclk) the internal pll generates this output signal, and is the processor clock output that is used as the timing reference for the debug bus timing (ddata[3:0] and pst[3:0]). pstclk is at the same frequency as the core processor and cache memory. the frequency is 2x the clkin. 17.13.4 debug data (ddata[3:0]) the debug data signals (ddata[3:0]) display captured processor data and breakpoint status. see chapter 5, ?debug support,? for additional information on this bus. 17.13.5 processor status (pst[3:0]) the processor status pins indicate the mcf5307 processor status. during debug mode, the timing is synchronous with the processor clock (pstclk) and the status is not related to the current bus transfer. table 2-11 shows the encodings of these signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-21 debug module/jtag signals . 17.14 debug module/jtag signals the mcf5307 complies with the ieee 1149.1a jtag testing standard. jtag test pins are multiplexed with background debug pins. except for tck, these signals are selected by the value of mtmod0. if mtmod0 is high, jtag signals are chosen; if it is low, debug module signals are chosen. mtmod0 should be changed only while rsti is asserted. 17.14.1 test reset/development serial clock (trst /dsclk) if mtmod0 is high, trst is selected. trst asynchronously resets the internal jtag controller to the test logic reset state, causing the jtag instruction register to choose the bypass instruction. when this occurs, jtag logic is benign and does not interfere with normal mcf5307 functionality. although trst is asynchronous, motorola recommends that it makes an asserted-to-negated transition only while tms is held high. trst has an internal pull-up resistor so if it is not driven low, it defaults to a logic level of 1. if trst is not used, it can be tied to ground or, if tck is clocked, to v dd . tying trst to ground places the jtag table 17-17. processor status signal encodings pst[3:0] de?ition hex binary 0x0 0000 continue execution 0x1 0001 begin execution of an instruction 0x2 0010 reserved 0x3 0011 entry into user-mode 0x4 0100 begin execution of pulse and wddata instructions 0x5 0101 begin execution of taken branch or synch_pc 1 1 rev. b enhancement. 0x6 0110 reserved 0x7 0111 begin execution of rte instruction 0x8 1000 begin 1-byte data transfer on ddata 0x9 1001 begin 2-byte data transfer on ddata 0xa 1010 begin 3-byte data transfer on ddata 0xb 1011 begin 4-byte data transfer on ddata 0xc 1100 exception processing 2 2 these encodings are asserted for multiple cycles. 0xd 1101 emulator mode entry exception processing 2 0xe 1110 processor is stopped, waiting for interrupt 2 0xf 1111 processor is halted 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-22 mcf5307 users manual debug module/jtag signals controller in test logic reset state immediately. tying it to v dd causes the jtag controller (if tms is a logic level of 1) to eventually enter test logic reset state after 5 tck clocks. if mtmod0 is low, dsclk is selected. dsclk is the development serial clock for the serial interface to the debug module. the maximum dsclk frequency is 1/5 clkin. see chapter 5, ?debug support.? 17.14.2 test mode select/breakpoint (tms/bkpt ) if mtmod0 is high, tms is selected. the tms input provides information to determine the jtag test operation mode. the state of tms and the internal 16-state jtag controller state machine at the rising edge of tck determine whether the jtag controller holds its current state or advances to the next state. this directly controls whether jtag data or instruction operations occur. tms has an internal pull-up resistor so that if it is not driven low, it defaults to a logic level of 1. but if tms is not used, it should be tied to v dd . if mtmod0 is low, bkpt is selected. bkpt signals a hardware breakpoint to the processor in debug mode. see chapter 5, ?debug support.? 17.14.3 test data input/development serial input (tdi/dsi) if mtmod0 is high, tdi is selected. tdi provides the serial data port for loading the various jtag boundary scan, bypass, and instruction registers. shifting in data depends on the state of the jtag controller state machine and the instruction in the instruction register. shifts occur on the tck rising edge. tdi has an internal pull-up resistor, so when not driven low it defaults to high. but if tdi is not used, it should be tied to v dd . if mtmod0 is low, dsi is selected. dsi provides the single-bit communication for debug module commands. see chapter 5, ?debug support.? 17.14.4 test data output/development serial output (tdo/dso) if mtmod0 is high, tdo is selected. the tdo output provides the serial data port for outputting data from jtag logic. shifting out data depends on the jtag controller state machine and the instruction in the instruction register. data shifting occurs on the falling edge of tck. when tdo is not outputting test data, it is three-stated. tdo can be three-stated to allow bused or parallel connections to other devices having jtag. if mtmod0 is low, dso is selected. dso provides single-bit communication for debug module responses. see chapter 5, ?debug support.? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 17. signal descriptions 17-23 debug module/jtag signals 17.14.5 test clock (tck) tck is the dedicated jtag test logic clock independent of the mcf5307 processor clock. various jtag operations occur on the rising or falling edge of tck. holding tck high or low for an inde nite period does not cause jtag test logic to lose state information. if tck is not used, it must be tied to ground. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17-24 mcf5307 users manual debug module/jtag signals f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-1 chapter 18 bus operation this chapter describes data-transfer operations, error conditions, bus arbitration, and reset operations. it describes transfers initiated by the mcf5307 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. chapter 11, ?synchronous/asynchronous dram controller module,? describes dram cycles. 18.1 features the following list summarizes bus operation features: up to 32 bits of address and data 8-, 16-, and 32-bit port sizes byte, word, longword, and line size transfers bus arbitration for external devices burst and burst-inhibited transfer support internal termination for core and dma bus cycles external termination of bus cycles controlled by an external bus master note that, throughout this manual, an overbar indicates an active-low signal. 18.2 bus and control signals table 18-1 summarizes mcf5307 bus signals described in chapter 17, ?signal descriptions.? table 18-1. coldfire bus signal summary signal name description mcf5307 master external master edge as address strobe o i falling a[31:0] address bus o i rising be /bwe 1 byte enable/byte write enable o o falling cs [7:0] 1 chip selects o o falling d[31:0] data bus i/o i/o rising f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-2 mcf5307 users manual bus characteristics 18.3 bus characteristics the mcf5307 uses an input clock signal (clkin) to generate its internal clock. bclko is the bus clock rate, where all bus operations are synchronous to the rising edge of bclko. some of the bus control signals (be /bwe , oe , cs x , and as ) are synchronous to the falling edge, shown in figure 18-1. bus characteristics may differ somewhat for interfacing with external dram. figure 18-1. signal relationship to bclko for non-dram access irq [7,5,3,1] interrupt request i i rising oe 1 output enable o i falling r/w read/write o i rising siz[1:0] transfer size o i rising t a transfer acknowledge i o rising tip transfer in progress o three-state rising tm[2:0] transfer modi er o three-state rising ts transfer start o i rising tt[1:0] transfer type o three-state rising 1 these signals change after the falling edge. in chapter 20, electrical speci cations, these signals are speci ed off the rising edge because clkin is squared up internally. table 18-1. coldfire bus signal summary (continued) signal name description mcf5307 master external master edge rising-edge signals falling-edge signals inputs t vo t ho t vo t ho t si t hi bclko t vo =propagation delay of signal relative to bclko edge t ho =output hold time relative to bclko edge t si =required input setup time relative to bclko edge t hi =required input hold time relative to bclko edge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-3 data transfer operation 18.4 data transfer operation data transfers between the mcf5307 and other devices involve the following signals: address bus (a[31:0]) data bus (d[31:0]) control signals (ts and t a ) as , cs x , oe , be /bwe attribute signals (r/w , siz, tt, tm, and tip ) the address bus, write data, ts , and all attribute signals change on the rising edge of bclko. read data is latched into the mcf5307 on the rising edge of bclko. as , cs x , oe , and be /bwe change on the falling edge. the mcf5307 bus supports byte, word, and longword operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. transfer parameters such as port size, the number of wait states for the external slave being accessed, and whether internal transfer termination is enabled, can be programmed in the chip-select control registers (cscrs) and dram control registers (dacrs). for aligned transfers larger than the port size, siz[1:0] behaves as follows: if bursting is used, siz[1:0] stays at the size of transfer. if bursting is inhibited, siz[1:0] rst shows the size of the transfer and then shows the port size. table 18-2 shows encoding for siz[1:0]. figure 18-2 shows the byte lanes that external memory should be connected to and the sequential transfers if a longword is transferred for three port sizes. for example, an 8-bit memory should be connected to d[31:24] (be0 ). a longword transfer takes four transfers on d[31:24], starting with the msb and going to the lsb. table 18-2. bus cycle size encoding siz[1:0] port size 00 longword 01 byte 10 word 11 line f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-4 mcf5307 users manual data transfer operation figure 18-2. connections for external memory port sizes the timing relationships between bclkochip select (cs [7:0]), byte enable/byte write enables (be /bwe [3:0]), and output enable (oe ) are similar to their relationships with address strobe (as ) in that all transitions occur during the low phase of bclko. however, as shown in figure 18-3, differences in on-chip signal routing and external loading may prevent signals from asserting simultaneously. figure 18-3. chip-select module output timing diagram 18.4.1 bus cycle execution when a bus cycle is initiated, the mcf5307 rst compares its address with the base address and mask con gurations programmed for chip selects 0?7 (cscr0?cscr7) and for dram blocks 0 and 1 address and control registers (dacr0 and dacr1). if the driven address matches a programmed chip select or dram block, the appropriate chip select is asserted or the dram block is selected using the speci cations programmed in the respective con guration register. otherwise, the following occurs: if the address and attributes do not match in cscr or dacr, the mcf5307 runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. if an address and attribute match in multiple cscrs, the matching chip-select signals are driven; however, the mcf5307 runs an external burst-inhibited bus cycle with external termination on a 32-bit port. if an address and attribute match both dacrs or a dacr and a cscr, the operation is unde ned. processor data bus byte 0 8-bit port 16-bit port 32-bit port byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 d[31:24] d[23:16] d[15:8] d[7:0] external memory memory memory byte enable be0 be1 be2 be3 driven with indeterminate values driven with indeterminate values cs [7:0] bclko be /bwe [3:0] as , oe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-5 data transfer operation table 18-3 shows the type of access as a function of match in the cscrs and dacrs. basic bus operations occur in three clocks, as follows: 1. during the rst clock, the address, attributes, and ts are driven. as is asserted at the falling edge of the clock to indicate that address and attributes are valid and stable. 2. data and t a are sampled during the second clock of a bus-read cycle. during a read, the external device provides data and is sampled at the rising edge at the end of the second bus clock. this data is concurrent with t a , which is also sampled at the rising clock edge. during a write, the mcf5307 drives data from the rising clock edge at the end of the rst clock to the rising clock edge at the end of the bus cycle. wait states can be added between the rst and second clocks by delaying the assertion of t a . t a can be con gured to be generated internally through the dacrs and cscrs. if t a is not generated internally, the system must provide it externally. 3. the last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. figure 18-6 and figure 18-8 show the basic read and write operations. 18.4.2 data transfer cycle states the data transfer operation in the mcf5307 is controlled by an on-chip state machine. each bus clock cycle is divided into two states. even states occur when bclko is high and odd states occur when bclko is low. the state transition diagram for basic and fast-termination read and write cycles is shown in figure 18-4. table 18-3. accesses by matches in cscrs and dacrs number of cscr matches number of dacr matches type of access 0 0 external 10 de ned by cscrs multiple 0 external, burst-inhibited, 32-bit 01 de ned by dacrs 1 1 unde ned multiple 1 unde ned 0 multiple unde ned 1 multiple unde ned multiple multiple unde ned f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-6 mcf5307 users manual data transfer operation figure 18-4. data transfer state transition diagram table 18-4 describes the states as they appear in subsequent timing diagrams. note that the tt[1:0], tm[2:0], and tip functions are chosen in the par, as described in section 15.1.1, ?pin assignment register (par).? table 18-4. bus cycle states state cycle bclko description s0 all high the read or write cycle is initiated. on the rising edge of bclko, the mcf5307 places a valid address on the address bus, asserts tip , and drives r/w high for a read and low for a write, if these signals are not already in the appropriate state. the mcf5307 asserts tt[1:0], tm[2:0], siz[1:0], and ts on the rising edge of bclko. s1 all low as asserts on the falling edge of bclko, indicating that the address and attributes are stable. the appropriate cs x , be /bwe , and oe signals assert on the bclko falling edge. fast termination t a must be asserted during s1. data is made available by the external device and is sampled on the rising edge of bclko with t a asserted. s2 read/write (skipped for fast termination) high ts is negated on the rising edge of bclko. write the data bus is driven out of high impedance as data is placed on the bus on the rising edge of bclko. s3 read/write (skipped for fast termination) low the mcf5307 waits for t a assertion. if t a is not sampled as asserted before the rising edge of bclko at the end of the rst clock cycle, the mcf5307 inserts wait states (full clock cycles) until t a is sampled as asserted. read data is made available by the external device on the falling edge of bclko and is sampled on the rising edge of bclko with t a asserted. s4 all high the external device should negate t a . read (including fast termination) the external device can stop driving data after the rising edge of bclko. however, data could be driven up to s5. s0 s3 s5 s4 s1 s2 basic next cycle wait states read/write fast termination f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-7 data transfer operation note: an external device has at most two bclko cycles after the start of s4 to three-state the data bus after data is sampled in s3. this applies to basic read cycles, fast-termination cycles, and the last transfer of a burst. 18.4.3 read cycle during a read cycle, the mcf5307 receives data from memory or from a peripheral device. figure 18-5 is a read cycle owchart. figure 18-5. read cycle flowchart the read cycle timing diagram is shown in figure 18-6. note: in the following timing diagrams, t a waveforms apply for chip selects programmed to enable either internal or external termination. t a assertion should look the same in either case. s5 s5 low as , cs , be /bwe , and oe are negated on the bclko falling edge. the mcf5307 stops driving address lines and r/w on the rising edge of bclko, terminating the read or write cycle. at the same time, the mcf5307 negates tt[1:0], tm[2:0], tip , and siz[1:0] on the rising edge of bclko. note that the rising edge of bclko may be the start of s0 for the next access cycle; in this case, tip remains asserted and r/w may not transition, depending on the nature of the back-to-back cycles. read the external device stops driving data between s4 and s5. write the data bus returns to high impedance on the rising edge of bclko. the rising edge of bclko may be the start of s0 for the next access. table 18-4. bus cycle states (continued) state cycle bclko description system 1. set r/w to read 2. place address on a[31:0] 3. assert tt[1:0], tm[2:0], tip , and siz[1:0] 4. assert ts 5. assert as 6. negate ts 1. decode address and select the appropriate slave device. 2. drive data on d[31:0] 3. assert ta 1. sample ta low and latch data 1. negate ta . 2. stop driving d[31:0] 1. start next cycle mcf5307 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-8 mcf5307 users manual data transfer operation figure 18-6. basic read bus cycle note the following characteristics of a basic read: in s3, data is made available by the external device on the falling edge of bclko and is sampled on the rising edge of bclko with t a asserted. in s4, the external device can stop driving data after the rising edge of bclko. however, data could be driven up to s5. for a read cycle, the external device stops driving data between s4 and s5. states are described in table 18-4. 18.4.4 write cycle during a write cycle, the mcf5307 sends data to memory or to a peripheral device. the write cycle owchart is shown in figure 18-7. r/w tt[1:0], tm[2:0] tip ts d[31:0] t a read s0 s1 s2 s3 s4 s5 bclko as , cs x be x, oe s iz[1:0], a[31:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-9 data transfer operation figure 18-7. write cycle flowchart the write cycle timing diagram is shown in figure 18-8. figure 18-8. basic write bus cycle table 18-4 describes the six states of a basic write cycle. 18.4.5 fast-termination cycles two clock-cycle transfers are supported on the mcf5307 bus. in most cases, this is impractical to use in a system because the termination must take place in the same half clock during which as is asserted. because this is atypical, it is not referred to as the zero-wait-state case but is called the fast-termination case. a fast-termination cycle is one in which an external device or memory asserts t a as soon as ts is detected. this means that the mcf5307 samples t a on the rising edge of the second cycle of the bus transfer. figure 18-9 shows a read cycle with fast termination. note that fast termination cannot be used with internal termination. 1. sample ta low 1. tree-state d[31:0] 2. start next cycle system 1. set r/w to write 2. place address on a[31:0] 3. assert tt[1:0], tm[2:0], tip , and siz[1:0] 4. assert ts 5. assert as 6. place data on d[31:0] 7. negate ts 1. decode address 2. store data on d[31:0] 3. assert ta 1. negate ta mcf5307 a[31:0], tt[1:0] r/w tip ts d[31:0] t a s0 s1 s2 s3 s4 s5 write bclko as , cs x bwe x tm[2:0], siz[1:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-10 mcf5307 users manual data transfer operation figure 18-9. read cycle with fast termination figure 18-10 shows a write cycle with fast termination. figure 18-10. write cycle with fast termination 18.4.6 back-to-back bus cycles the mcf5307 runs back-to-back bus cycles whenever possible. for example, when a longword read is started on a word-size bus, the processor performs two back-to-back word read accesses. back-to-back accesses are distinguished by the continuous assertion of tip throughout the cycle. figure 18-11 shows a read back-to-back with a write. a[31:0],tt[1:0] r/w tip ts d[31:0] t a s0 s1 s4 s5 read bclko as , cs x be x, oe tm[2:0, siz[1:0]] a[31:0], tt[1:0] r/w tip ts as , cs x d[31:0] t a s0 s1 s4 s5 write bclko bwe x , oe tm[2:0], siz[1:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-11 data transfer operation figure 18-11. back-to-back bus cycles basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type of operations to be placed back to back. the initiation of a back-to-back cycle is not user de nable. 18.4.7 burst cycles the mcf5307 can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to. for example, with bursting enabled, a word transfer to an 8-bit port would take a 2-byte burst cycle for which siz[1:0] = 10 throughout. a line transfer to a 32-bit port would take a 4-longword burst cycle, for which siz[1:0] = 11 throughout. the mcf5307 bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize dma transfers. a user can add wait states by delaying termination of the cycle. the initiation of a burst cycle is encoded on the size pins. for burst transfers to smaller port sizes, siz[1:0] indicates the size of the entire transfer. for example, if the mcf5307 writes a longword to an 8-bit port, siz[1:0] = 00 for the rst byte transfer and does not change. cscrs are used to enable bursting for reads, writes, or both. mcf5307 memory space can be declared burst-inhibited for reads and writes by clearing the appropriate cscr x [bstr,bstw]. a line access to a burst-inhibited region is broken into separate port-width accesses. unlike a burst access, siz[1:0] = 11 only for the rst port-width access; for the remaining accesses, siz[1:0] re ects the port width, with individual accesses separated by as negations. the address changes if internal termination is used but does not change if external termination is used, as shown in figure 18-12 and figure 18-14. a[31:0], tt[1:0] r/w tip ts as , cs x d[31:0] t a read s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 write oe bclko be /bwe x tm[2:0], siz[1:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-12 mcf5307 users manual data transfer operation 18.4.7.1 line transfers a line is a 16-byte-aligned, 16-byte value. despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transfers on multiple address boundaries. table 18-5 shows allowable patterns for line accesses. 18.4.7.2 line read bus cycles figure 18-12 shows line read with zero wait states. the access starts like a basic read bus cycle with the rst data transfer sampled on the rising edge of s4, but the next pipelined burst data is sampled a cycle later on the rising edge of s6. each subsequent pipelined data burst is single cycle until the last one, which can be held for up to 2 bclko cycles after t a is asserted. note that as and cs x are asserted throughout the burst transfer. this example shows the timing for external termination, which differs only from the internal termination example in figure 18-13 in that the address lines change only at the beginning (assertion of ts and tip ) and end (negation of tip ) of the transfer. figure 18-12. line read burst (2-1-1-1), external termination figure 18-13 shows timing when internal termination is used. table 18-5. allowable line access patterns a[3:2] longword accesses 00 0 4 8 c 01 4 8 c 0 10 8 c 0 4 11 c 0 4 8 a[31:0], tt[1:0] r/w tip ts as , cs x d[31:0] t a read read s0 s1 s2 s3 s4 s5 s10 s9 s8 s7 s6 s11 s12 read read bclko be /bwe x , oe tm[2:0], siz[1:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-13 data transfer operation figure 18-13. line read burst (2-1-1-1), internal termination figure 18-14 shows a line access read with one wait state programmed in cscr x to give the peripheral or memory more time to return read data. this gure follows the same execution as a zero-wait state read burst with the exception of an added wait state. . figure 18-14. line read burst (3-2-2-2), external termination figure 18-15 shows a burst-inhibited line read access with fast termination. the external device executes a basic read cycle while determining that a line is being transferred. the external device uses fast termination for subsequent transfers. tt[1:0] r/w tip ts as , cs x d[31:0] t a read read s0 s1 s2 s3 s4 s5 s10 s9 s8 s7 s6 s11 s12 read read bclko be /bwe x , oe tm[2:0], siz[1:0] a[31:0] a[31:0], tt[1:0] r/w tip ts as , cs x d[31:0] t a read s0 s1 s2 s3 s4 s5 s10 s9 s8 s7 s6 s11 s12 s13 ws ws ws ws read read read bclko tm[2:0], siz[1:0] be /bwe x , oe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-14 mcf5307 users manual data transfer operation figure 18-15. line read burst-inhibited, fast, external termination 18.4.7.3 line write bus cycles figure 18-16 shows a line access write with zero wait states. it begins like a basic write bus cycle with data driven one clock after ts . the next pipelined burst data is driven a cycle after the write data is registered (on the rising edge of s6). each subsequent burst takes a single cycle. note that as with the line read example in figure 18-12, as and cs x remain asserted throughout the burst transfer. this example shows the behavior of the address lines for both internal and external termination. note that with external termination, address lines, like siz, tt, and tm, hold the same value for the entire transfer. figure 18-16. line write burst (2-1-1-1), internal/external termination a[31:0] r/w tt[1:0] tip siz[1:0] ts d[31:0] t a line longword basic fast fast fast a[3:2] = 00 a[3:2] = 01 a[3:2] = 10 a[3:2] = 11 s0 s1 s2 s3 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 s7 s6 read read read read bclko tm[2:0] as , cs x be /bwe x , oe a[31:0] siz[1:0] ts as , cs x d[31:0] t a write write write write s0 s1 s2 s3 s4 s5 s10 s9 s8 s7 s6 s11 tm[1:0], tt[1:0] bclko oe , be /bwe a[31:0] internal termination external termination r/w , tip f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-15 data transfer operation figure 18-17 shows a line burst write with one wait-state insertion. figure 18-17. line write burst (3-2-2-2) with one wait state, internal termination figure 18-18 shows a burst-inhibited line write. the external device executes a basic write cycle while determining that a line is being transferred. the external device uses fast termination to end each subsequent transfer. figure 18-18. line write burst-inhibited, internal termination 18.4.7.4 transfers using mixed port sizes figure 18-19 shows timing for a longword read from an 8-bit port using external termination. figure 18-20 shows the same transfer with internal termination. for both, siz[1:0] change only at the start of a new transfer because this burst is implemented as one a[31:0] r/w , tip tm[2:0], tt[1:0] ts as , cs x d[31:0] t a write write write write s0 s1 s2 s3 s4 s5 s10 s9 s8 s7 s6 s11 ws ws ws ws bclko siz[1:0] oe , bwe a[31:0] r/w , tip tt[1:0] siz[1:0] ts d[31:0] t a line longword basic fast fast fast a[3:2] = 00 a[3:2] = 01 a[3:2] = 10 a[3:2] = 11 write write write write s0 s1 s2 s3 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 bclko tm[2:0] as , cs x o e , bwe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-16 mcf5307 users manual misaligned operands transfer. figure 18-19. longword read from an 8-bit port, external termination note that with external termination, address signals do not change. with internal termination, figure 18-20, a[1:0] increment for the same longword transfer. figure 18-20. longword read from an 8-bit port, internal termination 18.5 misaligned operands because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned. a byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a longword is misaligned at an address not a multiple of four. although the mcf5307 enforces no alignment restrictions for data operands (including program counter (pc) relative data addressing), additional bus cycles are required for misaligned operands. a[31:0], tt[1:0] r/w tip ts as , csx d[31:0] t a read read s0 s1 s2 s3 s4 s5 s10 s9 s8 s7 s6 s11 s12 read read bclko be /bwe x , oe tm[2:0], siz[1:0] a[31:2], tt[1:0] r/w tip ts as , csx d[31:0] t a read read read read be /bwe x , oe tm[2:0], siz[1:0] a[1:0] s0 s1 s2 s3 s4 s5 s10 s9 s8 s7 s6 s11 s12 bclko f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-17 bus errors instruction words and extension words (opcodes) must reside on word boundaries. attempting to prefetch a misaligned instruction word causes an address error exception. the mcf5307 converts misaligned, cache-inhibited operand accesses to multiple aligned accesses. figure 18-21 shows the transfer of a longword operand from a byte address to a 32-bit port. in this example, siz[1:0] specify a byte transfer and a byte offset of 0x1. the slave device supplies the byte and acknowledges the data transfer. when the mcf5307 starts the second cycle, siz[1:0] specify a word transfer with a byte offset of 0x2. the next two bytes are transferred in this cycle. in the third cycle, byte 3 is transferred. the byte offset is now 0x0, the port supplies the nal byte, and the operation is complete. figure 18-21. example of a misaligned longword transfer (32-bit port) if an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the cache. the example in figure 18-22 differs from the one in figure 18-21 in that the operand is word-sized and the transfer takes only two bus cycles. figure 18-22. example of a misaligned word transfer (32-bit port) note: external masters using internal mcf5307 chip selects and default memory control signals must initiate aligned transfers. 18.6 bus errors the mcf5307 has no bus monitor. if the auto-acknowledge feature is not enabled for the address that generates the error, the bus cycle can be terminated by asserting t a or by using the software watchdog timer. if it is required that the mcf5307 handle a bus error differently, an interrupt handler can be invoked by asserting an interrupt to the core along with t a when the bus error occurs. 18.7 interrupt exceptions a peripheral device uses the interrupt-request signals (irq x ) to signal the core to take an interrupt exception when it needs the mcf5307 or is ready to send information to it. the interrupt transfers control to an appropriate routine. transfer 1 transfer 2 transfer 3 byte 3 byte 0 byte 1 byte 2 31 24 23 16 15 8 7 0 001 010 100 a[2:0] transfer 1 transfer 2 byte 0 byte 0 31 24 23 16 15 8 7 0 001 100 a[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-18 mcf5307 users manual interrupt exceptions the mcf5307 has the following two levels of interrupt masking: interrupt mask registers in the sim compare interrupt inputs with programmable interrupt mask levels. the sim outputs only unmasked interrupts. the status register uses a 3-bit interrupt priority mask. the core recognizes only interrupt requests of higher priority than the value in the mask. see section 2.2.2.1, ?status register (sr).? note: to mask a level 1?6 interrupt source, write a higher-level sr interrupt mask before setting imr. then restore the mask to its previous value. do not mask a level 7 interrupt source. the mcf5307 continuously samples and synchronizes external interrupt inputs. an interrupt request must be held for at least two consecutive bclko periods to be considered valid. to guarantee that the interrupt is recognized, the request level must be maintained until the mcf5307 acknowledges the interrupt with an interrupt-acknowledge cycle. note: interrupt levels 1?7 are level-sensitive. level 7 is also edge-triggered. see section 18.7.1, ?level 7 interrupts.? the mcf5307 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any higher-priority pending exception. thus, the mcf5307 executes at least one instruction in an interrupt exception handler before recognizing another interrupt request. if autovector generation is used for internal interrupts (icr n [avec] = 1), the interrupt acknowledge vector is generated internally and no interrupt acknowledge cycle is generated on the external bus. if autovector generation is used for external interrupts, no interrupt acknowledge cycle is shown on the external bus (as is not asserted) unless avr[blk] is 0. consequently, the external interrupt must be cleared in the interrupt service routine. see section 9.2.2, ?autovector register (avr).? 18.7.1 level 7 interrupts level 7 interrupts are nonmaskable and are handled differently than other interrupts. level 7 interrupts are edge triggered by a transition from a lower priority request to the level 7 request. interrupts at all other levels are level sensitive. therefore, if irq7 remains asserted, the mcf5307 recognizes only one level 7 interrupt because only one transition from a lower level request to a level 7evel 7 request occurred. for the processor to recognize two consecutive level 7 interrupts, one of the following must occur: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-19 interrupt exceptions the interrupt request on the interrupt control pins is raised to level 7 and stays there until an interrupt-acknowledge cycle begins. the level later drops but then returns to level 7, causing a second transition on the interrupt control lines. the interrupt request on the interrupt control pins is raised to level 7 and stays there. if the level 7 interrupt routine lowers the mask level, a second level 7 interrupt is recognized without a transition of the interrupt control pins. after the level 7 routine completes, the mcf5307 compares the mask level to the request level on the irq x signals. because the mask level is lower than the requested level, the interrupt mask is set back to level 7. to ensure it is recognized, the level 7 request on irq7 must be held until the second interrupt-acknowledge bus cycle begins. 18.7.2 interrupt-acknowledge cycle when the mcf5307 processes an interrupt exception, it performs an interrupt- acknowledge bus cycle to obtain the vector number that contains the starting location of the interrupt exception handler. the interrupt-acknowledge bus cycle is a read transfer that differs from normal read cycles in the following respects: tt[1:0] = 0x3 to indicate a cpu space or acknowledge bus cycle. tm[2:0] = the level of interrupt being acknowledged. a[31:5] = 0x7f_ffff. a[4:2] = the interrupt request level being acknowledged (same as tm[2:0]). a[1:0] = 00. during the interrupt-acknowledge bus cycle (a read cycle), the responding device places the vector number on d[31:24] and the cycle is terminated normally with t a . figure 18-23 is a ow diagram for an interrupt-acknowledge cycle terminated with t a . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-20 mcf5307 users manual bus arbitration figure 18-23. interrupt-acknowledge cycle flowchart 18.8 bus arbitration the mcf5307 bus protocol gives either the mcf5307 or an external device access to the external bus. if more than one external device uses the bus, an external arbiter can prioritize requests and determine which device is bus master. when the mcf5307 is bus master, it uses the bus to fetch instructions and transfer data to and from external memory. when an external device is bus master, the mcf5307 can monitor the external master?s transfers and interact through its chip-select, dram control, and transfer termination signals. see section 10.4.1.3, ?chip-select control registers (cscr0?cscr7),? and chapter 11, ?synchronous/asynchronous dram controller module.? two-wire bus arbitration is used where the mcf5307 shares the bus with a single external device. this mode uses bg and bd . the external device can ignore br . three-wire mode is used where the mcf5307 shares the bus with multiple external devices. this requires an external bus arbiter and uses bg , bd , and br . in either mode, the mcf5307 bus arbiter operates synchronously and transitions between states on the rising edge of bclko. table 18-6 shows the four arbitration states the mcf5307 can be in during bus operation. table 18-6. mcf5307 arbitration protocol states state master bus bd description reset none not driven negated the mcf5307 enters reset state from any other state when rsti or software watchdog reset is asserted. if both are negated, the mcf5307 enters implicit or external device mastership state, depending on bg . implicit master mcf5307 not driven negated the mcf5307 is bus master (bg input is asserted) but is not ready to begin a bus cycle. it continues to three-state the bus until an internal bus request. system 1. decode address and select the appropriate slave device. 2. drive data on d[31:24] 3. assert ta for one bclko cycle 1. read and store data (d[31:24]) 2. recognize the transfer is done 1. negate ts 2. drive tm[2:0] to indicate interrupt acknowledge (tm[2:0] = interrupt level) 1. drive 0x7fffff on a[31:5] 2. drive 0x0 on a[1:0] 3. drive interrupt level on a[4:2] 4. drive r/w to read (r/w = 1) 5. drive siz[1:0] to indicate byte (siz[1:0] = 01) 6. drive tt[1:0] and tm[2:0] to indicate interrupt acknowledge (tt[1:0] = 11; tm[2:0] = interrupt level) 7. assert ts for one bclko cycle mcf5307 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-21 general operation of external master transfers if the mcf5307 is the only possible master, bg can be tied to gnd?no arbiter is needed. 18.8.1 bus arbitration signals bus arbitration signal timings in table 18-7 are referenced to the system clock, which is not considered a bus signal. clock routing is expected to meet application requirements. 18.9 general operation of external master transfers an external master asserts its hold signal (such as holdreq) when it executes a bus cycle, driving bg high and forcing the mcf5307 to hold all bus requests. during an external master cycle, the mcf5307 can provide memory control signals (oe , cs [7:0], be /bwe [3:0], ras [1:0], cas [3:0]) and t a while the external master drives the address and data bus and other required bus control signals. when the external master asserts ts or as to the mcf5307, the beginning of a bus cycle is identi ed and the mcf5307 starts decoding the address driven. explicit master mcf5307 driven asserted the mcf5307 is explicit bus master when bg is asserted and at least one bus cycle has been initiated. it asserts bd and retains explicit mastership until bg is negated even if no active bus cycles are executed. it releases the bus at the end of the current bus cycle, then negates bd and three-states the bus signals. external master external not driven negated an external device is bus master (bg negated to mcf5307). the mcf5307 can assert oe , cs [7:0], be /bwe [3:0], t a, and all dram controller signals (ras [1:0], cas [3:0], sras , scas , dramw , scke). table 18-7. coldfire bus arbitration signal summary signal i/o description br o bus request. indicates to an external arbiter that the processor needs to become bus master. br is negated when the mcf5307 begins an access to the external bus with no other internal accesses pending. br remains negated until another internal request occurs. bg i bus grant. an external arbiter asserts bg to indicate that the mcf5307 can control the bus at the next rising edge of bclko. when the arbiter negates bg , the mcf5307 must release the bus as soon as the current transfer completes. the external arbiter must not grant the bus to any other device until both bd and bg are negated. bd o bus driven. the mcf5307 asserts bd to indicate it is current master and is driving the bus. if it loses bus mastership during a transfer, it completes the last transfer of the current access, negates bd , and three-states all bus signals on the rising edge of bclko. if it loses mastership during an idle clock cycle, it three-states all bus signals on the rising edge of bclko. table 18-6. mcf5307 arbitration protocol states (continued) state master bus bd description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-22 mcf5307 users manual general operation of external master transfers note the following regarding external master accesses: for the mcf5307 to assert a cs x during external master accesses, csmr n [am] must be set. external master hits use the corresponding cscr n settings for auto-acknowledge, byte enables, and wait states. see section 10.4.1.3, ?chip-select control registers (cscr0?cscr7).? to enable dram control signals during external master accesses, dcmr n [am] must be set. during external master bus cycles, either ts or as (but not both) should be driven to the mcf5307. driving both during a bus cycle causes indeterminate results. external master transfers that use the mcf5307 to drive memory control signals and t a are like normal mcf5307 transfers. figure 18-24 shows timing for basic back-to-back bus cycles during an external master transfer. figure 18-24. basic no-wait-state external master access r/w is asserted high for reads and low for writes; otherwise, the transfers are the same. in figure 18-24, the mcf5307 chip select?s internal transfer acknowledge is enabled and the mcf5307 drives t a as an output after a programmed number of wait states. r/w a[31:0], tt[1:0] tip ts as d[31:0] t a 1 bg , bd 2 external master c1 c2 c4 c5 c6 c7 c3 c8 c9 cs 1 be /bwe 1 1 depending on programming, these signals may or may not be driven by the processor. c10 c11 br 2 2 this signal is driven by the processor for an external master transfer. bclko holdreq s iz[1:0], tm[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-23 general operation of external master transfers note: bus timing diagrams for external master transfers are not valid for on-chip internal four-channel dma accesses on the mcf5307. timing diagrams describe transactions in general terms of bus cycles (c n ) rather than the states (s n ) used in the bus diagrams. table 18-8 de nes the cycles for figure 18-24. figure 18-25 shows a burst line access for an external master transfer with the chip select set to no-wait states and with internal transfer-acknowledge assertion enabled. table 18-8. cycles for basic no-wait-state external master access cycle de?ition c1 the external master asserts holdreq, signaling the mcf5307 to hold bus requests. bd should not be asserted. the external master drives address, ts , r/w , tt[1:0], tm[2:0], tip , and siz[1:0] as mcf5307 inputs. c2 c3 the mcf5307 decodes the external master s address and control signals to identify the proper chip select and byte enable assertion. the external master negates ts in c2. c4 on the falling edge of bclko, the mcf5307 asserts the appropriate chip select for the external master access along with the appropriate byte enables. c5 on the rising edge of bclko, data is driven onto the bus by the device selected by cs . on the rising edge, the mcf5307 asserts t a to indicate the cycle is complete. c6 t a negates on the rising edge of bclko. on the falling edge, the mcf5307 negates the chip select and byte enables and the next cycle can begin. c7 the external master negates tip on the rising edge of bclko. c8 the external device retains bus mastership and drives the address bus, ts , r/w , tt[1:0], tm[2:0], tip , and siz[1:0] as inputs to the mcf5307. c9 the mcf5307 decodes the external master s address and control signals to identify the proper chip select and byte enable assertion. the external master negates ts . the mcf5307 asserts br on the rising edge of bclko, signalling that it wants to arbitrate for the bus when the current cycle completes. c10 the mcf5307 continues to decode the external device s address and control signals to identify the proper chip select and byte enable assertion. c11 on the falling edge of bclko, the mcf5307 asserts the appropriate chip select for the external master access along with the appropriate byte enables. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-24 mcf5307 users manual general operation of external master transfers figure 18-25. external master burst line access to 32-bit port table 18-9 de nes the cycles for figure 18-25. table 18-9. cycles for external master burst line access to 32-bit port cycle de?ition c1 the external device is bus master and asserts holdreq, indicating to the mcf5307 to hold all bus requests. in other words, bd should not be asserted. the external master drives address, ts , r/w , tt[1:0], tm[2:0], tip , and siz[1:0] as inputs to the mcf5307. siz[1:0] inputs indicate a line transfer. the mcf5307 is not asserting br . c2 c3 the mcf5307 decodes the external device s address and control signals to identify the proper chip-select and byte-enable assertion. the external device negates ts in c2. address and r/w are latched in the mcf5307 on the rising edge of bclko in c2. after c2, the address and r/w are ignored for the rest of the burst transfer. c4 on the falling edge of bclko, the mcf5307 asserts the appropriate chip select for the external device access along with the appropriate byte enables. c5 on the rising edge of bclko, data is driven onto the bus by the device selected by cs . the mcf5307 asserts t a on the rising edge of bclko, indicating the rst data transfer is complete. a[31:0] r/w tt[1:0], tm[2:0] tip ts as , br 2 d[31:0] t a 1 bg , bd 2 external master c1 c2 c4 c5 c6 c7 c3 c8 c9 cs 1 be /bwe 1 1 depending on programming, these signals may or may not be driven by the processor. c10 c11 2 these signals are driven by the processor for an external master transfer. bclko siz[1:0] holdreq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-25 general operation of external master transfers 18.9.1 two-device bus arbitration protocol (two-wire mode) two-wire mode bus arbitration lets the mcf5307 share the external bus with a single external bus device without requiring an external bus arbiter. figure 18-26 shows the mcf5307 connecting to an external device using the two-wire mode. the mcf5307 bg input is connected to the holdreq output of the external device; the mcf5307 bd output is connected to the holdack input of the external device. because the external device controls the state of holdreq, it controls when the mcf5307 is granted the bus, giving the mcf5307 lower priority. figure 18-26. mcf5307 two-wire mode bus arbitration interface when the external device is not using the bus, it negates holdreq, driving bg low and granting the bus to the mcf5307. when the mcf5307 has an internal bus request pending and bg is low, the mcf5307 drives bd low, negating holdack to the external device. when the external bus device needs the external bus, it asserts holdreq, driving bg high, requesting the mcf5307 to release the bus. if bg is negated while a bus cycle is in progress, the mcf5307 releases the bus at the completion of the bus cycle. note that the mcf5307 considers the individual transfers of a burst or burst-inhibited access to be a single bus cycle and does not release the bus until the last transfer of the series completes. when the bus has been granted to the mcf5307, one of two situations can occur. in the rst case, if the mcf5307 has an internal bus request pending, the mcf5307 asserts bd to indicate explicit bus mastership and begins the pending bus cycle by asserting ts . as c6 c8 no-wait state data transfers 2 4 occur on the rising edges of bclko. t a continues to be asserted indicating completion of each transfer. tip , cs x , and be /bwe [3:0] are driven. c9 t a negates on the rising edge of bclko along with external device s negation of tip . on the falling edge, the mcf5307 negates chip select and byte enables, creating an opportunity for another cycle to begin. table 18-9. cycles for external master burst line access to 32-bit port (continued) cycle de?ition bg bd br holdreq holdack external bus master a[31:0] r/w siz[1:0] d[31:0] ts ta a[31:0] r/w siz[1:0] d[31:0] ts ta to/from external memory and control mcf5307 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-26 mcf5307 users manual general operation of external master transfers shown in figure 18-25, the mcf5307 continues to assert bd until the completion of the bus cycle. if bg is negated by the end of the bus cycle, the mcf5307 negates bd . while bg is asserted, bd remains asserted to indicate the mcf5307 is master, and it continuously drives the address bus, attributes, and control signals. s figure 18-27. two-wire bus arbitration with bus request asserted in the second situation, the bus is granted to the mcf5307, but it does not have an internal bus request pending, so it takes implicit bus mastership. the mcf5307 does not drive the bus and does not assert bd if the bus has an implicit master. if an internal bus request is generated, the mcf5307 assumes explicit bus mastership. if explicit mastership was assumed because an internal request was generated, the mcf5307 immediately begins an access and asserts bd . in figure 18-28, the external device is bus master during c1 and c2. during c3 the external device releases control of the bus by asserting bg to the mcf5307. at this point, there is an internal access pending so the mcf5307 asserts bd during c4 and begins the access. thus, the mcf5307 becomes the explicit external bus master. also during c4, the external device removes the grant from the mcf5307 by negating bg . as the current bus master, the mcf5307 continues to assert bd until the current transfer completes. because bg is negated, the mcf5307 negates bd during c9 and three-states the external bus, thereby returning external bus mastership to the external device. a[31:0], tt[1:0] r/w tip ts as d[31:0] t a bg bd external master c1 c2 c4 c5 c6 c7 c3 c8 c9 mcf5307 bclko siz[1:0], tm[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-27 general operation of external master transfers figure 18-28. two-wire implicit and explicit bus mastership in figure 18-28, the external device is master during c1 and c2. it releases bus control in c3 by asserting bg to the mcf5307. during c4 and c5, the mcf5307 is implicit master because no internal access is pending. in c5, an internal bus request becomes pending, causing the mcf5307 to become explicit bus master in c6 by asserting bd . in c7, the external device removes the bus grant to the mcf5307. the mcf5307 does not release the bus (the mcf5307 continues to assert bd ) until the transfer ends. note: the mcf5307 can start a transfer in the clock cycle after bg is asserted. the external master must not assert bg to the mcf5307 while driving the bus or the part may be damaged. chapter 5, ?debug support is a mcf5307 bus arbitration state diagram. states are described in table 18-6. r/w tip ts as d[31:0] t a bg bd external master explicit mastership implicit mastership c1 c2 c4 c5 c6 c7 c3 c8 c9 mcf5307 bclko a[31:0], tt[1:0] siz[1:0], tm[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-28 mcf5307 users manual general operation of external master transfers figure 18-29. mcf5307 two-wire bus arbitration protocol state diagram table 18-10 describes the two-wire bus arbitration protocol transition conditions. table 18-10. mcf5307 two-wire bus arbitration protocol transition conditions present state condition label rsti software watchdog reset bg bus request transfer in progress end of cycle 1 next state reset a1 a 2 reset a2 n 3 a reset a3nnn em 4 a4 n n a implicit mas implicit master b1nnnem b2 n n a explicit mas b3 n n a n implicit mas b4 n n a a explicit mas explicit master c1 n n a explicit mas c2 n n n explicit mas c3nnnnem c4 n n n a n explicit mas c5 n n n a a em external master d1 n n n em mas d2 n n a explicit mas d3 n n a n implicit mas d4 n n a a explicit mas reset implicit master explicit master external a1 a2 a3 a4 c3 c1 c2 c5 c4 b2 b1 b4 d2 d4 d3 b3 d1 master f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-29 general operation of external master transfers 18.9.2 multiple external bus device arbitration protocol (three-wire mode) three-wire mode lets the mcf5307 share the external bus with multiple external devices. this mode requires an external arbiter to assign priorities to each potential master and to determine which device accesses the external bus. the arbiter uses the mcf5307 bus arbitration signals, br , bd , and bg , to control use of the external bus by the mcf5307. the mcf5307 requests the bus from the external bus arbiter by asserting br when the core requests an access. it continues to assert br until after the transfer starts. it can negate br at any time regardless of the bg status. if the mcf5307 is granted the bus when an internal bus request is generated, it asserts bd and the access begins immediately. the mcf5307 always drives br and bd , which cannot be directly wire-ored with other devices. the external arbiter asserts bg to grant the bus to mcf5307, which can begin a bus cycle after the next rising edge of bclko. if bg is negated during a bus cycle, the mcf5307 releases the bus when the cycle completes. to guarantee that the bus is released, bg must be negated before the rising edge of the bclko in which the last t a is asserted. note that the mcf5307 treats any series of burst or a burst-inhibited transfers as a single bus cycle and does not release the bus until the last transfer of the series completes. when the mcf5307 is granted the bus after it asserts br , one of two things can occur. if the mcf5307 has an internal bus request pending, it asserts bd , indicating explicit bus mastership, and begins the pending bus cycle by asserting ts . the mcf5307 continues to assert bd until the external bus arbiter negates bg , after which bd is negated at the completion of the bus cycle. as long as bg is asserted, bd remains asserted to indicate that the mcf5307 is bus master, and the mcf5307 continuously drives the address bus, attributes, and control signals. if no internal request is pending, the mcf5307 takes implicit bus mastership. it does not drive the bus and does not assert bd if the bus has an implicit master. if an internal bus request is generated, the mcf5307 assumes explicit bus mastership and immediately begins an access and asserts bd . figure 18-30 shows implicit and explicit bus mastership due to generation of an internal bus request. 1 both normal terminations and terminations due to bus errors generate an end of cycle. bus cycles resulting from a burst-inhibited transfer are considered part of that original transfer. 2 a means asserted. 3 n means negated. 4 em means external master. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-30 mcf5307 users manual general operation of external master transfers figure 18-30. three-wire implicit and explicit bus mastership in figure 18-30, the external device is bus master during c1 and c2, releasing control in c3, at which time the external arbiter asserts bg to the mcf5307. during c4 and c5, the mcf5307 is implicit master because no internal access is pending. in c5, an internal bus request becomes pending, causing the mcf5307 to take explicit bus mastership in c6 by asserting br and bd . in c7, the external device removes the bus grant to the mcf5307. the mcf5307 does not release the bus (the mcf5307 asserts bd ) until the transfer ends. note: the mcf5307 can start a transfer in the cycle after bg is asserted. the external arbiter should not assert bg to the mcf5307 until the previous external master stops driving the bus. asserting bg during another external master?s transfer may damage the part. r/w tip ts as d[31:0] t a bg bd external master explicit mastership implicit mastership c1 c2 c4 c5 c6 c7 c3 c8 c9 br mcf5307 bclko a[31:0], tt[1:0] siz[1:0], tm[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-31 general operation of external master transfers figure 18-31. three-wire bus arbitration in figure 18-31, the external device is bus master during c1 and c2. during c2, the mcf5307 requests the external bus because of a pending internal transfer. on c3, the external releases mastership and the external arbiter grants the bus to the mcf5307 by asserting bg . at this point, an internal is access pending so the mcf5307 asserts bd during c4 and begins the access. thus, the mcf5307 becomes the explicit bus master. also during c4, the external arbiter removes the grant from the mcf5307 by negating bg . because the mcf5307 is bus master, it continues to assert bd until the current transfer completes. because bg is negated, the mcf5307 negates bd during c9 and three-states the external bus, thereby passing mastership to an external device. the mcf5307 can assert br to signal the external arbiter that it needs the bus. however, there is no guarantee that when the bus is granted to the mcf5307 that a bus cycle will be performed. at best, br must be used as a status output that indicates when the mcf5307 needs the bus, but not as an indication that the mcf5307 is in a certain bus arbitration state. figure 18-32 is a high-level state diagram for mcf5307 bus arbitration protocol. table 18-6 describes the four states shown in figure 18-32. r/w tip ts as d[31:0] t a bg bd external master c1 c2 c4 c5 c6 c7 c3 c8 c9 br mcf5307 bclko a[31:0], tt[1:0] siz[1:0], tm[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-32 mcf5307 users manual general operation of external master transfers figure 18-32. three-wire bus arbitration protocol state diagram table 18-11 lists conditions that cause state transitions. table 18-11. three-wire bus arbitration protocol transition conditions current state condition label rsti software watchdog reset bg bus request transfer in progress end of cycle 1 next state reset a1 asserted reset a2 negated asserted reset a3 negated negated negated em a4 negated negated asserted implicit master implicit master b1 negated negated negated external device master b2 negated negated asserted explicit master b3 negated negated asserted negated implicit master b4 negated negated asserted asserted explicit master reset implicit master explicit master external a1 a2 a3 a4 c3 c1 c2 c5 c4 b2 b1 b4 d2 d4 d3 b3 d1 master f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-33 reset operation the bus arbitration state diagram can be used for the mcf5307 three-wire bus arbitration protocol to approximate the high-level behavior of the mcf5307. it is assumed that all ts or as signals in a system are tied together and each bus device?s bd and br signals are connected individually to the external arbiter. the external arbiter must ensure that any external masters will have released the bus after the next rising edge of before asserting bg to the mcf5307. the mcf5307 does not monitor external bus master operation regarding bus arbitration. note: the mcf5307 can start a transfer on the rising edge of the cycle after bg is asserted. the external arbiter should not assert bg to the mcf5307 until the previous external master stops driving the bus or the part may be damaged. 18.10 reset operation the mcf5307 supports two types of reset. asserting rsti resets the entire mcf5307. a software watchdog reset resets everything but the internal pll module. explicit master c1 negated negated asserted explicit master c2 negated negated negated explicit master c3 negated negated negated negated external device master c4 negated negated negated yes negated explicit master c5 negated negated negated yes yes external device master external master d1 negated negated negated 1 external device master d2 negated negated asserted explicit master d3 negated negated asserted negated implicit master d4 negated negated asserted asserted explicit master 1 both normal terminations and terminations due to bus errors generate an end of cycle. bus cycles resulting from a burst-inhibited transfer are considered part of that original transfer. table 18-11. three-wire bus arbitration protocol transition conditions (continued) current state condition label rsti software watchdog reset bg bus request transfer in progress end of cycle 1 next state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-34 mcf5307 users manual reset operation 18.10.1 master reset to perform a master reset, an external device asserts rsti . when power is applied to the system, external circuitry should assert rsti for a minimum of 80 clkin cycles after vcc is within tolerance. figure 18-33 is a functional timing diagram of the master reset operation, showing relationships among vcc, rsti , mode selects, and bus signals. clkin must be stable by the time vcc reaches the minimum operating speci cation. clkin should start oscillating as vcc is ramped up to clear out contention internal to the mcf5307 caused by the random states of internal ip- ops on power up. rsti is internally synchronized for two clkin cycles before being used and must meet the speci ed setup and hold times in relationship to clkin to be recognized. figure 18-33. master reset timing during the master reset period, all signals capable of being three-stated are driven to a high-impedance; all others are negated. when rsti negates, all bus signals remain in a high-impedance state until the mcf5307 is granted the bus and the core begins the rst bus cycle for reset exception processing. a master reset causes any bus cycle (including dram refresh cycle) to terminate and initializes registers appropriately for a reset exception. note that during reset d[7:0] are sampled on the negating edge of rsti for initial mcf5307 con gurations listed in table 18-12. rsti d[7:0] bus signals bd br rst o 100k clkin cycles pll lock time >80 clkin cycles vcc clkin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 18. bus operation 18-35 reset operation see section 17.5.5, ?data/con guration pins (d[7:0]).? motorola recommends that the data pins be driven rather than using a weak pull-up or pull-down resistor. table 17-1 lists the encoding of these pins sampled at reset. 18.10.2 software watchdog reset a software watchdog reset is performed if the executing software does not provide the correct write data sequence with the enable-control bit set. this reset helps prevent runaway software or unterminated bus cycles. figure 18-34 is a functional timing diagram of the software watchdog reset operation, showing rst o and bus signal relationships. table 18-12. data pin configuration pin function d7 auto-acknowledge con guration (aa_config) d[6:5] port size con guration (ps_config[1:0]) d4 address con guration (addr_config/d4) d[3:2] frequency of clkin (freq[1:0]) d[1:0] ratio of bclko/processor clock {divide[1:0]) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18-36 mcf5307 users manual reset operation figure 18-34. software watchdog reset timing during the software watchdog reset period, all signals that can be are driven to a high-impedance state; all those that cannot be are negated. when rst o negates, bus signals remain in a high-impedance state until the mcf5307 is granted the bus and the coldfire core begins the rst bus cycle for reset exception processing. 100k clkin d[7:0] latched >80 clkin bclko clkin rsti bclko bclko pstclk rsto 30 bclko 20 bclko 15 bclko (1/2 mode) (1/3 mode) (1/4 mode) d[7:0] cycle lock time f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 19. ieee 1149.1 test access port (jtag) 19-1 chapter 19 ieee 1149.1 test access port (jtag) this chapter describes con guration and operation of the mcf5307 jtag test implementation. it describes the use of jtag instructions and provides information on how to disable jtag functionality. 19.1 overview the mcf5307 dedicated user-accessible test logic is fully compliant with the publication standard test access port and boundary-scan architecture, ieee standard 1149.1. use the following description in conjunction with the supporting ieee document listed above. this section includes the description of those chip-speci c items that the ieee standard requires as well as those items speci c to the mcf5307 implementation. the mcf5307 jtag test architecture supports circuit board test strategies based on the ieee standard. this architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (tap) and the jtag reset pin, trst . test logic design is static and is independent of the system logic except where the jtag is subordinate to other complimentary test modes, as described in chapter 5, ?debug support.? when in subordinate mode, jtag test logic is placed in reset and the tap pins can be used for other purposes, as described in table 19-1. the mcf5307 jtag implementation can do the following: perform boundary-scan operations to test circuit board electrical continuity bypass the mcf5307 by reducing the shift register path to a single cell set mcf5307 output drive pins to xed logic values while reducing the shift register path to a single cell sample mcf5307 system pins during operation and transparently shift out the result protect mcf5307 system output and input pins from backdriving and random toggling (such as during in-circuit testing) by placing all system pins in high- impedance state note: ieee standard 1149.1 may interfere with system designs that do not incorporate jtag capability. section 19.6, ?disabling ieee standard 1149.1 operation,? describes precautions for ensuring that this logic does not affect system or debug operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
19-2 mcf5307 users manual jtag signal descriptions figure 19-1 is a block diagram of the mcf5307 implementation of the 1149.1 ieee standard. the test logic includes several test data registers, an instruction register, instruction register control decode, and a 16-state dedicated tap controller. figure 19-1. jtag test logic block diagram 19.2 jtag signal descriptions jtag operation on the mcf5307 is enabled when mtmod0 is high (logic 1), as described in table 19-1. otherwise, jtag tap signals, tck, tms, tdi, tdo, and trst , are interpreted as the debug port pins. mtmod0 should not be changed while rsti is asserted. table 19-1. jtag pin descriptions pin description tck test clock. the dedicated jtag test logic clock is independent of the mcf5307 processor clock. various jtag operations occur on the rising or falling edge of tck. internal jtag controller logic is designed such that holding tck high or low inde nitely does cause the jtag test logic to lose state information. if tck is not used, it should be tied to ground. tms/ bkpt test mode select (mtmod0 high)/breakpoint (mtmod0 low). tms provides the jtag controller with information to determine the test operation mode. the states of tms and of the internal 16-state jtag controller state machine at the rising edge of tck determine whether the jtag controller holds its current state or advances to the next state. this directly controls whether jtag data or instruction operations occur. tms has an internal pull-up, so if it is not driven low, its value defaults to a logic level of 1. if tms is not used, it should be tied to vdd. bkpt signals a hardware breakpoint to the processor in debug mode. see chapter 5, debug support. test data registers tdi tms trst tdo v+ v+ v+ boundary scan register id code bypass 3-bit instruction register 3-bit instruction decode m u x ta p m u x tck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 19. ieee 1149.1 test access port (jtag) 19-3 tap controller 19.3 tap controller the state of tms at the rising edge of tck determines the current state of the tap controller. the tap controller can follow two basic two paths, one for executing jtag instructions and the other for manipulating jtag data based on jtag instructions. the various states of the tap controller are shown in figure 19-2. for more detail on each state, see the ieee standard 1149.1 jtag document. note that regardless of the tap controller state, test-logic-reset can be entered if tms is held high for at least ve rising edges of tck. figure 19-2 shows the jtag tap controller state machine. tdi/dsi test data input (mtmod0 high)/development serial input (mtmod0 low). tdi provides the serial data port for loading the jtag boundary-scan, bypass, and instruction registers. shifting in of data depends on the state of the jtag controller state machine and the instruction in the instruction register. this shift occurs on the rising edge of tck. tdi has an internal pull-up so if it is not driven low its value defaults to a logical 1. if tdi is not used, it should be tied to vdd. dsi provides single-bit communication for debug module commands. see chapter 5, debug support. tdo/ dso test data output (mtmod0 high)/development serial output (mtmod0 low). tdo is the serial data port for outputting data from jtag logic. shifting data out depends on the state of the jtag controller state machine and the instruction currently in the instruction register. this shift occurs on the falling edge of tck. when not outputting test data, tdo is three-stated. it can also be placed in three-state mode to allow bussed or parallel connections to other devices having jtag. dso provides single-bit communication for debug module commands. see chapter 5, debug support. trst / dsclk test reset (mtmod0 high)/development serial clock (mtmod0 low). as trst , this pin asynchronously resets the internal jtag controller to the test logic reset state, causing the jtag instruction register to choose the idcode instruction. when this occurs, all jtag logic is benign and does not interfere with normal mcf5307 functionality. although this signal is asynchronous, motorola recommends that trst make only an asserted-to-negated transition while tms is held at a logic 1 value. trst has an internal pull-up; if it is not driven low its value defaults to a logic level of 1. however, if trst is not used, it can either be tied to ground or, if tck is clocked, to vdd. the former connection places the jtag controller in the test logic reset state immediately; the latter connection eventually puts the jtag controller (if tms is a logic 1) into the test logic reset state after 5 tck cycles. dsclk is the development serial clock for the serial interface to the debug module.the maximum dsclk frequency is 1/2 the bclko frequency. see chapter 5, debug support. table 19-1. jtag pin descriptions pin description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
19-4 mcf5307 users manual jtag register descriptions figure 19-2. jtag tap controller state machine 19.4 jtag register descriptions the following sections describe the jtag registers implemented on the mcf5307. test-logic-reset tlr run-test-idle rti select-dr-scan sedr capture-ir update-ir exit2-ir pause-ir exit1-ir shift-ir capture-dr update-dr exit2-dr pause-dr exit1-dr shift-dr 0 0 0 1 0 1 1 0 0 0 1 1 0 1 1 11 0 11 11 00 0 1 cadr shdr e1dr padr cair shir e1ir pair <-- value of tms at rising edge of tck select-ir-scan seir 1 0 0 0 1 0 upir updr e2dr e2ir f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 19. ieee 1149.1 test access port (jtag) 19-5 jtag register descriptions 19.4.1 jtag instruction shift register the mcf5307 ieee standard 1149.1 implementation uses a 3-bit instruction-shift register (ir) without parity. this register transfers its value to a parallel hold register and applies one of six instructions on the falling edge of tck when the tap state machine is in update-ir state. to load instructions into the shift portion of the register, place the serial data on tdi before each rising edge of tck. the msb of the instruction shift register is the bit closest to the tdi pin, and the lsb is the bit closest to tdo. table 19-2 describes customer-usable instructions. table 19-2. jtag instructions instruction class ir description extest (ext) required 000 selects the boundary-scan register. forces all output pins and bidirectional pins con gured as outputs to the preloaded xed values (with the sample/preload instruction) and held in the boundary-scan update registers. extest can also con gure the direction of bidirectional pins and establish high-impedance states on some pins. extest becomes active on the falling edge of tck in the update-ir state when the data held in the instruction-shift register is equivalent to octal 0. idcode (idc) optional 001 selects the idcode register for connection as a shift path between tdi and tdo. interrogates the mcf5307 for version number and other part identi cation. the idcode register is implemented in accordance with ieee standard 1149.1 so the lsb of the shift register stage is set to logic 1 on the rising edge of tck following entry into the capture-dr state. therefore, the rst bit shifted out after selecting the idcode register is always a logic 1. the remaining 31-bits are also set to xed values. see section 19.4.2, idcode register. idcode is the default value in the ir when a jtag reset occurs by either asserting trst or holding tms high while clocking tck through at least ve rising edges and the falling edge after the fth rising edge. a jtag reset causes the tap state machine to enter test-logic-reset state (normal operation of the tap state machine into the test-logic-reset state also places the default value of octal 1 into the instruction register). the shift register portion of the instruction register is loaded with the default value of octal 1 in capture-ir state and a tck rising edge occurs. sample/ preload (smp) required 100 provides two separate functions. it obtains a sample of the system data and control signals at the mcf5307 input pins and before the boundary-scan cell at the output pins. this sampling occurs on the rising edge of tck in the capture-dr state when an instruction encoding of octal 4 is in the instruction register. sampled data is observed by shifting it through the boundary-scan register to tdo by using shift-dr state. the data capture and shift are transparent to system operation. the users must provide external synchronization to achieve meaningful results because there is no internal synchronization between tck and clk. sample/preload also initializes the boundary-scan register update cells before selecting extest or clamp. this is done by ignoring data shifted out of tdo while shifting in initialization data. the update-dr state in conjunction with the falling edge of tck can then transfer this data to the update cells. this data is applied to external outputs when an instruction listed above is applied. highz (hiz) optional 101 anticipates the need to backdrive outputs and protects inputs from random toggling during board testing. selects the bypass register, forcing all output and bidirectional pins into high-impedance. highz goes active on the falling edge of tck in the update-ir state when instruction shift register data held is equivalent to octal 5. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
19-6 mcf5307 users manual jtag register descriptions the ieee standard 1149.1 requires the extest, sample/preload, and bypass instructions. idcode, clamp, and highz are optional standard instructions that the mcf5307 implementation supports and are described in the ieee standard 1149.1. 19.4.2 idcode register the mcf5307 includes an ieee standard 1149.1-compliant jtag identi cation register, idcode, which is read by the mcf5307 jtag instruction encoded as octal 1. table 19-3 describes idcode bit assignments. clamp (cmp) optional 110 selects the bypass register and asserts functional reset while forcing all output and bidirectional pins con gured as outputs to xed, preloaded values in the boundary-scan update registers. enhances test ef ciency by reducing the overall shift path to one bit (the bypass register) while conducting an extest type of instruction through the boundary-scan register. clamp becomes active on the falling edge of tck in the update-ir state when instruction-shift register data is equivalent to octal 6. bypass (byp) required 111 selects the single-bit bypass register, creating a single-bit shift register path from tdi to the bypass register to tdo. enhances test ef ciency by reducing the overall shift path when a device other than the mcf5307 is under test on a board design with multiple chips on the overall 1149.1 de ned boundary-scan chain. the bypass register is implemented in accordance with 1149.1 so the shift register stage is set to logic 0 on the rising edge of tck following entry into the capture-dr state. therefore, the rst bit shifted out after selecting the bypass register is always a logic 0 (to differentiate a part that supports an idcode register from a part that supports only the bypass register). bypass goes active on the falling edge of tck in the update-ir state when instruction shift register data is equivalent to octal 7. 31 30 29 28 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 version number (0000 forh55j, 0001 for j20c) 0100110000000011000000011101 table 19-3. idcode bit assignments bits description 31 28 version number. indicates the revision number of the mcf5307 27 22 design center. indicates the coldfire design center 21 12 device number. indicates an mcf5307 11 1 indicates the reduced jedec id for motorola. joint electron device engineering council (jedec) publication 106-a and chapter 11 of the ieee standard 1149.1 give more information on this eld. 0 identi es this as the jtag idcode register (and not the bypass register) according to the ieee standard 1149.1 table 19-2. jtag instructions (continued) instruction class ir description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 19. ieee 1149.1 test access port (jtag) 19-7 jtag register descriptions 19.4.3 jtag boundary-scan register the mcf5307 model includes an ieee standard 1149.1-compliant boundary-scan register connected between tdi and tdo when the extest or sample/preload instructions are selected. this register captures signal data on the input pins, forces xed values on the output pins, and selects the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state pins. table 19-4 shows mcf5307 boundary-scan register bits. table 19-4. boundary-scan bit definitions bit cell type pin cell pin type bit cell type pin cell pin type 0 o.ctl pp0 enable 120 o.pin be0 o 1 o.pin pp0 i/o 121 o.pin scke o 2 i.pin pp0 i/o 122 o.pin scas o 3 io.ctl pp1 enable 123 o.pin sras o 4 o.pin pp1 i/o 124 o.pin dramw o 5 i.pin pp1 i/o 125 o.pin cas3 o 6 io.ctl pp2 enable 126 o.pin cas2 o 7 o.pin pp2 i/o 127 o.pin cas1 o 8 i.pin pp2 i/o 128 o.pin cas0 o 9 io.ctl pp3 enable 129 o.pin ras1 o 10 o.pin pp3 i/o 130 o.pin ras0 o 11 i.pin pp3 i/o 131 i.pin tin1 i 12 io.ctl pp4 enable 132 i.pin tin0 i 13 o.pin pp4 i/o 133 o.pin tout0 o 14 i.pin pp4 i/o 134 o.pin tout1 o 15 io.ctl pp5 enable 135 i.pin bg i 16 o.pin pp5 i/o 136 o.pin bd o 17 i.pin pp5 i/o 137 o.pin br o 18 io.ctl pp6 enable 138 i.pin irq1 i 19 o.pin pp6 i/o 139 i.pin irq3 i 20 i.pin pp6 i/o 140 i.pin irq5 i 21 io.ctl pp7 enable 141 i.pin irq7 i 22 o.pin pp7 i/o 142 i.pin rsti i 23 i.pin pp7 i/o 143 o.pin ts i/o 24 o.pin pst3 o 144 i.pin ts i/o 25 o.pin pst2 o 145 io.ctl t a enable 26 o.pin pst1 o 146 o.pin t a i/o 27 o.pin pst0 o 147 i.pin t a i/o 28 o.pin ddata3 o 148 o.pin r/w i/o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
19-8 mcf5307 users manual jtag register descriptions 29 o.pin ddata2 o 149 i.pin r/w i/o 30 o.pin ddata1 o 150 o.pin as i/o 31 o.pin ddata0 o 151 i.pin as i/o 32 o.pin pstclk o 152 o.pin cs7 o 33 i.pin clkin i 153 o.pin cs6 o 34 io.ctl rst o enable 154 o.pin cs5 o 35 o.pin rst o i/o 155 o.pin cs4 o 36 i.pin rst o i/o 156 o.pin cs3 o 37 o.pin bclko o 157 o.pin cs2 o 38 i.pin edgesel i 158 o.pin cs1 o 39 o.pin txd0 o 159 o.pin cs0 o 40 i.pin rxd0 i 160 o.pin oe o 41 o.pin rts0 o 161 o.pin siz1 i/o 42 i.pin cts0 i 162 i.pin siz1 i/o 43 o.pin txd1 o 163 o.pin siz0 i/o 44 i.pin rxd1 i 164 i.pin siz0 i/o 45 o.pin rts1 o 165 io.ctl pp15 enable 46 i.pin cts1 i 166 i.pin pp15 i/o 47 i.pin hiz i 167 o.pin pp15 i/o 48 io.ctl data enable 168 io.ctl pp14 enable 49 o.pin d0 i/o 169 i.pin pp14 i/o 50 i.pin d0 i/o 170 o.pin pp14 i/o 51 o.pin d1 i/o 171 io.ctl pp13 enable 52 i.pin d1 i/o 172 i.pin pp13 i/o 53 o.pin d2 i/o 173 o.pin pp13 i/o 54 i.pin d2 i/o 174 io.ctl pp12 enable 55 o.pin d3 i/o 175 i.pin pp12 i/o 56 i.pin d3 i/o 176 o.pin pp12 i/o 57 o.pin d4 i/o 177 io.ctl pp11 enable 58 i.pin d4 i/o 178 i.pin pp11 i/o 59 o.pin d5 i/o 179 o.pin pp11 i/o 60 i.pin d5 i/o 180 io.ctl pp10 enable 61 o.pin d6 i/o 181 i.pin pp10 i/o 62 i.pin d6 i/o 182 o.pin pp10 i/o 63 o.pin d7 i/o 183 io.ctl pp9 enable 64 i.pin d7 i/o 184 i.pin pp9 i/o table 19-4. boundary-scan bit definitions bit cell type pin cell pin type bit cell type pin cell pin type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 19. ieee 1149.1 test access port (jtag) 19-9 jtag register descriptions 65 o.pin d8 i/o 185 o.pin pp9 i/o 66 i.pin d8 i/o 186 io.ctl pp8 enable 67 o.pin d9 i/o 187 i.pin pp8 i/o 68 i.pin d9 i/o 188 o.pin pp8 i/o 69 o.pin d10 i/o 189 io.ctl ts /r/w /siz enable 70 i.pin d10 i/o 190 io.ctl address enable 71 o.pin d11 i/o 191 o.pin a23 i/o 72 i.pin d11 i/o 192 i.pin a23 i/o 73 o.pin d12 i/o 193 o.pin a22 i/o 74 i.pin d12 i/o 194 i.pin a22 i/o 75 o.pin d13 i/o 195 o.pin a21 i/o 76 i.pin d13 i/o 196 i.pin a21 i/o 77 o.pin d14 i/o 197 o.pin a20 i/o 78 i.pin d14 i/o 198 i.pin a20 i/o 79 o.pin d15 i/o 199 o.pin a19 i/o 80 i.pin d15 i/o 200 i.pin a19 i/o 81 o.pin d16 i/o 201 o.pin a18 i/o 82 i.pin d16 i/o 202 i.pin a18 i/o 83 o.pin d17 i/o 203 o.pin a17 i/o 84 i.pin d17 i/o 204 i.pin a17 i/o 85 o.pin d18 i/o 205 o.pin a16 i/o 86 i.pin d18 i/o 206 i.pin a16 i/o 87 o.pin d19 i/o 207 o.pin a15 i/o 88 i.pin d19 i/o 208 i.pin a15 i/o 89 o.pin d20 i/o 209 o.pin a14 i/o 90 i.pin d20 i/o 210 i.pin a14 i/o 91 o.pin d21 i/o 211 o.pin a13 i/o 92 i.pin d21 i/o 212 i.pin a13 i/o 93 o.pin d22 i/o 213 o.pin a12 i/o 94 i.pin d22 i/o 214 i.pin a12 i/o 95 o.pin d23 i/o 215 o.pin a11 i/o 96 i.pin d23 i/o 216 i.pin a11 i/o 97 o.pin d24 i/o 217 o.pin a10 i/o 98 i.pin d24 i/o 218 i.pin a10 i/o 99 o.pin d25 i/o 219 o.pin a9 i/o 100 i.pin d25 i/o 220 i.pin a9 i/o table 19-4. boundary-scan bit definitions bit cell type pin cell pin type bit cell type pin cell pin type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
19-10 mcf5307 users manual restrictions 19.4.4 jtag bypass register the ieee standard 1149.1-compliant bypass register creates a single-bit shift register path from tdi to the bypass register to tdo when the bypass instruction is selected. 19.5 restrictions test logic design is static, so tck can be stopped in high or low state with no data loss. however, system logic uses a different system clock not internally synchronized to tck. operation mixing 1149.1 test logic with system functional logic that uses both clocks must coordinate and synchronize these clocks externally to the mcf5307. 101 o.pin d26 i/o 221 o.pin a8 i/o 102 i.pin d26 i/o 222 i.pin a8 i/o 103 o.pin d27 i/o 223 o.pin a7 i/o 104 i.pin d27 i/o 224 i.pin a7 i/o 105 o.pin d28 i/o 225 o.pin a6 i/o 106 i.pin d28 i/o 226 i.pin a6 i/o 107 o.pin d29 i/o 227 o.pin a5 i/o 108 i.pin d29 i/o 228 i.pin a5 i/o 109 o.pin d30 i/o 229 o.pin a4 i/o 110 i.pin d30 i/o 230 i.pin a4 i/o 111 o.pin d31 i/o 231 o.pin a3 i/o 112 i.pin d31 i/o 232 i.pin a3 i/o 113 o.pin sda od 233 o.pin a2 i/o 114 i.pin sda i 234 i.pin a2 i/o 115 o.pin scl od 235 o.pin a1 i/o 116 i.pin scl i 236 i.pin a1 i/o 117 o.pin be3 o 237 o.pin a0 i/o 118 o.pin be2 o 238 i.pin a0 i/o 119 o.pin be1 o table 19-4. boundary-scan bit definitions bit cell type pin cell pin type bit cell type pin cell pin type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 19. ieee 1149.1 test access port (jtag) 19-11 disabling ieee standard 1149.1 operation 19.6 disabling ieee standard 1149.1 operation there are two ways to use the mcf5307 without ieee standard 1149.1 test logic being active: nonuse of jtag test logic by either nontermination (disconnection) or intentionally xing tap logic values. the following issues must be addressed if ieee standard 1149.1 logic is not to be used when the mcf5307 is assembled onto a board. ? ieee standard 1149.1 test logic must remain transparent and benign to the system logic during functional operation. to ensure that the part enters the test-logic-reset state requires either connecting trst to logic 0 or connecting tck to a source that supplies ve rising edges and a falling edge after the fth rising edge. the recommended solution is to connect trst to logic 0. ? tck has no internal pull-up as is required on tms, tdi, and trst ; therefore, it must be terminated to preclude mid-level input values. figure 19-4 shows pin values recommended for disabling jtag with the mcf5307 in jtag mode. figure 19-4. disabling jtag in jtag mode disabling jtag test logic by holding mtmod0 low during reset (debug mode). this allows the ieee standard 1149.1 test controller to enter test-logic-reset state when trst is internally asserted to the controller. tap pins function as debug mode pins. in jtag mode, inputs tdi/dsi, tms/bkpt , and trst /dsclk have internal pull-ups enabled. figure 19-5 shows pin values recommended for disabling jtag in debug mode. figure 19-5. disabling jtag in debug mode tdi/dsi tck vdd trst /dsclk tms/bkpt note: mtmod0 high allows jtag mode. tdi/dsi tck debug interface trst /dsclk tms/bkpt note: mtmod0 low prohibits jtag. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
19-12 mcf5307 users manual obtaining the ieee standard 1149.1 19.7 obtaining the ieee standard 1149.1 the ieee standard 1149.1 jtag speci cation is a copyrighted document and must be obtained directly from the ieee: ieee standards department 445 hoes lane p.o. box 1331 piscataway, nj 08855-1331 usa http://stdsbbs.ieee.org/ fax: 908-981-9667 information: 908-981-0060 or 1-800-678-4333 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-1 chapter 20 electrical speci?ations this chapter describes the ac and dc electrical speci cations and thermal characteristics for the mcf5307. note that this information was correct at the time this book was published. as process technologies improve, there is a likelihood that this information may change. to con rm that this is the latest information, see motorola?s coldfire webpage, http://www.motorola.com/cold re. 20.1 general parameters table 20-1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. operating outside of these ranges may cause erratic behavior or damage to the processor. table 20-2 lists junction and ambient operating temperatures. table 20-3 lists dc electrical operating temperatures. this table is based on an operating table 20-1. absolute maximum ratings rating symbol value units supply voltage v cc -0.3 to +4.0 v maximum operating voltage v cc +3.6 v minimum operating voltage v cc +3.0 v input voltage v in -0.5 to +5.5 v storage temperature range t stg -55 to +150 o c table 20-2. operating temperatures characteristic symbol value units maximum operating junction temperature t j 105 o c maximum operating ambient temperature t amax 70 1 1 this published maximum operating ambient temperature should be used only as a system design guideline. all device operating parameters are guaranteed only when the junction temperature lies within the specified range. o c minimum operating ambient temperature t amin 0 o c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-2 mcf5307 users manual clock timing speci?ations voltage of vcc = 3.3 vdc 0.3 vdc. 20.2 clock timing speci?ations table 20-4 lists speci cations for the clock timing parameters shown in figure 20-1 and figure 20-2. table 20-3. dc electrical specifications characteristic symbol min max units operation voltage range v cc 3.0 3.6 v input high voltage v ih 2.0 3.6 v input low voltage v il -0.5 0.8 v input signal undershoot 0.8 v input signal overshoot 0.8 v input leakage current @ 0.5/2.4 v during normal operation i in 20 a high impedance (three-state) leakage current @ 0.5/2.4 v during normal operation i tsi 20 a signal low input current, v il = 0.8 v 1 1 bkpt /tms, dsi/tdi, dsclk/trst i il 01 ma signal high input current, v ih = 2.0 v 1 i ih 01 ma output high voltage i oh = 6 ma 2 , 12 ma 3 2 d[31:0], a[23:0], pp[15:0],ts , ta , siz[1:0], r/w , br , bd , rsto , as , cs [7:0], be [3:0], oe , pstclk, pst[3:0], ddata[3:0], dso, tout[1:0], scl, sda, r ts [1:0], txd[1:0] 3 bclko, ras [1:0], cas [3:0], dramw , scke, sras , scas v oh 2.4 v output low voltage i ol = 6 ma 2 , 12 ma 3 v ol 0.5 v load capacitance (all outputs) c l 50 pf capacitance 4 , v in = 0 v, f = 1 mhz 4 capacitance c in is periodically sampled rather than 100% tested. c in 10 pf table 20-4. clock timing specification num characteristic 66 mhz 90 mhz units min max min max c1 clkin cycle time 30 22 ns c2 clkin rise time (0.5v to 2.4 v) 5 5ns c3 clkin fall time (2.4v to 0.5 v) 5 5ns c4 clkin duty cycle (at 1.5 v) 40 60 40 60 % c5 pstclk cycle time 15 11 ns c6 pstclk duty cycle (at 1.5 v) 40 60 40 60 % c7 bclko cycle time 30 22 ns c8 bclko duty cycle (at 1.5 v) 45 55 45 55 % f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-3 input/output ac timing speci?ations figure 20-1 shows timings for the parameters listed in table 20-4. figure 20-1. clock timing figure 20-2 shows pstclk timings for parameters listed in table 20-4. figure 20-2. pstclk timing 20.3 input/output ac timing speci?ations table 20-5 lists speci cations for parameters shown in figure 20-3 and figure 20-4. note that inputs irq [7,5,3,1], bkpt , and as are synchronized internally; that is, the logic level is validated if the value does not change for two consecutive rising bclko edges. setup and hold times must be met only if recognition on a particular clock edge is required. table 20-5. input ac timing specification num characteristic 66 mhz 90 mhz units min max min max b1 1 valid to bclko rising (setup) 7.5 5.5 ns b2 1 bclko rising to invalid (hold) 3 2 ns b3 2 valid to bclko falling (setup) 7.5 5.5 ns b4 2 bclko falling to invalid (hold) 3 2 ns bclko bclko c1 c4 c4 c3 c2 c7 c8 c8 note: input and output ac timing speci cations are measured to bclko with a 50-pf load capacitance (not including pin capacitance). pstclk c6 c6 c5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-4 mcf5307 users manual input/output ac timing speci?ations table 20-6 lists speci cations for timings in figure 20-3, figure 20-4, and figure 20-10. although output signals that share a speci cation number have approximately the same timing, due to loading differences, they do not necessarily change at the same time. however, they have similar timings; that is, minimum and maximum times are not mixed. note that these gures show two representative bus operations and do not attempt to show all cases. for explanations of the states, s0?s5, see section 18.4, ?data transfer b5 3 bclko to input high impedance 2 2 bus clock b6 bclko to edgesel delay 0 7.5 0 5.5 ns 1 inputs: bg , t a , a[23:0], pp[15:0], siz[1:0], r/w , ts , edgesel, d[31:0], irq [7,5,3,1], and bkpt 2 inputs: as 3 inputs: d[31:0] table 20-6. output ac timing specification num characteristic 66 mhz 90 mhz units min max min max b10 1,2,3 1 outputs that only change on rising edge of bclko: rsto , ts , br , bd , ta , r/w , siz[1:0], pp[7:0] (and pp[15:8] when con gured as parallel port outputs). 2 outputs that can change on either bclko edge depending only upon edgesel: d[31:0], a[23:0], scke, sras , scas , dramw (and pp[15:8] when individually con gured as address outputs). 3 outputs that can change on either bclko edge depending only upon edgesel: d[31:0], a[23:0], scke, sras , scas , dramw (and pp[15:8] when individually con gured as address outputs). bclko rising to valid 15 11 ns b11 1,2,3,4 4 applies to d[31:0], a[23:0], r sto , ts , br , bd , ta , r/w , siz[1:0], pp[7:0] (and pp[15:8] when con gured as parallel port outputs). bclko rising to invalid (hold) 1 1 ns b11a 1,2,3,5 5 applies to ras [1:0], cas [1:0], scke, sras , scas , dramw bclko rising to invalid (hold) 0.5 0.5 b12 6,7 6 high impedance (three-state): d[31:0] 7 outputs that transition to high-impedance due to bus arbitration: a[23:0], r/w , siz[1:0], ts , as , t a , (and pp[15:0] when individually con gured as address outputs) bclko to high impedance (three-state) 15 11 ns b13 8,2,3 8 outputs that only change on falling edge of bclko: as , cs [7:0], be [3:0], oe bclko rising to valid 15 11 ns b14 8,2,3 bclko rising to invalid (hold) 3 2 ns b15 2,3 edgesel to valid 18.5 13.5 ns b16 2,3 edgesel to invalid (hold) 3 2 ns h1 hiz to high impedance 60 60 ns h2 hiz to low impedance 60 60 ns table 20-5. input ac timing specification num characteristic 66 mhz 90 mhz units min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-5 input/output ac timing speci?ations operation.? note that figure 20-4 does not show all signals that apply to each timing speci cation. see the previous tables for a complete listing. figure 20-3 shows ac timings for normal read and write bus cycles. figure 20-3. ac timings?ormal read and write bus cycles figure 20-4 shows timings for a read cycle with edgesel tied to buffered bclko. bclko a[31:0] r/w ts as , cs , oe d[31:0] t a b10 b13 b11 b2 b1 b14 b5 b10 b11 b12 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 tm[2:0] tt[1:0] siz[1:0] be /bwe [3:0] tip f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-6 mcf5307 users manual input/output ac timing speci?ations figure 20-4. sdram read cycle with edgesel tied to buffered bclko figure 20-5 shows an sdram write cycle with edgesel tied to buffered bclko. a[31:0] ts sras scas 1 d[31:0] actv nop pall nop ras read row column edgesel dramw cas b16 b15 b15 b16 b2 b1 b16 b16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bclko 1 dacr[casl] = 2 b6 nop nop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-7 input/output ac timing speci?ations figure 20-5. sdram write cycle with edgesel tied to buffered bclko figure 20-6 shows an sdram read cycle with edgesel tied high. a[31:0] ts sras scas 1 d[31:0] actv pall nop ras write row column edgesel dramw cas b16 b15 b15 b16 b16 b16 0 1 2 3 4 5 6 7 8 9 10 11 12 bclko b15 1 dacr[casl] = 2 b6 nop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-8 mcf5307 users manual input/output ac timing speci?ations figure 20-6. sdram read cycle with edgesel tied high figure 20-7 shows an sdram write cycle with edgesel tied high. a[31:0] ts sras d[31:0] actv nop pall nop ras read row column bclko 0 dramw cas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 b11 b10 b10 b11a b2 b1 b11a b11a 1 dacr[casl] = 2 scas 1 nop b11a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-9 input/output ac timing speci?ations figure 20-7. sdram write cycle with edgesel tied high figure 20-8 shows an sdram read cycle with edgesel tied low. a[31:0] ts sras scas 1 d[31:0] actv pall nop ras write row column bclko dramw cas b10 b10 b11a b11 b11a 0 1 2 3 4 5 6 7 8 9 10 11 12 b10 nop 1 dacr[casl] = 2 b11a b11 b11a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-10 mcf5307 users manual input/output ac timing speci?ations figure 20-8. sdram read cycle with edgesel tied low figure 20-9 shows an sdram write cycle with edgesel tied low. a[31:0] ts sras d[31:0] actv nop pall nop ras read row column bclko 0 dramw cas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 b14 b13 b13 b14 b2 b1 b14 b14 scas 1 1 dacr[casl] = 2 nop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-11 input/output ac timing speci?ations figure 20-9. sdram write cycle with edgesel tied low figure 20-10 shows ac timing showing high impedance. figure 20-10. ac output timing?igh impedance a[31:0] ts sras scas 1 d[31:0] actv pall nop ras write row column bclko dramw cas b14 b13 b13 b14 b14 b14 0 1 2 3 4 5 6 7 8 9 10 11 12 b13 1 dacr[casl] = 2 nop h1 h2 hiz outputs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-12 mcf5307 users manual reset timing speci?ations 20.4 reset timing speci?ations table 20-7 lists speci cations for the reset timing parameters shown in figure 20-11. figure 20-11 shows reset timing for the values in table 20-7. figure 20-11. reset timing 20.5 debug ac timing speci?ations table 20-8 lists speci cations for the debug ac timing parameters shown in figure 20-13. table 20-7. reset timing specification num characteristic 66 mhz 90 mhz units min max min max r1 1 1 rsti and d[7:0] are synchronized internally. setup and hold times must be met only if recognition on a particular clock is required. valid to clkin (setup) 7.5 5.5 ns r2 clkin to invalid (hold) 3 2 ns r3 rsti to invalid (hold) 3 2 ns table 20-8. debug ac timing specification num characteristic 66 mhz 90 mhz units min max min max d1 pst, ddata to pstclk setup 7.5 5.5 ns d2 pstclk to pst, ddata hold 7.5 5.5 ns d3 dsi-to-dsclk setup 1 1 pstclks clkin rsti d[7:0] r2 r1 r1 r3 note: mode selects are registered on the rising clkin edge before the cycle in which rsti is recognized as being negated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-13 debug ac timing speci?ations figure 20-12 shows real-time trace timing for the values in table 20-8. figure 20-12. real-time trace ac timing figure 20-13 shows bdm serial port ac timing for the values in table 20-8. figure 20-13. bdm serial port ac timing d4 1 dsclk-to-dso hold 4 4 pstclks d5 dsclk cycle time 5 5 pstclks 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of pstclk. table 20-8. debug ac timing specification num characteristic 66 mhz 90 mhz units min max min max pstclk pst[3:0] d2 d1 ddata[3:0] dsi dso current next pstclk past current dsclk d3 d4 d5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-14 mcf5307 users manual timer module ac timing speci?ations 20.6 timer module ac timing speci?ations table 20-9 lists speci cations for timer module ac timing parameters shown in figure 20-14. figure 20-14 shows timings for table 20-9. figure 20-14. timer module ac timing table 20-9. timer module ac timing specification num characteristic 66 mhz 90 mhz units min max min max t1 tin cycle time 3 3 bus clocks t2 tin valid to bclko (input setup) 7.5 5.5 ns t3 bclko to tin invalid (input hold) 3 2 ns t4 bclko to tout valid (output valid) 15 11 ns t5 bclko to tout invalid (output hold) 1.5 1.5 ns t6 tin pulse width 1 1 bus clocks t7 tout pulse width 1 1 bus clocks bclko t6 t2 t3 t1 t7 t4 t5 tin tin tout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-15 i 2 c input/output timing speci?ations 20.7 i 2 c input/output timing speci?ations table 20-10 lists speci cations for the i 2 c input timing parameters shown in figure 20.8. table 20-11 lists speci cations for the i 2 c output timing parameters shown in figure 20.8. table 20-10. i 2 c input timing specifications between scl and sda num characteristic 66 mhz 90 mhz units min max min max i1 start condition hold time 2 2 bus clocks i2 clock low period 8 8 bus clocks i3 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) 1 1ms i4 data hold time 0 0 ns i5 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) 1 1ms i6 clock high time 4 4 bus clocks i7 data setup time 0 0 ns i8 start condition setup time (for repeated start condition only) 2 2 bus clocks i9 stop condition setup time 2 2 bus clocks table 20-11. i 2 c output timing specifications between scl and sda num characteristic 66 mhz 90 mhz units min max min max i1 1 1 note: output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in table 20-11. the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the scl low period. the actual position is affected by the prescale and division values programmed into the ifdr; however, the numbers given in table 20-11 are minimum values. start condition hold time 6 6 bus clocks i2 1 clock low period 10 10 bus clocks i3 2 2 because scl and sda are open-collector-type outputs, which the processor can only actively drive low, the time scl or sda take to reach a high level depends on external signal capacitance and pull-up resistor values. scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) s i4 1 data hold time 7 7 bus clocks i5 3 3 speci ed at a nominal 50-pf load. scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) 3 3ns i6 1 clock high time 10 10 bus clocks i7 1 data setup time 2 2 bus clocks i8 1 start condition setup time (for repeated start condition only) 20 20 bus clocks i9 1 stop condition setup time 10 10 bus clocks f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-16 mcf5307 users manual uart module ac timing speci?ations figure 20.8 shows timing for the values in table 20-10 and table 20-11. figure 20-15. i 2 c input/output timings 20.8 uart module ac timing speci?ations table 20-12 lists speci cations for uart module ac timing parameters in figure 20-16. figure 20-16 shows uart timing for the values in table 20-12. table 20-12. uart module ac timing specifications num characteristic 66 mhz 90 mhz units min max min max u1 rxd valid to bclko (input setup) 7.5 5.5 ns u2 bclko to rxd invalid (input hold) 3 2 ns u3 cts valid to bclko (input setup) 7.5 5.5 ns u4 bclko to cts invalid (input hold) 3 2 ns u5 bclko to txd valid (output valid) 15 11 ns u6 bclko to txd invalid (output hold) 1.5 1.5 ns u7 bclko to r ts valid (output valid) 15 11 ns u8 bclko to r ts invalid (output hold) 1.5 1.5 ns i2 i6 i1 i4 i7 i8 i9 i5 i3 scl sda f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-17 uart module ac timing speci?ations figure 20-16. uart0/1 module ac timing?art mode bclko rxd cts txd r ts u1 u2 u3 u4 u5 u6 u7 u8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-18 mcf5307 users manual parallel port (general-purpose i/o) timing speci?ations 20.9 parallel port (general-purpose i/o) timing speci?ations table 20-13 lists speci cations for general-purpose i/o timing parameters in figure 20-17. figure 20-17 shows general-purpose i/o timing. figure 20-17. general-purpose i/o timing table 20-13. general-purpose i/o port ac timing specifications num characteristic 66 mhz 90 mhz units min max min max p1 pp valid to bclko (input setup) 7.5 5.5 ns p2 bclko to pp invalid (input hold) 3 2 ns p3 bclko to pp valid (output valid) 15 11 ns p4 bclko to pp invalid (output hold) 1 1 ns bclko pp in pp out p1 p2 p4 p3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-19 dma timing speci?ations 20.10 dma timing speci?ations table 20-14 lists speci cations for dma timing parameters shown in figure 20-17. figure 20-18 shows dma ac timing. figure 20-18. dma timing table 20-14. dma ac timing specifications num characteristic 66 mhz 90 mhz units min max min max m1 dreq valid to bclko (input setup) 7.5 5.5 ns m2 bclko to dreq invalid (input hold) 3 2 ns bclko dreq m1 m2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-20 mcf5307 users manual ieee 1149.1 (jtag) ac timing speci?ations 20.11 ieee 1149.1 (jtag) ac timing speci?ations table 20-15 lists speci cations for jtag ac timing parameters shown in figure 20-19. figure 20-19 shows jtag timing. table 20-15. ieee 1149.1 (jtag) ac timing specifications num characteristic all frequencies units min max tck frequency of operation 0 10 mhz j1 tck cycle time 100 ns j2a tck clock pulse high width (measured at 1.5 v) 40 ns j2b tck clock pulse low width (measured at 1.5 v) 40 ns j3a tck fall time (v ih = 2.4 v to v il = 0.5v) 5ns j3b tck rise time (v il = 0.5v to v ih = 2.4v) 5ns j4 tdi, tms to tck rising (input setup) 10 ns j5 tck rising to tdi, tms invalid (hold) 15 ns j6 boundary scan data valid to tck (setup) 10 ns j7 tck to boundary-scan data invalid (hold) 15 ns j8 trst pulse width (asynchronous to clock edges) 15 j9 tck falling to tdo valid (signal from driven or three-state) 30 ns j10 tck falling to tdo high impedance 30 ns j11 tck falling to boundary scan data valid (signal from driven or three-state) 30 ns j12 tck falling to boundary scan data high impedance 30 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 20. electrical speci?ations 20-21 ieee 1149.1 (jtag) ac timing speci?ations figure 20-19. ieee 1149.1 (jtag) ac timing j1 j2a j2b j4 j5 j6 j7 j8 j9 j10 j11 j12 j3a j3b tck tdi, tms trst tdo boundary scan data output boundary scan data input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20-22 mcf5307 users manual ieee 1149.1 (jtag) ac timing speci?ations f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
appendix a. list of memory maps a-1 appendix a list of memory maps table a-1. sim registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x000 reset status register (rsr) [p. 6-5] system protection control register (sypcr) [p. 6-8] software watchdog interrupt vector register (swivr) [p. 6-9] software watchdog service register (swsr) [p. 6-9] 0x004 pin assignment register (par) [p. 6-10] interrupt port assignment register (irqpar) [p. 9-7] reserved 0x008 pll control (pllcr) [p. 7-3] reserved 0x00c default bus master park register (mpark) [p. 6-11] reserved 0x010 0x03c reserved table a-2. interrupt controller registers mbar offset [31:24] [23:16] [15:8] [7:0] interrupt registers [p. 9-3] 0x040 interrupt pending register (ipr) [p. 9-6] 0x044 interrupt mask register (imr) [p. 9-6] 0x048 reserved autovector register (avr) [p. 9-5] interrupt control registers (icrs) [p. 9-3] 0x04c software watchdog timer (icr0) [p. 6-6] timer0 (icr1) [p. 9-2] timer1 (icr2) [p. 9-3] i 2 c (icr3) [p. 9-3] 0x050 uart0 (icr4) [p. 9-3] uart1 (icr5) [p. 9-3] dma0 (icr6) [p. 9-3] dma1 (icr7) [p. 9-3] 0x054 dma2 (icr8) [p. 9-3] dma3 (icr9) [p. 9-3] reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-2 mcf5307 users manual table a-3. chip-select registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x080 chip-select address register bank 0 (csar0) [p. 10-6] reserved 1 0x084 chip-select mask register bank 0 (csmr0) [p. 10-6] 0x088 reserved 1 chip-select control register bank 0 (cscr0) [p. 10-8] 0x08c chip-select address register bank 1 (csar1) [p. 10-6] reserved 1 0x090 chip-select mask register bank 1 (csmr1) [p. 10-6] 0x094 reserved 1 chip-select control register bank 1 (cscr1) [p. 10-8] 0x098 chip-select address register bank 2 (csar2) [p. 10-6] reserved 1 0x09c chip-select mask register bank 2 (csmr2) [p. 10-6] 0x0a0 reserved 1 chip-select control register bank 2 (cscr2) [p. 10-8 0x0a4 chip-select address register bank 3 (csar3) [p. 10-6] reserved 1 0x0a8 chip-select mask register bank 3 (csmr3) [p. 10-6] 0x0ac reserved 1 chip-select control register bank 3 (cscr3) [p. 10-8] 0x0b0 chip-select address register bank 4 (csar4) [p. 10-6] reserved 1 0x0b4 chip-select mask register bank 4 (csmr4) [p. 10-6] 0x0b8 reserved 1 chip-select control register bank 4 (cscr4) [p. 10-8] 0x0bc chip-select address register bank 5 (csar5) [p. 10-6] reserved 1 0x0c0 chip-select mask register bank 5 (csmr5) [p. 10-6] 0x0c4 reserved chip-select control register bank 5 (cscr5) [p. 10-8] 0x0c8 chip-select address register bank 6 (csar6) [p. 10-6] reserved 1 0x0cc chip-select mask register bank 6 (csmr6) [p. 10-6] 0x0d0 reserved 1 chip-select control register bank 6 (cscr6) [p. 10-8] 0x0d4 chip-select address register bank 7 (csar7) [p. 10-6] reserved 1 0x0d8 chip-select mask register bank 7 (csmr7) [p. 10-6] 0x0dc reserved 1 chip-select control register bank 7 (cscr7) [p. 10-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
appendix a. list of memory maps a-3 mbar offset [31:24] [23:16] [15:8] [7:0] 0x080 chip-select address register bank 0 (csar0) [p. 10-6] reserved 1 0x084 chip-select mask register bank 0 (csmr0) [p. 10-6] 0x088 reserved 1 chip-select control register bank 0 (cscr0) [p. 10-8] 0x08c chip-select address register bank 1 (csar1) [p. 10-6] reserved 1 0x090 chip-select mask register bank 1 (csmr1) [p. 10-6] 0x094 reserved 1 chip-select control register bank 1 (cscr1) [p. 10-8] 0x098 chip-select address register bank 2 (csar2) [p. 10-6] reserved 1 0x09c chip-select mask register bank 2 (csmr2) [p. 10-6] 0x0a0 reserved 1 chip-select control register bank 2 (cscr2) [p. 10-8] 0x0a4 chip-select address register bank 3 (csar3) [p. 10-6] reserved 1 0x0a8 chip-select mask register bank 3 (csmr3) [p. 10-6] 0x0ac reserved 1 chip-select control register bank 3 (cscr3) [p. 10-8] 0x0b0 chip-select address register bank 4 (csar4) [p. 10-6] reserved 1 0x0b4 chip-select mask register bank 4 (csmr4) [p. 10-6] 0x0b8 reserved 1 chip-select control register bank 4 (cscr4) [p. 10-8] 1 addresses not assigned to a register and undefined register bits are reserved for expansion. write accesses to these reserved address spaces and reserved register bits have no effect. table a-4. dram controller registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x100 dram control register (dcr) [p. 11-3] reserved 0x104 reserved 0x108 dram address and control register 0 (dacr0) [p. 11-3] 0x10c dram mask register block 0 (dmr0) [p. 11-3] 0x110 dram address and control register 1 (dacr1) [p. 11-3] 0x114 dram mask register block 1 (dmr1) [p. 11-3] table a-3. chip-select registers (continued) mbar offset [31:24] [23:16] [15:8] [7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-4 mcf5307 users manual table a-5. general-purpose timer registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x140 timer 0 mode register (tmr0) [p. 13-3] reserved 0x144 timer 0 reference register (trr0) [p. 13-4] reserved 0x148 timer 0 capture register (tcr0) [p. 13-4] reserved 0x14c timer 0 counter (tcn0) [p. 13-5] reserved 0x150 reserved timer 0 event register (ter0) [p. 13-5] reserved 0x180 timer 1 mode register (tmr1) [p. 13-3] reserved 0x184 timer 1 reference register (trr1) [p. 13-4] reserved 0x188 timer 1 capture register (tcr1) [p. 13-4] reserved 0x18c timer 1 counter (tcn1) [p. 13-5] reserved 0x190 reserved timer 1 event register (ter1) [p. 13-5] reserved table a-6. uart0 module programming model mbar offset [31:24] [23:16] [15:8] [7:0] 0x1c0 uart mode registers 1 (umr1 n ) [p. 14-4], (umr2 n ) [p. 14-6] 0x1c4 (read) uart status registers (usr n ) [p. 14-7] (write) uart clock-select register 1 (ucsr n ) [p. 14-8] 0x1c8 (read) do not access 2 (write) uart command registers (ucr n ) [p. 14-9] 0x1cc (uart/read) uart receiver buffers (urb n ) [p. 14-11] (uart/write) uart transmitter buffers (utb n ) [p. 14-11] 0x1d0 (read) uart input port change registers (uipcr n ) [p. 14-12] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
appendix a. list of memory maps a-5 (write) uart auxiliary control registers 1 (uacr n ) [p. 14-12] 0x1d4 (read) uart interrupt status registers (uisr n ) [p. 14-13] (write) uart interrupt mask registers (uimr n ) [p. 14-13] 0x1d8 uart divider upper registers (udu n ) [p. 14-14] 0x1dc uart divider lower registers (udl n ) [p. 14-14] 0x1e0 0x1ec do not access 2 0x1f0 uart interrupt vector register (uivr n ) [p. 14-15] 0x1f4 (read) uart input port registers (uip n ) [p. 14-15] (write) do not access 2 0x1f8 (read) do not access 2 (write) uart output port bit set command registers (uop1 n 3 ) [p. 14-15] 0x1fc (read) do not access 2 (write) uart output port bit reset command registers (uop0 n 3 ) [p. 14-15] 1 umr1 n , umr2 n , and ucsr n should be changed only after the receiver/transmitter is issued a software reset command. that is, if channel operation is not disabled, undesirable results may occur. 2 this address is for factory testing. reading this location results in undesired effects and possible incorrect transmission or reception of characters. register contents may also be changed. 3 address-triggered commands table a-6. uart0 module programming model (continued) mbar offset [31:24] [23:16] [15:8] [7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-6 mcf5307 users manual table a-7. uart1 module programming model mbar offset [31:24] [23:16] [15:8] [7:0] 0x200 uart mode registers 1 (umr1 n ) [p. 14-4], (umr2 n ) [p. 14-6] 0x204 (read) uart status registers (usr n ) [p. 14-7] (write) uart clock-select register 1 (ucsr n ) [p. 14-8] 0x208 (read) do not access 2 (write) uart command registers (ucr n ) [p. 14-9] 0x20c (uart/read) uart receiver buffers (urb n ) [p. 14-11] (uart/write) uart transmitter buffers (utb n ) [p. 14-11] 0x210 (read) uart input port change registers (uipcr n ) [p. 14-12] (write) uart auxiliary control registers 1 (uacr n ) [p. 14-12] 0x214 (read) uart interrupt status registers (uisr n ) [p. 14-13] (write) uart interrupt mask registers (uimr n ) [p. 14-13] 0x218 uart divider upper registers (udu n ) [p. 14-14] 0x21c uart divider lower registers (udl n ) [p. 14-14] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
appendix a. list of memory maps a-7 0x220 0x22c do not access 2 0x230 uart interrupt vector register (uivr n ) [p. 14-15] 0x234 (read) uart input port registers (uip n ) [p. 14-15] (write) do not access 2 0x238 (read) do not access 2 (write) uart output port bit set command registers (uop1 n 3 ) [p. 14-15] 0x23c (read) do not access 2 (write) uart output port bit reset command registers (uop0 n 3 ) [p. 14-15] 1 umr1 n , umr2 n , and ucsr n should be changed only after the receiver/transmitter is issued a software reset command. that is, if channel operation is not disabled, undesirable results may occur. 2 this address is for factory testing. reading this location results in undesired effects and possible incorrect transmission or reception of characters. register contents may also be changed. 3 address-triggered commands table a-8. parallel port memory map mbar offset [31:24] [23:16] [15:8] [7:0] 0x244 parallel port data direction register (paddr) [p. 15-2] reserved 0x248 parallel port data register (padat) [p. 15-2] reserved table a-9. i 2 c interface memory map mbar offset [31:24] [23:16] [15:8] [7:0] 0x280 i 2 c address register (iadr) [p. 8-6] reserved 0x284 i 2 c frequency divider register (ifdr) [p. 8-7] reserved table a-7. uart1 module programming model (continued) mbar offset [31:24] [23:16] [15:8] [7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-8 mcf5307 users manual 0x288 i 2 c control register (i2cr) [p. 8-8] reserved 0x28c i 2 c status register (i2sr) [p. 8-9] reserved 0x290 i 2 c data i/o register (i2dr) [p. 8-10] reserved table a-10. dma controller registers mbar offset [31:24] [23:16] [15:8] [7:0] 0x300 source address register 0 (sar0) [p. 12-6] 0x304 destination address register 0 (dar0) [p. 12-7] 0x308 dma control register 0 (dcr0) [p. 12-8] 0x30c byte count register 0 (bcr24bit = 0) 1 reserved 0x30c reserved byte count register 0 (bcr24bit = 1) 1 (bcr0) [p. 12-7] 0x310 dma status register 0 (dsr0) [p. 12-10] reserved 0x314 dma interrupt vector register 0 (divr0) [p. 12-11] reserved 0x340 source address register 1 (sar1) [p. 12-6] 0x344 destination address register 1 (dar1) [p. 12-7] 0x348 dma control register 1 (dcr1) [p. 12-8] 0x34c byte count register 1 (bcr24bit = 0) 1 reserved 0x34c reserved byte count register 1 (bcr24bit = 1) 1 (bcr1) [p. 12-7] 0x350 dma status register 1 (dsr1) [p. 12-10] reserved 0x354 dma interrupt vector register 1 (divr1) [p. 12-11] reserved 0x380 source address register 2 (sar2) [p. 12-6] 0x384 destination address register 2 (dar2) [p. 12-7] 0x388 dma control register 2 (dcr2) [p. 12-8] 0x38c byte count register 2 (bcr24bit = 0) 1 reserved 0x38c reserved byte count register 2 (bcr24bit = 1) 1 (bcr2) [p. 12-7] 0x390 dma status register 2 (dsr2) [p. 12-10] reserved table a-9. i 2 c interface memory map mbar offset [31:24] [23:16] [15:8] [7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
appendix a. list of memory maps a-9 0x394 dma interrupt vector register 2 (divr2) [p. 12-11] reserved 0x3c0 source address register 3 (sar3) [p. 12-6] 0x3c4 destination address register 3 (dar3) [p. 12-7] 0x3c8 dma control register 3 (dcr3) [p. 12-8] 0x3cc byte count register 3 (bcr24bit = 0) 1 reserved 0x3cc reserved byte count register 3 (bcr24bit = 1) 1 (bcr3) [p. 12-7] 0x3d0 dma status register 3 (dsr3) [p. 12-10] reserved 0x3d4 dma interrupt vector register 3 (divr3) [p. 12-11] reserved 1 on the 0h55j and 1h55j revisions of the mcf5307, the byte count register of the dma channels can accommodate only 16 bits. however, on the newest revision of the mcf5307, an expanded 24-bit byte count range provides greater exibility. for this reason, the position of the byte count register (bcr) in the memory map depends on whether a 16- or 24-bit byte counter is chosen. the selection is made by programming mpark[bcr24bit] in the sim module. in the new mcf5307, the 24-bit byte count can be selected by setting bcr24bit = 1, making dcr[at] available. the at bit selects whether the dma channels assert an acknowledge during the entire transfer or only at the nal transfer of a dma transaction. new applications should take advantage of the full range of the 24-bit byte counter, including the at bit. the 16-bit byte count option (bcr24bit = 0) is kept to retain compatibility with older revisions of the mcf5307. table a-10. dma controller registers (continued) mbar offset [31:24] [23:16] [15:8] [7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-10 mcf5307 users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
glossary of terms and abbreviations glossary-11 glossary of terms and abbreviations the glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. architecture. a detailed speci cation of requirements for a processor or computer system. it does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible implementations . autovector. a method of determining the starting address of the service routine by fetching the value from a lookup table internal to the processor instead of requesting the value from the system. branch prediction .the process of guessing whether a branch will be taken. such predictions can be correct or incorrect; the term ?predicted? as it is used here does not imply that the prediction is correct (successful). branch resolution .the determination of whether a branch is taken or not taken. a branch is said to be resolved when the processor can determine which instruction path to take. if the branch is resolved as predicted, the instructions following the predicted branch that may have been speculatively executed can complete (see completion). if the branch is not resolved as predicted, instructions on the mispredicted path, and any results of speculative execution, are purged from the pipeline and fetching continues from the nonpredicted path. burst . a multiple-beat data transfer. cache . high-speed memory containing recently accessed data and/or instructions (subset of main memory). cache coherency . an attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system. caches are coherent if a processor performing a read from a b c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
glossary-12 mcf5307 users manual its cache is supplied with data corresponding to the most recent value written to memory or to another processor?s cache. cache ?sh . an operation that removes from a cache any data from a speci ed address range. this operation ensures that any modi ed data within the speci ed address range is written back to main memory. cache line . the smallest unit of consecutive data or instructions that is stored in a cache. for coldfire processors a line consists of 16 bytes. caching-inhibited . a memory update policy in which the cache is bypassed and the load or store is performed to or from main memory. cast outs . cache lines that must be written to memory when a cache miss causes a cache line to be replaced. clear . to cause a bit or bit eld to register a value of zero. see also set. copyback . a cache memory update policy in which processor write cycles are directly written only to the cache. external memory is updated only indirectly, for example, when a modi ed cache line is cast out to make room for newer data. effective address (ea) . the 32-bit address speci ed for an instruction. exception . a condition encountered by the processor that requires special, supervisor-level processing. exception handler . a software routine that executes when an exception is taken. normally, the exception handler corrects the condition that caused the exception, or performs some other meaningful task (that may include aborting the program that caused the exception). the address for each exception handler is identi ed by an exception vector de ned by the coldfire architecture. fetch . the act of retrieving instructions from either the cache or main memory and making them available to the instruction unit. flush . an operation that causes a modi ed cache line to be invalidated and the data to be written to memory. illegal instructions . a class of instructions that are not implemented for a particular processor. these include instructions not de ned by the coldfire architecture. e f h i f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
glossary of terms and abbreviations glossary-13 implementation . a particular processor that conforms to the coldfire architecture, but may differ from other architecture-compliant implementations for example in design, feature set, and implementation of optional features. the coldfire architecture has many different implementations. imprecise mode. a memory access mode that allows write accesses to a speci ed memory region to occur out of order. instruction queue . a holding place for instructions fetched from the current instruction stream. instruction latency . the total number of clock cycles necessary to execute an instruction and make the results of that instruction available. interrupt . an asynchronous exception . on coldfire processors, interrupts are a special case of exceptions. see also asynchronous exception. invalid state . state of a cache entry that does not currently contain a valid copy of a cache line from memory. least-signi?ant bit (lsb) . the bit of least value in an address, register, data element, or instruction encoding. least-signi?ant byte (lsb) . the byte of least value in an address, register, data element, or instruction encoding. longword . a 32-bit data element master. a device able to initiate data transfers on a bus. bus mastering refers to a feature supported by some bus architectures that allow a controller connected to the bus to communicate directly with other devices on the bus without going through the cpu. memory coherency . an aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory. modi?d state . cache state in which only one caching device has the valid data for that address. most-signi?ant bit (msb) . the highest-order bit in an address, registers, data element, or instruction encoding. most-signi?ant byte (msb) . the highest-order byte in an address, registers, data element, or instruction encoding. l l m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
glossary-14 mcf5307 users manual nop . no-operation. a single-cycle operation that does not affect registers or generate bus activity. over?w . an condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register(s). for example, if two 16-bit numbers are multiplied, the result may not be representable in 16 bits. pipelining . a technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one completes. precise mode. a memory access mode that ensures that all write accesses to a speci ed memory region occur in order. set (v) to write a nonzero value to a bit or bit eld; the opposite of clear . the term ?set? may also be used to generally describe the updating of a bit or bit eld. set ( n ). a subdivision of a cache . cacheable data can be stored in a given location in any one of the sets, typically corresponding to its lower- order address bits. because several memory locations can map to the same location, cached data is typically placed in the set whose cache line corresponding to that address was used least recently. see set- associativity. set-associativity . aspect of cache organization in which the cache space is divided into sections, called sets . the cache controller associates a particular main memory address with the contents of a particular set, or region, within the cache. slave . the device addressed by a master device. the slave is identi ed in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure. static branch prediction . mechanism by which software (for example, compilers) can hint to the machine hardware about the direction a branch is likely to take. supervisor mode . the privileged operation state of a processor. in supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. n o p s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
glossary of terms and abbreviations glossary-15 system memory . the physical memory available to a processor. tenure . a tenure consists of three phases: arbitration, transfer, termination. there can be separate address bus tenures and data bus tenures. throughput . the measure of the number of instructions that are processed per clock cycle. transfer termination . the successful or unsuccessful conclusion of a data transfer. under?w. a condition that occurs during arithmetic operations when the result cannot be represented accurately in the destination register. user mode . the operating state of a processor used typically by application software. in user mode, software can access only certain control registers and can access only user memory space. no privileged operations can be performed. word . a 16-bit data element. write-through . a cache memory update policy in which all processor write cycles are written to both the cache and memory. t u v w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
glossary-16 mcf5307 users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index index-17 a accumulator (acc), 2-28 addressing mode summary, 2-33 variant, 5-5 arbitration between masters, 6-14 bus control, 6-11 for internal transfers, 6-12 b baud rates calculating, 14-19 bus operation arbitration control, 6-11 characteristics, 18-2 control signals, 18-1 data transfer back-to-back cycles, 18-10 burst cycles line read bus, 18-12 line transfers, 18-12 line write bus, 18-14 mixed port sizes, 18-15 overview, 18-11 cycle execution, 18-4 cycle states, 18-5 fast-termination cycles, 18-9 operation, 18-3 read cycle, 18-7 write cycle, 18-8 errors, 18-17 external master transfers general, 18-21 two-device arbitration protocol, 18-25 two-wire mode, 18-25 features, 18-1 interrupt exceptions, 18-17 master park register, 6-11 misaligned operands, 18-16 reset master, 18-34 overview, 18-33 software watchdog, 18-35 c ccr, 2-28 chip-select module 8-, 16-, and 32-bit port sizing, 10-4 enable signals, 17-15 operation, 10-2 general, 10-3 global, 10-4 overview, 10-1 registers, 10-5, 10-6, a-2 code example, 10-9 control, 10-8 mask, 10-6 signals, 10-1 clock pll control, 6-10 coldfire core addressing mode summary, 2-33 condition code register (ccr), 2-28 exception processing overview, 2-47 features and enhancements, 2-21 instruction set summary, 2-34 integer data formats, 2-31 mac registers, 1-14 programming model, 2-26 status register, 2-29 supervisor programming model, 2-29 user programming mode, 2-27 cpu stop instruction, 6-10 d debug attribute trigger register, 5-7 bdm command set summary, 5-20 breakpoint operation, 5-40 real-time support, 5-39 taken branch, 5-4 theory, 5-40 dma controller module byte count registers, 12-7 programming model, 12-4 signal description, 12-2 source address registers, 12-6 timing specifications, 20-19 transfer overview, 12-3 dram controller asynchronous operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-18 mcf5307 users manual burst page mode, 11-12 continuous page mode, 11-13 extended data out, 11-15 general, 11-4 mode signals, 11-4 register set, 11-4 general guidelines, 11-8 non-page mode, 11-11 refresh operation, 11-16 registers, 11-3 address and control, 11-5 mask, 11-7 signals, 17-16 synchronous operation address and control registers, 11-20 address multiplexing, 11-23 auto-refresh, 11-31 burst page mode, 11-27 continuous page mode, 11-29 controller signals, 11-17 edge select, 11-18 general guidelines, 11-23 initialization, 11-33 interfacing, 11-27 mask registers, 11-22 mode register settings, 11-33 register set, 11-19 self-refresh, 11-32 dsclk, 5-2 e electrical specifications clock timing, 20-2 debug ac timing, 20-12 dma timing, 20-19 general parameters, 20-1 i 2 c input/output timing, 20-15 input/iutput ac timing, 20-3 jtag ac timing, 20-20 parallel port timing, 20-18 reset timing, 20-12 timer module ac timing, 20-14 uart module ac timing, 20-16 f fault-on-fault halt, 5-16 h halt fault-on-fault, 5-16 i i 2 c address register, 8-6 arbitration procedure, 8-4 clock stretching, 8-5 synchronization, 8-5 control register, 8-8 data i/o register, 8-10 features, 8-1 frequency divider register, 8-7 handshaking, 8-5 interface memory map, a-7 lost arbitration, 8-13 overview, 8-1 programming examples, 8-10 model, 8-6 protocol, 8-3 repeated start generation, 8-12 slave mode, 8-13 software response, 8-11 start generation, 8-10 status register, 8-9 stop generation, 8-12 system configuration, 8-3 timing specifications, 20-15 ieee standard 1149.1 test access port, see jtag instruction set general summary, 2-34 mac summary, 3-4 mac unit execution times, 3-5 integer data formats memory, 2-32 registers, 2-31 interrupt controller autovector register, 9-5 overview, 9-1 pending and mask registers, 9-6 port assignment register, 9-7 j jtag ac timing, 20-20 obtaining ieee standard 1149.1, 19-12 overview, 19-1 registers boundary scan, 19-7 bypass, 19-10 descriptions, 19-4 idcode, 19-6 instruction shift, 19-5 restrictions, 19-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index index-19 signal descriptions, 19-2 tap controller, 19-3 test logic disabling, 19-11 m mac data representation, 3-4 instruction execution timings, 3-5 instruction set summary, 3-4 operation, 3-3 programming model, 2-26, 3-2 status register (macsr), 1-14, 2-29 mask registers dram, 11-7, 11-22 mac, 1-14, 2-29 mbar, 6-4 mechanical data case drawing, 16-9 diagram, 16-8 pinout, 16-1 memory sim register, 6-3 movec instruction, 5-36 o output port command registers, 14-15 p parallel port code example, 15-3 data direction register, 15-2 data register, 15-2 operation, 15-1 pin assignment register, 6-10, 15-1 pll, 7-2 clock control for stop, 6-10 clock frequency relationships, 7-4 control register, 7-3 modes, 7-2 operation, 7-2 overview, 7-1 port list, 7-3 power supply filter circuit, 7-6 reset/initialization, 7-2 timing relationships, 7-4 power supply filter circuit, 7-6 privilege level modes, 1-12 programming models overview, 2-26 sim, 6-3 summary, a-1 supervisor, 2-29 user, 2-27 pst outputs, 5-3 pulse instruction, 5-4 r registers ablr/abhr, 5-7, 5-8 address (a0 ? a6), 2-27 avr, 9-5 bdm address attribute, 5-9 bus master park, 6-11 chip-select control, 10-8 mask, 10-6 module, 10-5 condition code, 2-28 condition code (ccr), 2-28 data breakpoint/mask, 5-12 data d0 - d7, 2-27 dbr/dbmr, 5-7 debug attribute trigger, 5-7 dma byte count, 12-7 source address, 12-6 dram asynchronous address and control, 11-5 dacr, 11-5 dcr, 11-4 dmr, 11-7 mode signals, 11-4 general operation, 11-3 synchronous dacr, 11-20 dcr, 11-19 dmr, 11-22 mode settings, 11-33 i 2 c address, 8-6 control, 8-8 data i/o, 8-10 frequency divider, 8-7 status, 8-9 i2cr, 8-8 i2dr, 8-10 i2sr, 8-9 iadr, 8-6 ifdr, 8-7 interrupt controller autovector, 9-5 pending and mask, 9-6 port assignment, 9-7 ipr and imr, 9-6 irqpar, 9-7 jtag f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-20 mcf5307 users manual boundary scan, 19-7 bypass, 19-10 descriptions, 19-4 idcode, 19-6 instruction shift, 19-5 mac status, 1-14, 2-29 mask, 2-29 mbar, 6-4 mpark, 6-11 output port command, 14-15 padat, 15-2 paddr, 15-2 par, 6-10, 15-1 parallel port data, 15-2 pin assignment, 6-10, 15-1 pll control, 7-3 pllcr, 7-3 read control, 5-36 read debug module, 5-38 reset status, 6-5 rsr, 6-5 s bit, 1-12 sdram mode initialization, 11-38 sim base address, 6-4 memory map, 6-3 software watchdog interrupt, 6-9 status, 2-29 swivr, 6-9 swsr, 6-9 sypcr, 6-8 system protection control, 6-8 tcr, 13-4 ter, 13-5 timer module capture, 13-4 event, 13-5 mode, 13-3 reference, 13-4 tmr, 13-3 trigger definition, 5-14 uacr, 14-12 uart modules, 14-2?14-16 ucr, 14-9 ucsr, 14-8 udu/udl, 14-14 uip, 14-15 uipcr, 14-12 uisr, 14-13 uivr, 14-15 vector base, 2-30 write control, 5-37 write debug module, 5-39 rsti timing, 7-5 s sdram block diagram and major components, 11-2 controller registers, a-3 dacr initialization, 11-35 dcr initialization, 11-35 definitions, 11-2 dmr initialization, 11-37 example, 11-34 initialization code, 11-39 interface configuration, 11-35 mode register initialization, 11-38 overview, 11-1 signal descriptions, 17-1 address bus, 17-7 configuration, 17-14 strobe, 17-9 bus arbitration, 17-12 clock output, 17-13 data, 17-8 driven, 17-13 grant, 17-12 request, 17-12 chip-select module, 17-15 clock, 17-13 clock and reset signals divide control, 17-15 data bus, 17-8 data/configuration pins, 17-13 debug high impedance, 17-20 jtag, 17-21 processor clock output, 17-20 test clock, 17-23 mode, 17-20 overview, 17-20 dma controller module, 17-17 dram controller address strobes, 17-16 overview, 17-16 synchronous clock enable, 17-17 column address strobe, 17-17 edge select, 17-17 row address strobe, 17-17 write, 17-17 i 2 c module general, 17-19 serial data and clock, 17-19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index index-21 interrupt control signals, 17-12 request, 17-12 jtag, 19-2 parallel i/o port, 17-19 read/write, 17-8 reset in, out, 17-13 serial module general, 17-18 receiver serial data input, 17-18 send, 17-18 transmitter serial data output, 17-18 size, 17-8 timer module, 17-18 transfer acknowledge, 17-9 in progress, 17-10 modifier, 17-10 start, 17-9 signals overview, 17-1 sim features, 6-1 programming model, 6-3 register memory map, 6-3 software watchdog interrupt vector register, 6-9 service register, 6-9 timer, 6-6 stop instruction, 5-4, 5-17 system protection control register, 6-8 t timer module calculating time-out values, 13-7 capture registers, 13-4 code example, 13-6 counters, 13-5 event registers, 13-5 general-purpose programming model, 13-2 mode registers, 13-3 reference registers, 13-4 timing mac unit instructions, 3-5 pll, 7-4 rsti , 7-5 transfers generated internally, 6-12 u uart modules bus operation interrupt acknowledge cycles, 14-28 read cycles, 14-28 write cycles, 14-28 clock source baud rates, 14-19 external clock, 14-19 fifo stack in uart0, 14-24 initialization sequence, 14-29 looping modes, 14-25 automatic echo, 14-25 local loop-back, 14-25 remote loop-back, 14-26 mode registers, 14-4 multidrop mode, 14-26 programming, 14-28 receiver enabled, 14-22 register description, 14-2 serial overview, 14-2 signal definitions, 14-16 transmitter/receiver clock source, 14-18 modes, 14-19 transmitting in uart mode, 14-21 user programming model, 2-27 v variant address, 5-5 vector base register, 2-30 w wddata execution, 5-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-22 mcf5307 users manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 a part ii part iv part iii 6 glo ind part i overview coldfire core hardware multiply/accumulate (mac) unit local memory debug support sim overview phase-locked loop (pll) i 2 c module interrupt controller chip-select module synchronous/asynchronous dram controller module dma controller module timer module uart modules parallel port (general-purpose i/o) mechanical data signal descriptions bus operation ieee 1149.1 test access port (jtag) electrical specifications part i: mcf5307 processor core part ii: system integration module ( sim) part iv: hardware interface part iii: peripheral module glossary of terms and abbreviations index appendix: memory map b 20 glo ind ind f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
overview coldfire core hardware multiply/accumulate (mac) unit local memory debug support sim overview phase-locked loop (pll) i 2 c module interrupt controller chip-select module synchronous/asynchronous dram controller module dma controller module timer module uart modules parallel port (general-purpose i/o) mechanical data signal descriptions bus operation ieee 1149.1 test access port (jtag) electrical specifications part i: mcf5307 processor core part ii: system integration module ( sim) part iv: hardware interface part iii: peripheral module glossary of terms and abbreviations index appendix: memory map 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 a part ii part iv part iii 6 part i 20 glo ind f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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